Fixes regression of simple_gen test.
Also extended ivl_lpm_size API call to support all LPM types. This
simplifies some of the VHDL LPM generation code a little.
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
For example:
-- Generated from Verilog module child (vhdl_tests/generics.v:30)
-- MY_VALUE = 3
entity child is
To make it clear which values were used for this entity.
Conflicts:
tgt-vhdl/scope.cc
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
For example:
-- Generated from Verilog module child (vhdl_tests/generics.v:30)
-- MY_VALUE = 3
entity child is
To make it clear which values were used for this entity.
The function draw_scope was extracting the input/output parameters
just by looking at the (unordered) list of signals in the function
scope rather than using the ivl_scope_ports list.
This patch adds code to generate process-local variables
for scopes of type IVL_SCT_BLOCK. This also handles using
the correct assignment operator (:=) for the local VHDL
variables.
This avoids generating invalid VHDL signal names in the
following cases:
- The name begins or ends with an underscore
- The name contains two consecutive underscores
- The name is the same as a component declaration
- The name differs from another only in case
This fixes a bug where temporary variables could be declared
more than once.
It also takes out a debugging print statement I accidentally
left in the last patch.
I forgot to modify the LPM generating code with the
last patch. This *should* now always ensure a signal
is readable before code is generated to read from it.
This patch corrects several bugs with the generation of
VHDL `buffer' ports. The code generator should now
generate a buffer only if the port needs to be read inside
the architecture, otherwise it will stay `out'.
This also correct a bug where an output port is connected
directly to the output of an instantiated component. Generating
`buffer's would work here, but a more idiomatic VHDL approach is
to declare an intermediate signal which both outputs are connected
to. This is implemented in the patch (fixes the regression of
readout.v in the testsuite).
This is a fix for pr2527366 where draw_nexus would sometimes
generate code to drive an input from in an input (where they
should have been left unconnected)
Specifying -pdepth=N only outputs entities that correspond
to Verilog modules found at depth < N in the hierarchy.
Setting -pdepth=0 (the default) outputs all entities.
This is for feature request 2391457
This prints out an error message rather than crashing out with
an assertion failure when a function assigns to a non-local
variable, which cannot be done in VHDL.
If a module's input was connected to a nexus that contained
a constant driver. That constant would be incorrectly generated
as an assignment to the input *inside* the child module (instead
of an assignment inside the instantiating module).
Fix for pr2224949
The compiler generates a concatenation LPM to zero-pad ports when the
signal widths don't match up. However, when the VHDL generator generated
the input signals to this LPM it incorrectly sized them to be the width
of the result.
make_safe_name now makes sure a VHDL signal is never given a
name that conflicts with any reserved words. If it does, we
just prepend VL_.
(This code was already present, but the full list of reserved
words wasn't.)
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. This patch set covers the tgt-vhdl
directory, and was tested by Nick.
Generate scopes were previously ignored, and this would cause a segfault
later on. This patch gives an error whenever it encounters a generate
scope. This should be removed once generate statements are implemented.
Previously this was handled by creating an internal
signal that was connected to the output and could also
be read inside the entity. The correct solution is to
make the output `buffer' rather than `out'. However, this
does not work in the case when an output is connected to
an output of a child entity, and that values is read
in the parent. In this case *both* the outputs of the child
and the parent need to be made `buffer'.
Larry Doolittle
Nick Gasson
Cary R
Stephen Williams