luke
/
icestorm
mirror of https://github.com/YosysHQ/icestorm.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
824 Commits 1 Branch 1 Tag 6.6 MiB
Commit Graph

127 Commits

Author SHA1 Message Date
Miodrag Milanovic 9880f6e2dd Update variable name to PYTHON3 2021-09-06 11:11:52 +02:00
Miodrag Milanović f14a7fb4ca
Merge pull request #239 from xobs/python-bin-name 
Use $(PYTHON) in Makefiles instead of `python3`
 2021-09-06 11:08:23 +02:00
Nils Albartus d969c333d0 added I2C and SPI for u4k to database 2020-12-04 16:47:05 +01:00
Sean Cross 7597e5e3fa icefuzz: update Makefile to use $(PYTHON) variable 
Don't hardcode `python3` as the name of the Python interpreter.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-22 14:09:16 +08:00
Simon Schubert 56978cde58 add RGB_DRV/LED_DRV_CUR for u4k 2019-06-10 13:06:11 +02:00
Simon Schubert be0bca0230 u4k: add SMCCLK cell location 
icecube uses SMCCLK.CLK to "legalize" output cells.  Unclear what this
is for, but it appears in almost all outputs.
 2019-02-22 22:35:55 +01:00
Simon Schubert d76ac32ec9 iCE40 Ultra = iCE5LP = u4k port 2019-02-22 22:35:55 +01:00
Andrew Wygle a34ef88b8e Added missing ieren entries for lm4k. 
Config SPI pins weren't present in ioctrl_lm4k.sh
 2018-05-13 11:00:26 -07:00
Andrew Wygle da18da271b [WIP] Add partial icebox support for lm4k. 2018-05-12 21:47:09 -07:00
Andrew Wygle e4d502e76c Add LM4K to icefuzz Makefile and fuzzconfig.py. 2018-05-12 21:47:09 -07:00
Andrew Wygle a39b35ac2f Add LM family support to icecube.sh 2018-05-06 10:39:40 -07:00
David Shah 6efb7f7cc2 Tidy up 2018-01-30 10:21:44 +00:00
David Shah aa2b857d73 Updated 5k timing data, icetime regression fix 2018-01-29 14:02:37 +00:00
David Shah dd49c058a5 DSP related fixes 2018-01-28 16:38:46 +00:00
David Shah 420ef041b6 More DSP timing fuzzing, start adding new tiles to icetime 2018-01-22 17:03:16 +00:00
David Shah 8a30b4bbd4 Seperate different DSP configs in timing data 2018-01-22 16:34:51 +00:00
David Shah 78e5b89e7c Fix 5k timing data 2018-01-20 17:55:51 +00:00
David Shah 4b16c3735c I³C IO reverse engineered and documented 2018-01-16 15:17:20 +00:00
David Shah a59472812c Remove seperate 5k RAM DB and share with 8k instead 
This should ensure that the 5k RAM routing entries are now complete,
fixing #115
 2018-01-16 15:17:20 +00:00
David Shah ec3ad58683 Figure out missing SPI config bits, and add to chipdb 2018-01-16 15:16:44 +00:00
David Shah 411bcc53ff Whitespace fixes 2017-11-28 11:03:47 +00:00
David Shah f1025dbd88 Add uncommitted changes and tidy up some files 2017-11-28 11:00:51 +00:00
David Shah 2219530535 Preparations for 5k icetime 2017-11-24 16:31:08 +00:00
David Shah db87f48466 Documented I2C/SPI/LEDDA_IP 2017-11-24 15:50:16 +00:00
David Shah 6b2d196cb1 All 5k IP traced 2017-11-24 15:10:40 +00:00
David Shah 39b08012bb Work on UltraPlus IP tracing 2017-11-24 14:53:39 +00:00
David Shah bd6cf518f3 Begin I2C/SPI IP reverse engineering 2017-11-23 19:45:27 +00:00
David Shah da7a2a9d0d Fix whitespace and a couple of typos 2017-11-20 09:43:54 +00:00
David Shah 614c60df25 Add missing 5k BRAM bits 2017-11-17 18:29:14 +00:00
David Shah afcc653b78 Add support for UltraPlus SPRAM 2017-11-17 15:10:04 +00:00
David Shah 25ad7a24b9 5k RGB driver reverse engineered 2017-11-17 15:09:40 +00:00
David Shah 2f962ac92e Fix 5k corner routing, and reverse engineer SPRAM 2017-11-17 15:09:17 +00:00
David Shah 64e3c1a9cd Figure out DSP config bits for all locs 2017-11-17 15:08:58 +00:00
David Shah 94aa596cb1 Trace DSP routing 2017-11-17 15:08:25 +00:00
David Shah 96b527bfef Create icefuzz scripts for DSP and 5k 2017-11-17 15:07:52 +00:00
David Shah 629621642f Preparations for DSP and IpCon fuzzing 2017-11-08 16:05:42 +00:00
David Shah 5e7924c8c1 Add more 5k RAM bits to db 2017-11-05 19:14:42 +00:00
David Shah 7e58f47639 Add 5k colbuf fuzzing scripts 2017-11-02 11:48:29 +00:00
David Shah 3059607dd7 PLL configuration fuzzing script 2017-10-30 11:32:17 +00:00
David Shah e9e9d0e9cb Share glb_netwk data between 5k and 8k parts 2017-10-29 16:14:15 +00:00
David Shah 2a7c32e49a Add ColBufCtrl bits to database for 5k parts 2017-10-25 10:50:36 +01:00
David Shah 81e0d3c361 Add some verilog tests for analysing up5k features 2017-10-23 17:48:22 +01:00
David Shah bf21b64498 Fix IeRen database for up5k 2017-10-23 11:30:23 +01:00
David Shah aa653a2a51 Add DSP and IPConnect tile support to icepack and glbcheck 2017-10-21 14:59:13 +01:00
David Shah 172d561b01 Fix make_ram40 for UltraPlus 
Sometimes make_ram40 was assigning too many IO pins, causing a placment
failure, and also sometimes connecting a global clock net to WCLKE or
RCLKE which was also causing a placment failure.
 2017-10-20 16:27:06 +01:00
David Shah 42047c6114 Fix case where make_prim allocates all global buffer pins 
This is a low probability bug more likely to show up in low pin
count devices with few GBINs. In rare cases make_prim would
constrain all of the global buffer capable pins but not the clock
input. icecube would then fail to place the clock input. This is
fixed by always constraining the clock if all GBIN pins are used.
 2017-10-20 15:18:39 +01:00
David Shah 4a930377f0 Quick fix of pin 23 issue (pending further discussion) 2017-10-20 14:46:24 +01:00
Larry Doolittle b3d35ccadc Squelch trailing whitespace 2017-08-01 14:43:15 +02:00
Clifford Wolf b888b750a6 Fix some bugs in two of the icefuzz make_*.py scripts 2017-07-31 15:56:58 +02:00
Clifford Wolf ea0e19f3d3 Fix icecube.sh to work with lin and lin64 dirs, remove hardcoded ICECUBEDIR= 2017-07-31 15:56:25 +02:00