Add some verilog tests for analysing up5k features

This commit is contained in:
David Shah 2017-10-23 17:48:22 +01:00
parent bf21b64498
commit 81e0d3c361
8 changed files with 216 additions and 0 deletions

3
icefuzz/tests/intosc.pcf Normal file
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set_io clkhfpu 2
set_io clkhfen 3
set_io clkhf 4

14
icefuzz/tests/intosc.v Normal file
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module top (
input clkhfpu,
input clkhfen,
output clkhf
);
SB_HFOSC #(
.CLKHF_DIV("0b10")
) hfosc (
.CLKHFPU(clkhfpu),
.CLKHFEN(clkhfen),
.CLKHF(clkhf)
);
endmodule

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# set_io pin 1
set_io pin 39
# set_io pin
# set_io latch_in
# set_io clk_in
# set_io clk_out
# set_io oen
# set_io dout_0
# set_io dout_1
# set_io din_0
# set_io din_1

62
icefuzz/tests/sb_io_od.v Normal file
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//`define CONN_INTERNAL_BITS
`define PINTYPE 6'b010001
// `define IOSTANDARD "SB_LVCMOS"
`define IOSTANDARD "SB_LVCMOS"
// The following IO standards are just aliases for SB_LVCMOS
// `define IOSTANDARD "SB_LVCMOS25_16"
// `define IOSTANDARD "SB_LVCMOS25_12"
// `define IOSTANDARD "SB_LVCMOS25_8"
// `define IOSTANDARD "SB_LVCMOS25_4"
// `define IOSTANDARD "SB_LVCMOS18_10"
// `define IOSTANDARD "SB_LVCMOS18_8"
// `define IOSTANDARD "SB_LVCMOS18_4"
// `define IOSTANDARD "SB_LVCMOS18_2"
// `define IOSTANDARD "SB_LVCMOS15_4"
// `define IOSTANDARD "SB_LVCMOS15_2"
// `define IOSTANDARD "SB_MDDR10"
// `define IOSTANDARD "SB_MDDR8"
// `define IOSTANDARD "SB_MDDR4"
// `define IOSTANDARD "SB_MDDR2"
`ifdef CONN_INTERNAL_BITS
module top (
inout pin,
input latch_in,
input clk_in,
input clk_out,
input oen,
input dout_0,
input dout_1,
output din_0,
output din_1
);
`else
module top(pin);
inout pin;
wire latch_in = 0;
wire clk_in = 0;
wire clk_out = 0;
wire oen = 0;
wire dout_0 = 0;
wire dout_1 = 0;
wire din_0;
wire din_1;
`endif
SB_IO_OD #(
.PIN_TYPE(`PINTYPE),
.NEG_TRIGGER(1'b0)
) IO_PIN_I (
.PACKAGEPIN(pin),
.LATCHINPUTVALUE(latch_in),
.CLOCKENABLE(clk_en),
.INPUTCLK(clk_in),
.OUTPUTCLK(clk_out),
.OUTPUTENABLE(oen),
.DOUT0(dout_0),
.DOUT1(dout_1),
.DIN0(din_0),
.DIN1(din_1)
);
endmodule

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icefuzz/tests/sb_mac16.v Normal file
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module top(
input clk,
input rst,
input [7:0] a,
input [7:0] b,
output [15:0] y);
wire co;
wire [31:0] out;
SB_MAC16 i_sbmac16
(
.A(a),
.B(b),
.C(8'd0),
.D(8'd0),
.O(out),
.CLK(clk),
.IRSTTOP(rst),
.IRSTBOT(rst),
.ORSTTOP(rst),
.ORSTBOT(rst),
.AHOLD(1'b0),
.BHOLD(1'b0),
.CHOLD(1'b0),
.DHOLD(1'b0),
.OHOLDTOP(1'b0),
.OHOLDBOT(1'b0),
.OLOADTOP(1'b0),
.OLOADBOT(1'b0),
.ADDSUBTOP(1'b0),
.ADDSUBBOT(1'b0),
.CO(co),
.CI(1'b0),
.ACCUMCI(),
.ACCUMCO(),
.SIGNEXTIN(),
.SIGNEXTOUT()
);
//Config: mult_8x8_pipeline_unsigned
defparam i_sbmac16. B_SIGNED = 1'b0;
defparam i_sbmac16. A_SIGNED = 1'b0;
defparam i_sbmac16. MODE_8x8 = 1'b1;
defparam i_sbmac16. BOTADDSUB_CARRYSELECT = 2'b00;
defparam i_sbmac16. BOTADDSUB_UPPERINPUT = 1'b0;
defparam i_sbmac16. BOTADDSUB_LOWERINPUT = 2'b00;
defparam i_sbmac16. BOTOUTPUT_SELECT = 2'b10;
defparam i_sbmac16. TOPADDSUB_CARRYSELECT = 2'b00;
defparam i_sbmac16. TOPADDSUB_UPPERINPUT = 1'b0;
defparam i_sbmac16. TOPADDSUB_LOWERINPUT = 2'b00;
defparam i_sbmac16. TOPOUTPUT_SELECT = 2'b10;
defparam i_sbmac16. PIPELINE_16x16_MULT_REG2 = 1'b0;
defparam i_sbmac16. PIPELINE_16x16_MULT_REG1 = 1'b1;
defparam i_sbmac16. BOT_8x8_MULT_REG = 1'b1;
defparam i_sbmac16. TOP_8x8_MULT_REG = 1'b1;
defparam i_sbmac16. D_REG = 1'b0;
defparam i_sbmac16. B_REG = 1'b1;
defparam i_sbmac16. A_REG = 1'b1;
defparam i_sbmac16. C_REG = 1'b0;
assign y = out[15:0];
endmodule

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set_io r_led 39
set_io g_led 40
set_io b_led 41

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module top(
input r_in,
input g_in,
input b_in,
output r_led,
output g_led,
output b_led);
wire curren;
wire rgbleden;
SB_RGBA_DRV RGBA_DRIVER (
.CURREN(curren),
.RGBLEDEN(rgbleden),
.RGB0PWM(r_in),
.RGB1PWM(r_in),
.RGB2PWM(r_in),
.RGB0(r_led),
.RGB1(g_led),
.RGB2(b_led)
);
defparam RGBA_DRIVER.CURRENT_MODE = "0b0";
defparam RGBA_DRIVER.RGB0_CURRENT = "0b000011";
defparam RGBA_DRIVER.RGB1_CURRENT = "0b001111";
defparam RGBA_DRIVER.RGB2_CURRENT = "0b111111";
assign curren = 1'b1;
assign rgbleden = 1'b1;
endmodule

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module top(
input clk,
input [13:0] addr,
input [7:0] din,
input wren,
input cs,
output [7:0] dout
);
SB_SPRAM256KA spram_i
(
.ADDRESS(addr),
.DATAIN(din),
.MASKWREN(4'b1111),
.WREN(wren),
.CHIPSELECT(cs),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b0),
.DATAOUT(dout)
);
endmodule