mirror of https://github.com/YosysHQ/icestorm.git
Tidy up
This commit is contained in:
David Shah
parent
a5849e3ba8
commit
6efb7f7cc2
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@ -1,768 +0,0 @@
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Reading file 'sb_io_i3c.asc'..
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Fabric size (without IO tiles): 24 x 30
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.io_tile 1 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 2 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 3 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 4 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 5 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 6 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 7 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 8 0
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IOB_0 PINTYPE_0
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IoCtrl IE_1
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IoCtrl REN_1
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IoCtrl cf_bit_35
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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buffer io_0/D_IN_0 span12_vert_0
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.io_tile 9 0
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IOB_0 PINTYPE_0
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IOB_1 PINTYPE_0
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IoCtrl IE_0
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IoCtrl IE_1
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IoCtrl REN_0
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IoCtrl REN_1
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IoCtrl cf_bit_35
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IoCtrl cf_bit_39
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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buffer io_0/D_IN_0 span12_vert_8
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buffer io_1/D_IN_0 span12_vert_4
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.io_tile 10 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 11 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 12 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 13 0
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IOB_1 PINTYPE_0
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IoCtrl IE_0
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IoCtrl REN_0
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IoCtrl cf_bit_39
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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buffer io_1/D_IN_0 span12_vert_4
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.io_tile 14 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 15 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 16 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 17 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 18 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 19 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 20 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 21 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 22 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 23 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 24 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 1 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 2 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 3 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 4 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 5 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 6 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 7 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 8 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 9 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 10 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 11 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 12 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 13 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 14 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 15 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 16 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 17 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 18 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 19 31
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IOB_0 PINTYPE_0
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IOB_1 PINTYPE_0
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IoCtrl cf_bit_32
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IoCtrl cf_bit_36
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 20 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 21 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 22 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 23 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 24 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.logic_tile 8 1
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routing sp12_v_b_0 sp12_v_t_23
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.logic_tile 9 3
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routing sp12_v_b_0 sp12_h_r_0
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.logic_tile 13 3
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routing sp12_v_b_0 sp12_h_r_0
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.logic_tile 21 3
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routing sp12_h_l_23 sp12_v_t_23
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.logic_tile 9 5
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routing sp12_v_b_0 sp12_h_r_0
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.logic_tile 21 5
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routing sp12_h_l_23 sp12_v_t_23
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.logic_tile 8 13
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routing sp12_v_b_0 sp12_v_t_23
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.logic_tile 21 15
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routing sp12_v_b_0 sp12_v_t_23
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.logic_tile 21 17
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routing sp12_v_b_0 sp12_v_t_23
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.logic_tile 21 22
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buffer sp12_v_b_15 sp4_v_b_19
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.logic_tile 21 23
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routing sp4_v_b_6 sp4_h_r_0
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.logic_tile 8 25
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routing sp12_v_b_0 sp12_h_r_0
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.logic_tile 18 25
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buffer sp12_h_r_20 sp4_h_r_22
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.logic_tile 21 25
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routing sp4_h_l_46 sp4_h_r_7
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.logic_tile 21 27
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routing sp12_v_b_0 sp12_h_r_0
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.dsp0_tile 25 15
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routing sp12_v_b_0 sp12_v_t_23
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.dsp0_tile 25 23
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routing sp4_h_l_37 sp4_v_t_37
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.dsp2_tile 25 25
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routing sp4_h_l_42 sp4_v_t_37
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.ipcon_tile 0 1
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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.ipcon_tile 25 1
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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.ipcon_tile 0 2
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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.ipcon_tile 25 2
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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.ipcon_tile 0 3
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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.ipcon_tile 25 3
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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routing sp12_h_l_23 sp12_v_t_23
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.ipcon_tile 0 4
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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.ipcon_tile 25 4
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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.ipcon_tile 0 9
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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.ipcon_tile 25 9
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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.ipcon_tile 0 14
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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.ipcon_tile 0 19
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 19
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 20
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 20
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 21
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 21
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 22
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 22
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 27
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 27
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
buffer local_g0_0 lutff_4/in_0
|
||||
buffer local_g1_0 lutff_7/in_0
|
||||
buffer local_g2_0 lutff_6/in_0
|
||||
buffer local_g3_0 lutff_5/in_0
|
||||
buffer sp12_h_r_8 local_g0_0
|
||||
buffer sp12_v_b_0 local_g3_0
|
||||
buffer sp4_v_b_0 local_g1_0
|
||||
buffer sp4_v_b_24 local_g2_0
|
||||
|
||||
.ipcon_tile 0 28
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 28
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 29
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 29
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 30
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 30
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
|
|
@ -1,108 +0,0 @@
|
|||
# ******************************************************************************
|
||||
|
||||
# iCEcube Static Timer
|
||||
|
||||
# Version: 2017.08.27940
|
||||
|
||||
# Build Date: Sep 12 2017 08:03:55
|
||||
|
||||
# File Generated: Jan 13 2018 18:40:35
|
||||
|
||||
# Purpose: Timing Report with critical paths info
|
||||
|
||||
# Copyright (C) 2006-2010 by Lattice Semiconductor Corp. All rights reserved.
|
||||
|
||||
# ******************************************************************************
|
||||
|
||||
Device: iCE40UP5KUP5K
|
||||
Derating factors (Best:Typical:Worst) :- ( 1 : 1 : 1 )
|
||||
Derating factor used to generate this timing report: Worst
|
||||
Based on the following operating conditions
|
||||
Junction Temperature(degree Celsius): 0
|
||||
Core Voltage(V): -1
|
||||
Process Corner: Worst
|
||||
NOTE:
|
||||
Please check both worst-case and best-case scenarios for "Setup Times"
|
||||
and "Hold Times" checks
|
||||
Maximum Operating Frequency is: N/A
|
||||
|
||||
|
||||
#####################################################################
|
||||
3::Datasheet Report
|
||||
|
||||
All values are in Picoseconds
|
||||
=====================================================================
|
||||
|
||||
3.1::Setup Times
|
||||
----------------
|
||||
|
||||
Data Port Clock Port Setup Times Clock Reference:Phase
|
||||
--------- ---------- ----------- ---------------------
|
||||
|
||||
|
||||
3.2::Clock to Out
|
||||
-----------------
|
||||
|
||||
Data Port Clock Port Clock to Out Clock Reference:Phase
|
||||
--------- ---------- ------------ ---------------------
|
||||
|
||||
|
||||
3.3::Pad to Pad
|
||||
---------------
|
||||
|
||||
Port Name (Input) Port Name (Output) Pad to Pad
|
||||
----------------- ------------------ ----------
|
||||
|
||||
|
||||
3.4::Hold Times
|
||||
---------------
|
||||
|
||||
Data Port Clock Port Hold Times Clock Reference:Phase
|
||||
--------- ---------- ---------- ---------------------
|
||||
|
||||
|
||||
3.5::Minimum Clock to Out
|
||||
-------------------------
|
||||
|
||||
Data Port Clock Port Minimum Clock to Out Clock Reference:Phase
|
||||
--------- ---------- -------------------- ---------------------
|
||||
|
||||
|
||||
3.6::Minimum Pad To Pad
|
||||
-----------------------
|
||||
|
||||
Port Name (Input) Port Name (Output) Minimum Pad To Pad
|
||||
----------------- ------------------ ------------------
|
||||
|
||||
=====================================================================
|
||||
End of Datasheet Report
|
||||
#####################################################################
|
||||
|
||||
#####################################################################
|
||||
6::Path Details for DataSheet
|
||||
=====================================================================
|
||||
|
||||
|
||||
|
||||
=====================================================================
|
||||
End of Path Details for Datasheet
|
||||
#####################################################################
|
||||
|
||||
#####################################################################
|
||||
Detailed Setup Report for all timing paths
|
||||
=====================================================================
|
||||
=====================================================================
|
||||
End of Detailed Setup Report for all timing paths
|
||||
#####################################################################
|
||||
|
||||
#####################################################################
|
||||
Detailed Hold Report for all timing paths
|
||||
=====================================================================
|
||||
=====================================================================
|
||||
End of Detailed Hold Report for all timing paths
|
||||
#####################################################################
|
||||
|
||||
#####################################################################
|
||||
End of Timing Report
|
||||
#####################################################################
|
||||
|
||||
|
|
@ -1,278 +0,0 @@
|
|||
// Reading file 'sb_io_i3c.asc'..
|
||||
|
||||
module chip (input pin_23_puen, input pin_25_puen, input pin_23_wkpuen, input pin_25_wkpuen, input pin_23, input pin_25);
|
||||
|
||||
wire pin_23_puen;
|
||||
// (7, 1, 'neigh_op_bnr_0')
|
||||
// (7, 1, 'neigh_op_bnr_4')
|
||||
// (8, 0, 'io_0/D_IN_0')
|
||||
// (8, 0, 'io_0/PAD')
|
||||
// (8, 0, 'span12_vert_0')
|
||||
// (8, 1, 'neigh_op_bot_0')
|
||||
// (8, 1, 'neigh_op_bot_4')
|
||||
// (8, 1, 'sp12_v_b_0')
|
||||
// (8, 1, 'sp12_v_t_23')
|
||||
// (8, 2, 'sp12_v_b_23')
|
||||
// (8, 3, 'sp12_v_b_20')
|
||||
// (8, 4, 'sp12_v_b_19')
|
||||
// (8, 5, 'sp12_v_b_16')
|
||||
// (8, 6, 'sp12_v_b_15')
|
||||
// (8, 7, 'sp12_v_b_12')
|
||||
// (8, 8, 'sp12_v_b_11')
|
||||
// (8, 9, 'sp12_v_b_8')
|
||||
// (8, 10, 'sp12_v_b_7')
|
||||
// (8, 11, 'sp12_v_b_4')
|
||||
// (8, 12, 'sp12_v_b_3')
|
||||
// (8, 13, 'sp12_v_b_0')
|
||||
// (8, 13, 'sp12_v_t_23')
|
||||
// (8, 14, 'sp12_v_b_23')
|
||||
// (8, 15, 'sp12_v_b_20')
|
||||
// (8, 16, 'sp12_v_b_19')
|
||||
// (8, 17, 'sp12_v_b_16')
|
||||
// (8, 18, 'sp12_v_b_15')
|
||||
// (8, 19, 'sp12_v_b_12')
|
||||
// (8, 20, 'sp12_v_b_11')
|
||||
// (8, 21, 'sp12_v_b_8')
|
||||
// (8, 22, 'sp12_v_b_7')
|
||||
// (8, 23, 'sp12_v_b_4')
|
||||
// (8, 24, 'sp12_v_b_3')
|
||||
// (8, 25, 'sp12_h_r_0')
|
||||
// (8, 25, 'sp12_v_b_0')
|
||||
// (9, 1, 'neigh_op_bnl_0')
|
||||
// (9, 1, 'neigh_op_bnl_4')
|
||||
// (9, 25, 'sp12_h_r_3')
|
||||
// (10, 25, 'sp12_h_r_4')
|
||||
// (11, 25, 'sp12_h_r_7')
|
||||
// (12, 25, 'sp12_h_r_8')
|
||||
// (13, 25, 'sp12_h_r_11')
|
||||
// (14, 25, 'sp12_h_r_12')
|
||||
// (15, 25, 'sp12_h_r_15')
|
||||
// (16, 25, 'sp12_h_r_16')
|
||||
// (17, 25, 'sp12_h_r_19')
|
||||
// (17, 25, 'sp4_h_r_11')
|
||||
// (18, 25, 'sp12_h_r_20')
|
||||
// (18, 25, 'sp4_h_r_22')
|
||||
// (19, 25, 'sp12_h_r_23')
|
||||
// (19, 25, 'sp4_h_r_35')
|
||||
// (20, 25, 'sp12_h_l_23')
|
||||
// (20, 25, 'sp4_h_r_46')
|
||||
// (21, 25, 'sp4_h_l_46')
|
||||
// (21, 25, 'sp4_h_r_7')
|
||||
// (22, 25, 'sp4_h_r_18')
|
||||
// (23, 25, 'sp4_h_r_31')
|
||||
// (24, 25, 'sp4_h_r_42')
|
||||
// (24, 26, 'sp4_r_v_b_37')
|
||||
// (24, 27, 'sp4_r_v_b_24')
|
||||
// (24, 28, 'sp4_r_v_b_13')
|
||||
// (24, 29, 'sp4_r_v_b_0')
|
||||
// (25, 25, 'sp4_h_l_42')
|
||||
// (25, 25, 'sp4_v_t_37')
|
||||
// (25, 26, 'sp4_v_b_37')
|
||||
// (25, 27, 'local_g2_0')
|
||||
// (25, 27, 'lutff_6/in_0')
|
||||
// (25, 27, 'sp4_v_b_24')
|
||||
// (25, 28, 'sp4_v_b_13')
|
||||
// (25, 29, 'sp4_v_b_0')
|
||||
|
||||
wire pin_25_puen;
|
||||
// (8, 1, 'neigh_op_bnr_0')
|
||||
// (8, 1, 'neigh_op_bnr_4')
|
||||
// (9, 0, 'io_0/D_IN_0')
|
||||
// (9, 0, 'io_0/PAD')
|
||||
// (9, 0, 'span12_vert_8')
|
||||
// (9, 1, 'neigh_op_bot_0')
|
||||
// (9, 1, 'neigh_op_bot_4')
|
||||
// (9, 1, 'sp12_v_b_8')
|
||||
// (9, 2, 'sp12_v_b_7')
|
||||
// (9, 3, 'sp12_v_b_4')
|
||||
// (9, 4, 'sp12_v_b_3')
|
||||
// (9, 5, 'sp12_h_r_0')
|
||||
// (9, 5, 'sp12_v_b_0')
|
||||
// (10, 1, 'neigh_op_bnl_0')
|
||||
// (10, 1, 'neigh_op_bnl_4')
|
||||
// (10, 5, 'sp12_h_r_3')
|
||||
// (11, 5, 'sp12_h_r_4')
|
||||
// (12, 5, 'sp12_h_r_7')
|
||||
// (13, 5, 'sp12_h_r_8')
|
||||
// (14, 5, 'sp12_h_r_11')
|
||||
// (15, 5, 'sp12_h_r_12')
|
||||
// (16, 5, 'sp12_h_r_15')
|
||||
// (17, 5, 'sp12_h_r_16')
|
||||
// (18, 5, 'sp12_h_r_19')
|
||||
// (19, 5, 'sp12_h_r_20')
|
||||
// (20, 5, 'sp12_h_r_23')
|
||||
// (20, 20, 'sp4_r_v_b_43')
|
||||
// (20, 21, 'sp4_r_v_b_30')
|
||||
// (20, 22, 'sp4_r_v_b_19')
|
||||
// (20, 23, 'sp4_r_v_b_6')
|
||||
// (21, 5, 'sp12_h_l_23')
|
||||
// (21, 5, 'sp12_v_t_23')
|
||||
// (21, 6, 'sp12_v_b_23')
|
||||
// (21, 7, 'sp12_v_b_20')
|
||||
// (21, 8, 'sp12_v_b_19')
|
||||
// (21, 9, 'sp12_v_b_16')
|
||||
// (21, 10, 'sp12_v_b_15')
|
||||
// (21, 11, 'sp12_v_b_12')
|
||||
// (21, 12, 'sp12_v_b_11')
|
||||
// (21, 13, 'sp12_v_b_8')
|
||||
// (21, 14, 'sp12_v_b_7')
|
||||
// (21, 15, 'sp12_v_b_4')
|
||||
// (21, 16, 'sp12_v_b_3')
|
||||
// (21, 17, 'sp12_v_b_0')
|
||||
// (21, 17, 'sp12_v_t_23')
|
||||
// (21, 18, 'sp12_v_b_23')
|
||||
// (21, 19, 'sp12_v_b_20')
|
||||
// (21, 19, 'sp4_v_t_43')
|
||||
// (21, 20, 'sp12_v_b_19')
|
||||
// (21, 20, 'sp4_v_b_43')
|
||||
// (21, 21, 'sp12_v_b_16')
|
||||
// (21, 21, 'sp4_v_b_30')
|
||||
// (21, 22, 'sp12_v_b_15')
|
||||
// (21, 22, 'sp4_v_b_19')
|
||||
// (21, 23, 'sp12_v_b_12')
|
||||
// (21, 23, 'sp4_h_r_0')
|
||||
// (21, 23, 'sp4_v_b_6')
|
||||
// (21, 24, 'sp12_v_b_11')
|
||||
// (21, 25, 'sp12_v_b_8')
|
||||
// (21, 26, 'sp12_v_b_7')
|
||||
// (21, 27, 'sp12_v_b_4')
|
||||
// (21, 28, 'sp12_v_b_3')
|
||||
// (21, 29, 'sp12_v_b_0')
|
||||
// (22, 23, 'sp4_h_r_13')
|
||||
// (23, 23, 'sp4_h_r_24')
|
||||
// (24, 23, 'sp4_h_r_37')
|
||||
// (24, 24, 'sp4_r_v_b_37')
|
||||
// (24, 25, 'sp4_r_v_b_24')
|
||||
// (24, 26, 'sp4_r_v_b_13')
|
||||
// (24, 27, 'sp4_r_v_b_0')
|
||||
// (25, 23, 'sp4_h_l_37')
|
||||
// (25, 23, 'sp4_v_t_37')
|
||||
// (25, 24, 'sp4_v_b_37')
|
||||
// (25, 25, 'sp4_v_b_24')
|
||||
// (25, 26, 'sp4_v_b_13')
|
||||
// (25, 27, 'local_g1_0')
|
||||
// (25, 27, 'lutff_7/in_0')
|
||||
// (25, 27, 'sp4_v_b_0')
|
||||
|
||||
wire pin_23_wkpuen;
|
||||
// (8, 1, 'neigh_op_bnr_2')
|
||||
// (8, 1, 'neigh_op_bnr_6')
|
||||
// (9, 0, 'io_1/D_IN_0')
|
||||
// (9, 0, 'io_1/PAD')
|
||||
// (9, 0, 'span12_vert_4')
|
||||
// (9, 1, 'neigh_op_bot_2')
|
||||
// (9, 1, 'neigh_op_bot_6')
|
||||
// (9, 1, 'sp12_v_b_4')
|
||||
// (9, 2, 'sp12_v_b_3')
|
||||
// (9, 3, 'sp12_h_r_0')
|
||||
// (9, 3, 'sp12_v_b_0')
|
||||
// (10, 1, 'neigh_op_bnl_2')
|
||||
// (10, 1, 'neigh_op_bnl_6')
|
||||
// (10, 3, 'sp12_h_r_3')
|
||||
// (11, 3, 'sp12_h_r_4')
|
||||
// (12, 3, 'sp12_h_r_7')
|
||||
// (13, 3, 'sp12_h_r_8')
|
||||
// (14, 3, 'sp12_h_r_11')
|
||||
// (15, 3, 'sp12_h_r_12')
|
||||
// (16, 3, 'sp12_h_r_15')
|
||||
// (17, 3, 'sp12_h_r_16')
|
||||
// (18, 3, 'sp12_h_r_19')
|
||||
// (19, 3, 'sp12_h_r_20')
|
||||
// (20, 3, 'sp12_h_r_23')
|
||||
// (21, 3, 'sp12_h_l_23')
|
||||
// (21, 3, 'sp12_v_t_23')
|
||||
// (21, 4, 'sp12_v_b_23')
|
||||
// (21, 5, 'sp12_v_b_20')
|
||||
// (21, 6, 'sp12_v_b_19')
|
||||
// (21, 7, 'sp12_v_b_16')
|
||||
// (21, 8, 'sp12_v_b_15')
|
||||
// (21, 9, 'sp12_v_b_12')
|
||||
// (21, 10, 'sp12_v_b_11')
|
||||
// (21, 11, 'sp12_v_b_8')
|
||||
// (21, 12, 'sp12_v_b_7')
|
||||
// (21, 13, 'sp12_v_b_4')
|
||||
// (21, 14, 'sp12_v_b_3')
|
||||
// (21, 15, 'sp12_v_b_0')
|
||||
// (21, 15, 'sp12_v_t_23')
|
||||
// (21, 16, 'sp12_v_b_23')
|
||||
// (21, 17, 'sp12_v_b_20')
|
||||
// (21, 18, 'sp12_v_b_19')
|
||||
// (21, 19, 'sp12_v_b_16')
|
||||
// (21, 20, 'sp12_v_b_15')
|
||||
// (21, 21, 'sp12_v_b_12')
|
||||
// (21, 22, 'sp12_v_b_11')
|
||||
// (21, 23, 'sp12_v_b_8')
|
||||
// (21, 24, 'sp12_v_b_7')
|
||||
// (21, 25, 'sp12_v_b_4')
|
||||
// (21, 26, 'sp12_v_b_3')
|
||||
// (21, 27, 'sp12_h_r_0')
|
||||
// (21, 27, 'sp12_v_b_0')
|
||||
// (22, 27, 'sp12_h_r_3')
|
||||
// (23, 27, 'sp12_h_r_4')
|
||||
// (24, 27, 'sp12_h_r_7')
|
||||
// (25, 27, 'local_g0_0')
|
||||
// (25, 27, 'lutff_4/in_0')
|
||||
// (25, 27, 'sp12_h_r_8')
|
||||
|
||||
wire pin_25_wkpuen;
|
||||
// (12, 1, 'neigh_op_bnr_2')
|
||||
// (12, 1, 'neigh_op_bnr_6')
|
||||
// (13, 0, 'io_1/D_IN_0')
|
||||
// (13, 0, 'io_1/PAD')
|
||||
// (13, 0, 'span12_vert_4')
|
||||
// (13, 1, 'neigh_op_bot_2')
|
||||
// (13, 1, 'neigh_op_bot_6')
|
||||
// (13, 1, 'sp12_v_b_4')
|
||||
// (13, 2, 'sp12_v_b_3')
|
||||
// (13, 3, 'sp12_h_r_0')
|
||||
// (13, 3, 'sp12_v_b_0')
|
||||
// (14, 1, 'neigh_op_bnl_2')
|
||||
// (14, 1, 'neigh_op_bnl_6')
|
||||
// (14, 3, 'sp12_h_r_3')
|
||||
// (15, 3, 'sp12_h_r_4')
|
||||
// (16, 3, 'sp12_h_r_7')
|
||||
// (17, 3, 'sp12_h_r_8')
|
||||
// (18, 3, 'sp12_h_r_11')
|
||||
// (19, 3, 'sp12_h_r_12')
|
||||
// (20, 3, 'sp12_h_r_15')
|
||||
// (21, 3, 'sp12_h_r_16')
|
||||
// (22, 3, 'sp12_h_r_19')
|
||||
// (23, 3, 'sp12_h_r_20')
|
||||
// (24, 3, 'sp12_h_r_23')
|
||||
// (25, 3, 'sp12_h_l_23')
|
||||
// (25, 3, 'sp12_v_t_23')
|
||||
// (25, 4, 'sp12_v_b_23')
|
||||
// (25, 5, 'sp12_v_b_20')
|
||||
// (25, 6, 'sp12_v_b_19')
|
||||
// (25, 7, 'sp12_v_b_16')
|
||||
// (25, 8, 'sp12_v_b_15')
|
||||
// (25, 9, 'sp12_v_b_12')
|
||||
// (25, 10, 'sp12_v_b_11')
|
||||
// (25, 11, 'sp12_v_b_8')
|
||||
// (25, 12, 'sp12_v_b_7')
|
||||
// (25, 13, 'sp12_v_b_4')
|
||||
// (25, 14, 'sp12_v_b_3')
|
||||
// (25, 15, 'sp12_v_b_0')
|
||||
// (25, 15, 'sp12_v_t_23')
|
||||
// (25, 16, 'sp12_v_b_23')
|
||||
// (25, 17, 'sp12_v_b_20')
|
||||
// (25, 18, 'sp12_v_b_19')
|
||||
// (25, 19, 'sp12_v_b_16')
|
||||
// (25, 20, 'sp12_v_b_15')
|
||||
// (25, 21, 'sp12_v_b_12')
|
||||
// (25, 22, 'sp12_v_b_11')
|
||||
// (25, 23, 'sp12_v_b_8')
|
||||
// (25, 24, 'sp12_v_b_7')
|
||||
// (25, 25, 'sp12_v_b_4')
|
||||
// (25, 26, 'sp12_v_b_3')
|
||||
// (25, 27, 'local_g3_0')
|
||||
// (25, 27, 'lutff_5/in_0')
|
||||
// (25, 27, 'sp12_v_b_0')
|
||||
|
||||
// Debug Symbols
|
||||
|
||||
|
||||
// Warning: unmatched port 'pin_23'
|
||||
// Warning: unmatched port 'pin_25'
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue