mirror of https://github.com/YosysHQ/icestorm.git
Documented I2C/SPI/LEDDA_IP
This commit is contained in:
David Shah
parent
6b2d196cb1
commit
db87f48466
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@ -1,19 +1,36 @@
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<!DOCTYPE html>
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<html><head><meta charset="UTF-8">
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<style>
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.multitab {
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margin-left: auto;
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padding-left: 10px;
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vertical-align: top;
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.ctab td, .ctab th, .cstab th, .cstab td {
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.ctab td {
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.ctab td, .cstab td {
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font-family:monospace;
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}
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</style>
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<title>Project IceStorm – UltraPlus Features Documentation</title>
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</head><body>
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@ -264,4 +281,135 @@ can be used as an open-drain IO using the standard IO cell.</p>
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<tr><td>100kΩ<br/>(default)</td><td>!cf_bit_35<br/>!B6[15]</td><td>!cf_bit_39<br/>!B12[15]</td></tr>
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</table>
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<h2>Hard IP</h2>
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<p>The UltraPlus devices contain three types of Hard IP: I<sup>2</sup>C (<span style="font-family:monospace">SB_I2C</span>), SPI (<span style="font-family:monospace">SB_SPI</span>), and LED PWM generation
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(<span style="font-family:monospace">SB_LEDDA_IP</span>). The connections and configurations for each of these blocks are documented below.</p>
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<table class="multitab"><tr><td>
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<table class="cstab">
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<tr><th>Signal</th><th>I2C<br/>(0, 31, 0)</th><th>I2C<br/>(25, 31, 0)</th></tr>
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<tr><td>SBACKO</td><td>(0, 30, slf_op_6)</td><td>(25, 30, slf_op_6)</td></tr>
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<tr><td>SBADRI0</td><td>(0, 30, lutff_1/in_0)</td><td>(25, 30, lutff_1/in_0)</td></tr>
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<tr><td>SBADRI1</td><td>(0, 30, lutff_2/in_0)</td><td>(25, 30, lutff_2/in_0)</td></tr>
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<tr><td>SBADRI2</td><td>(0, 30, lutff_3/in_0)</td><td>(25, 30, lutff_3/in_0)</td></tr>
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<tr><td>SBADRI3</td><td>(0, 30, lutff_4/in_0)</td><td>(25, 30, lutff_4/in_0)</td></tr>
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<tr><td>SBADRI4</td><td>(0, 30, lutff_5/in_0)</td><td>(25, 30, lutff_5/in_0)</td></tr>
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<tr><td>SBADRI5</td><td>(0, 30, lutff_6/in_0)</td><td>(25, 30, lutff_6/in_0)</td></tr>
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<tr><td>SBADRI6</td><td>(0, 30, lutff_7/in_0)</td><td>(25, 30, lutff_7/in_0)</td></tr>
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<tr><td>SBADRI7</td><td>(0, 29, lutff_2/in_0)</td><td>(25, 29, lutff_2/in_0)</td></tr>
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<tr><td>SBCLKI</td><td>(0, 30, clk)</td><td>(25, 30, clk)</td></tr>
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<tr><td>SBDATI0</td><td>(0, 29, lutff_5/in_0)</td><td>(25, 29, lutff_5/in_0)</td></tr>
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<tr><td>SBDATI1</td><td>(0, 29, lutff_6/in_0)</td><td>(25, 29, lutff_6/in_0)</td></tr>
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<tr><td>SBDATI2</td><td>(0, 29, lutff_7/in_0)</td><td>(25, 29, lutff_7/in_0)</td></tr>
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<tr><td>SBDATI3</td><td>(0, 30, lutff_0/in_3)</td><td>(25, 30, lutff_0/in_3)</td></tr>
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<tr><td>SBDATI4</td><td>(0, 30, lutff_5/in_1)</td><td>(25, 30, lutff_5/in_1)</td></tr>
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<tr><td>SBDATI5</td><td>(0, 30, lutff_6/in_1)</td><td>(25, 30, lutff_6/in_1)</td></tr>
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<tr><td>SBDATI6</td><td>(0, 30, lutff_7/in_1)</td><td>(25, 30, lutff_7/in_1)</td></tr>
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<tr><td>SBDATI7</td><td>(0, 30, lutff_0/in_0)</td><td>(25, 30, lutff_0/in_0)</td></tr>
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<tr><td>SBDATO0</td><td>(0, 29, slf_op_6)</td><td>(25, 29, slf_op_6)</td></tr>
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<tr><td>SBDATO1</td><td>(0, 29, slf_op_7)</td><td>(25, 29, slf_op_7)</td></tr>
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<tr><td>SBDATO2</td><td>(0, 30, slf_op_0)</td><td>(25, 30, slf_op_0)</td></tr>
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<tr><td>SBDATO3</td><td>(0, 30, slf_op_1)</td><td>(25, 30, slf_op_1)</td></tr>
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<tr><td>SBDATO4</td><td>(0, 30, slf_op_2)</td><td>(25, 30, slf_op_2)</td></tr>
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<tr><td>SBDATO5</td><td>(0, 30, slf_op_3)</td><td>(25, 30, slf_op_3)</td></tr>
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<tr><td>SBDATO6</td><td>(0, 30, slf_op_4)</td><td>(25, 30, slf_op_4)</td></tr>
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<tr><td>SBDATO7</td><td>(0, 30, slf_op_5)</td><td>(25, 30, slf_op_5)</td></tr>
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<tr><td>SBRWI</td><td>(0, 29, lutff_4/in_0)</td><td>(25, 29, lutff_4/in_0)</td></tr>
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<tr><td>SBSTBI</td><td>(0, 29, lutff_3/in_0)</td><td>(25, 29, lutff_3/in_0)</td></tr>
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<tr><td>I2CIRQ</td><td>(0, 30, slf_op_7)</td><td>(25, 30, slf_op_7)</td></tr>
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<tr><td>I2CWKUP</td><td>(0, 29, slf_op_5)</td><td>(25, 29, slf_op_5)</td></tr>
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<tr><td>SCLI</td><td>(0, 29, lutff_2/in_1)</td><td>(25, 29, lutff_2/in_1)</td></tr>
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<tr><td>SCLO</td><td>(0, 29, slf_op_3)</td><td>(25, 29, slf_op_3)</td></tr>
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<tr><td>SCLOE</td><td>(0, 29, slf_op_4)</td><td>(25, 29, slf_op_4)</td></tr>
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<tr><td>SDAI</td><td>(0, 29, lutff_1/in_1)</td><td>(25, 29, lutff_1/in_1)</td></tr>
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<tr><td>SDAO</td><td>(0, 29, slf_op_1)</td><td>(25, 29, slf_op_1)</td></tr>
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<tr><td>SDAOE</td><td>(0, 29, slf_op_2)</td><td>(25, 29, slf_op_2)</td></tr>
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<tr><td><em>I2C_ENABLE_0</em></td><td><em>(13, 31, cbit2usealt_in_0)</em></td><td><em>(19, 31, cbit2usealt_in_0)</em></td></tr>
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<tr><td><em>I2C_ENABLE_1</em></td><td><em>(12, 31, cbit2usealt_in_1)</em></td><td><em>(19, 31, cbit2usealt_in_1)</em></td></tr>
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<tr><td><em>SDA_INPUT_DELAYED</em></td><td><em>(12, 31, SDA_input_delay)</em></td><td><em>(19, 31, SDA_input_delay)</em></td></tr>
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<tr><td><em>SDA_OUTPUT_DELAYED</em></td><td><em>(12, 31, SDA_output_delay)</em></td><td><em>(19, 31, SDA_output_delay)</em></td></tr>
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</table>
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</td><td>
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<table class="cstab">
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<tr><th>Signal</th><th>SPI<br/>(0, 0, 0)</th><th>SPI<br/>(25, 0, 1)</th></tr>
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<tr><td>SBACKO</td><td>(0, 20, slf_op_1)</td><td>(25, 20, slf_op_1)</td></tr>
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<tr><td>SBADRI0</td><td>(0, 19, lutff_1/in_1)</td><td>(25, 19, lutff_1/in_1)</td></tr>
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<tr><td>SBADRI1</td><td>(0, 19, lutff_2/in_1)</td><td>(25, 19, lutff_2/in_1)</td></tr>
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<tr><td>SBADRI2</td><td>(0, 20, lutff_0/in_3)</td><td>(25, 20, lutff_0/in_3)</td></tr>
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<tr><td>SBADRI3</td><td>(0, 20, lutff_1/in_3)</td><td>(25, 20, lutff_1/in_3)</td></tr>
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<tr><td>SBADRI4</td><td>(0, 20, lutff_2/in_3)</td><td>(25, 20, lutff_2/in_3)</td></tr>
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<tr><td>SBADRI5</td><td>(0, 20, lutff_3/in_3)</td><td>(25, 20, lutff_3/in_3)</td></tr>
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<tr><td>SBADRI6</td><td>(0, 20, lutff_4/in_3)</td><td>(25, 20, lutff_4/in_3)</td></tr>
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<tr><td>SBADRI7</td><td>(0, 20, lutff_5/in_3)</td><td>(25, 20, lutff_5/in_3)</td></tr>
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<tr><td>SBCLKI</td><td>(0, 20, clk)</td><td>(25, 20, clk)</td></tr>
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<tr><td>SBDATI0</td><td>(0, 19, lutff_1/in_3)</td><td>(25, 19, lutff_1/in_3)</td></tr>
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<tr><td>SBDATI1</td><td>(0, 19, lutff_2/in_3)</td><td>(25, 19, lutff_2/in_3)</td></tr>
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<tr><td>SBDATI2</td><td>(0, 19, lutff_3/in_3)</td><td>(25, 19, lutff_3/in_3)</td></tr>
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<tr><td>SBDATI3</td><td>(0, 19, lutff_4/in_3)</td><td>(25, 19, lutff_4/in_3)</td></tr>
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<tr><td>SBDATI4</td><td>(0, 19, lutff_5/in_3)</td><td>(25, 19, lutff_5/in_3)</td></tr>
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<tr><td>SBDATI5</td><td>(0, 19, lutff_6/in_3)</td><td>(25, 19, lutff_6/in_3)</td></tr>
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<tr><td>SBDATI6</td><td>(0, 19, lutff_7/in_3)</td><td>(25, 19, lutff_7/in_3)</td></tr>
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<tr><td>SBDATI7</td><td>(0, 19, lutff_0/in_1)</td><td>(25, 19, lutff_0/in_1)</td></tr>
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<tr><td>SBDATO0</td><td>(0, 19, slf_op_1)</td><td>(25, 19, slf_op_1)</td></tr>
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<tr><td>SBDATO1</td><td>(0, 19, slf_op_2)</td><td>(25, 19, slf_op_2)</td></tr>
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<tr><td>SBDATO2</td><td>(0, 19, slf_op_3)</td><td>(25, 19, slf_op_3)</td></tr>
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<tr><td>SBDATO3</td><td>(0, 19, slf_op_4)</td><td>(25, 19, slf_op_4)</td></tr>
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<tr><td>SBDATO4</td><td>(0, 19, slf_op_5)</td><td>(25, 19, slf_op_5)</td></tr>
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<tr><td>SBDATO5</td><td>(0, 19, slf_op_6)</td><td>(25, 19, slf_op_6)</td></tr>
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<tr><td>SBDATO6</td><td>(0, 19, slf_op_7)</td><td>(25, 19, slf_op_7)</td></tr>
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<tr><td>SBDATO7</td><td>(0, 20, slf_op_0)</td><td>(25, 20, slf_op_0)</td></tr>
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<tr><td>SBRWI</td><td>(0, 19, lutff_0/in_3)</td><td>(25, 19, lutff_0/in_3)</td></tr>
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<tr><td>SBSTBI</td><td>(0, 20, lutff_6/in_3)</td><td>(25, 20, lutff_6/in_3)</td></tr>
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<tr><td>MCSNO0</td><td>(0, 21, slf_op_2)</td><td>(25, 21, slf_op_2)</td></tr>
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<tr><td>MCSNO1</td><td>(0, 21, slf_op_4)</td><td>(25, 21, slf_op_4)</td></tr>
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<tr><td>MCSNO2</td><td>(0, 21, slf_op_7)</td><td>(25, 21, slf_op_7)</td></tr>
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<tr><td>MCSNO3</td><td>(0, 22, slf_op_1)</td><td>(25, 22, slf_op_1)</td></tr>
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<tr><td>MCSNOE0</td><td>(0, 21, slf_op_3)</td><td>(25, 21, slf_op_3)</td></tr>
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<tr><td>MCSNOE1</td><td>(0, 21, slf_op_5)</td><td>(25, 21, slf_op_5)</td></tr>
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<tr><td>MCSNOE2</td><td>(0, 22, slf_op_0)</td><td>(25, 22, slf_op_0)</td></tr>
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<tr><td>MCSNOE3</td><td>(0, 22, slf_op_2)</td><td>(25, 22, slf_op_2)</td></tr>
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<tr><td>MI</td><td>(0, 22, lutff_0/in_1)</td><td>(25, 22, lutff_0/in_1)</td></tr>
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<tr><td>MO</td><td>(0, 20, slf_op_6)</td><td>(25, 20, slf_op_6)</td></tr>
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<tr><td>MOE</td><td>(0, 20, slf_op_7)</td><td>(25, 20, slf_op_7)</td></tr>
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<tr><td>SCKI</td><td>(0, 22, lutff_1/in_1)</td><td>(25, 22, lutff_1/in_1)</td></tr>
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<tr><td>SCKO</td><td>(0, 21, slf_op_0)</td><td>(25, 21, slf_op_0)</td></tr>
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<tr><td>SCKOE</td><td>(0, 21, slf_op_1)</td><td>(25, 21, slf_op_1)</td></tr>
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<tr><td>SCSNI</td><td>(0, 22, lutff_2/in_1)</td><td>(25, 22, lutff_2/in_1)</td></tr>
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<tr><td>SI</td><td>(0, 22, lutff_7/in_3)</td><td>(25, 22, lutff_7/in_3)</td></tr>
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<tr><td>SO</td><td>(0, 20, slf_op_4)</td><td>(25, 20, slf_op_4)</td></tr>
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<tr><td>SOE</td><td>(0, 20, slf_op_5)</td><td>(25, 20, slf_op_5)</td></tr>
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<tr><td>SPIIRQ</td><td>(0, 20, slf_op_2)</td><td>(25, 20, slf_op_2)</td></tr>
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<tr><td>SPIWKUP</td><td>(0, 20, slf_op_3)</td><td>(25, 20, slf_op_3)</td></tr>
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</table>
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</td><td>
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<table class="cstab">
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<tr><th>Signal</th><th>LEDDA_IP<br/>(0, 31, 2)</th></tr>
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<tr><td>LEDDADDR0</td><td>(0, 28, lutff_4/in_0)</td></tr>
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<tr><td>LEDDADDR1</td><td>(0, 28, lutff_5/in_0)</td></tr>
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<tr><td>LEDDADDR2</td><td>(0, 28, lutff_6/in_0)</td></tr>
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<tr><td>LEDDADDR3</td><td>(0, 28, lutff_7/in_0)</td></tr>
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<tr><td>LEDDCLK</td><td>(0, 29, clk)</td></tr>
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<tr><td>LEDDCS</td><td>(0, 28, lutff_2/in_0)</td></tr>
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<tr><td>LEDDDAT0</td><td>(0, 28, lutff_2/in_1)</td></tr>
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<tr><td>LEDDDAT1</td><td>(0, 28, lutff_3/in_1)</td></tr>
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<tr><td>LEDDDAT2</td><td>(0, 28, lutff_4/in_1)</td></tr>
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<tr><td>LEDDDAT3</td><td>(0, 28, lutff_5/in_1)</td></tr>
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<tr><td>LEDDDAT4</td><td>(0, 28, lutff_6/in_1)</td></tr>
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<tr><td>LEDDDAT5</td><td>(0, 28, lutff_7/in_1)</td></tr>
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<tr><td>LEDDDAT6</td><td>(0, 28, lutff_0/in_0)</td></tr>
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<tr><td>LEDDDAT7</td><td>(0, 28, lutff_1/in_0)</td></tr>
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<tr><td>LEDDDEN</td><td>(0, 28, lutff_1/in_1)</td></tr>
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<tr><td>LEDDEXE</td><td>(0, 28, lutff_0/in_1)</td></tr>
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<tr><td>LEDDON</td><td>(0, 29, slf_op_0)</td></tr>
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<tr><td>PWMOUT0</td><td>(0, 28, slf_op_4)</td></tr>
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<tr><td>PWMOUT1</td><td>(0, 28, slf_op_5)</td></tr>
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<tr><td>PWMOUT2</td><td>(0, 28, slf_op_6)</td></tr>
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</table>
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</td></tr></table>
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</p>
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<p>The I<sup>2</sup>C "glitch filter" is a seperate module from the I<sup>2</sup>C interface IP and needs to be reverse engineered seperately.
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</body></html>
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@ -0,0 +1,46 @@
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#!/usr/bin/env python3
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import ast, sys
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data = ""
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with open(sys.argv[1], 'r') as f:
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data = f.read()
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ip_dat = ast.literal_eval("{\n" + data + "}")
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def is_cbit(ident):
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if "_ENABLE" in ident or "DELAYED" in ident:
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return True
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else:
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return False
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def is_bus(ident):
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return ident.startswith("SB")
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ips = sorted(ip_dat)
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print ("<table class=\"cstab\">\n<tr><th>Signal</th>", end='')
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for ip in ips:
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t, loc = ip
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x, y, z = loc
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print("<th>%s<br/>(%d, %d, %d)</th>" % (t, x, y, z), end='')
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print ("</tr>")
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# TODO: could group busses?
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for print_t in ["SB", "G", "CBIT"]:
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for n in sorted(ip_dat[ips[0]]):
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if is_bus(n) != (print_t == "SB"):
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continue
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if is_cbit(n) != (print_t == "CBIT"):
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continue
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print("<tr>", end='')
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em_o = ""
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em_c = ""
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if is_cbit(n):
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em_o = "<em>"
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em_c = "</em>"
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print("<td>%s%s%s</td>" % (em_o, n, em_c), end='')
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for ip in ips:
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entry = ip_dat[ip][n]
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x, y, name = entry
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print("<td>%s(%d, %d, %s)%s</td>" % (em_o, x, y, name, em_c), end='')
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print("</tr>")
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print ("</table>")
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