u4k: add SMCCLK cell location

icecube uses SMCCLK.CLK to "legalize" output cells.  Unclear what this
is for, but it appears in almost all outputs.

icebox/icebox.py

@@ -5770,6 +5770,9 @@ extra_cells_db = {
             "CLKLF":                        (25, 19, "glb_netwk_5"),
             "CLKLF_FABRIC":                 (25, 19, "slf_op_0")
         },
+        ("SMCCLK", (25, 3, 0)) : {
+            "CLK":                          (25, 3, "slf_op_5")
+        },
     }
 }
 

icefuzz/tmedges.txt

@@ -3235,6 +3235,7 @@ SB_MAC16_ADS_U_32P32_BYPASS.O[26] Odrv4.I
 SB_MAC16_ADS_U_32P32_BYPASS.O[27] LocalMux.I
 SB_MAC16_ADS_U_32P32_BYPASS.O[27] Odrv12.I
 SB_MAC16_ADS_U_32P32_BYPASS.O[27] Odrv4.I
+SB_MAC16_ADS_U_32P32_BYPASS.O[28] Odrv12.I
 SB_MAC16_ADS_U_32P32_BYPASS.O[28] Odrv4.I
 SB_MAC16_ADS_U_32P32_BYPASS.O[29] Odrv12.I
 SB_MAC16_ADS_U_32P32_BYPASS.O[29] Odrv4.I
@@ -3577,6 +3578,7 @@ SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[19] Odrv12.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[19] Odrv4.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[1] LocalMux.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[1] Odrv12.I
+SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[1] Odrv4.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[20] LocalMux.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[20] Odrv12.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[20] Odrv4.I
@@ -3595,6 +3597,7 @@ SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[26] Odrv4.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[27] Odrv12.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[27] Odrv4.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[28] LocalMux.I
+SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[28] Odrv12.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[28] Odrv4.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[29] LocalMux.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[29] Odrv12.I
@@ -3623,6 +3626,7 @@ SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[8] LocalMux.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[8] Odrv12.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[8] Odrv4.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[9] LocalMux.I
+SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[9] Odrv12.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.O[9] Odrv4.I
 SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.SIGNEXTOUT SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE.SIGNEXTIN
 SB_MAC16_MAC_U_16X16_CIN_ALL_PIPELINE.ACCUMCO SB_MAC16_MAC_U_16X16_CIN_ALL_PIPELINE.ACCUMCI
@@ -3748,6 +3752,7 @@ SB_MAC16_MAC_U_16X16_IM_BYPASS.O[16] LocalMux.I
 SB_MAC16_MAC_U_16X16_IM_BYPASS.O[16] Odrv12.I
 SB_MAC16_MAC_U_16X16_IM_BYPASS.O[16] Odrv4.I
 SB_MAC16_MAC_U_16X16_IM_BYPASS.O[17] Odrv4.I
+SB_MAC16_MAC_U_16X16_IM_BYPASS.O[18] LocalMux.I
 SB_MAC16_MAC_U_16X16_IM_BYPASS.O[18] Odrv12.I
 SB_MAC16_MAC_U_16X16_IM_BYPASS.O[18] Odrv4.I
 SB_MAC16_MAC_U_16X16_IM_BYPASS.O[19] LocalMux.I
@@ -5150,6 +5155,8 @@ SB_RAM40_4K.RDATA[8] Odrv4.I
 SB_RAM40_4K.RDATA[9] LocalMux.I
 SB_RAM40_4K.RDATA[9] Odrv12.I
 SB_RAM40_4K.RDATA[9] Odrv4.I
+SMCCLK.CLK Odrv12.I
+SMCCLK.CLK Odrv4.I
 SRMux.O LogicCell40.sr
 SRMux.O SB_MAC16_ACC_U_16P16_ALL_PIPELINE.IRSTBOT
 SRMux.O SB_MAC16_ACC_U_16P16_ALL_PIPELINE.IRSTTOP
@@ -5339,6 +5346,7 @@ Span12Mux_s10_v.O Span12Mux_s5_v.I
 Span12Mux_s10_v.O Span12Mux_s7_h.I
 Span12Mux_s10_v.O Span12Mux_s8_h.I
 Span12Mux_s10_v.O Span12Mux_s9_h.I
+Span12Mux_s10_v.O Span12Mux_s9_v.I
 Span12Mux_s10_v.O Span12Mux_v.I
 Span12Mux_s11_h.O LocalMux.I
 Span12Mux_s11_h.O Sp12to4.I
@@ -5484,6 +5492,7 @@ Span12Mux_s6_v.O LocalMux.I
 Span12Mux_s6_v.O Sp12to4.I
 Span12Mux_s6_v.O Span12Mux_h.I
 Span12Mux_s6_v.O Span12Mux_s10_h.I
+Span12Mux_s6_v.O Span12Mux_s11_h.I
 Span12Mux_s6_v.O Span12Mux_s1_h.I
 Span12Mux_s6_v.O Span12Mux_s5_h.I
 Span12Mux_s6_v.O Span12Mux_s6_h.I

icefuzz/tmedges.ys

@@ -28,5 +28,7 @@ hierarchy -generate INV i:I o:O
 hierarchy -generate gio2CtrlBuf i:I o:O
 hierarchy -generate CascadeBuf i:I o:O
 
+hierarchy -generate SMCCLK o:CLK
+
 hierarchy -check
 tee -o tmedges_unrenamed.tmp edgetypes