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Add DSP and IPConnect tile support to icepack and glbcheck

This commit is contained in:
David Shah 2017-10-21 14:59:13 +01:00
parent 85be8e4e3d
commit aa653a2a51
2 changed files with 19 additions and 8 deletions
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7
icefuzz/glbcheck.py
View File

@ -30,13 +30,13 @@ with open(argv[1]) as f:
with open(argv[2]) as f:
current_tile = None
for line in f:
if line.startswith(("Tile", "IO_Tile", "RAM_Tile", "LogicTile")):
f = line.replace("IO_", "").replace("RAM_", "").split("_")
if line.startswith(("Tile", "IO_Tile", "RAM_Tile", "LogicTile", "DSP_Tile", "IpCon_Tile")):
f = line.replace("IO_", "").replace("RAM_", "").replace("DSP_","").replace("IpCon_","").split("_")
assert len(f) == 3
current_tile = "%02d.%02d" % (int(f[1]), int(f[2]))
continue
if line.find("GlobalNetwork") >= 0 or line.startswith(("IpCon", "DSP")):
if line.find("GlobalNetwork") >= 0:
current_tile = None
continue
@ -65,4 +65,3 @@ for bit in sorted(only_in_glb):
print(bit)
exit(1)

20
icepack/icepack.cc
View File

@ -801,7 +801,7 @@ void FpgaConfig::write_ascii(std::ostream &ofs) const
error("cram_x %d (bit %d, %d) larger than bank size %lu\n", cram_x, bit_x, bit_y, this->cram[cram_bank].size());
}
if (cram_y > int(this->cram[cram_bank][cram_x].size())) {
error("cram_y %d larger than bank size %lu\n", cram_y, this->cram[cram_bank][cram_x].size());
error("cram_y %d (bit %d, %d) larger than bank %d size %lu\n", cram_y, bit_x, bit_y, cram_bank, this->cram[cram_bank][cram_x].size());
}
ofs << (this->cram[cram_bank][cram_x][cram_y] ? '1' : '0');
}
@ -980,8 +980,18 @@ vector<int> FpgaConfig::chip_cols() const
string FpgaConfig::tile_type(int x, int y) const
{
if ((x == 0 || x == this->chip_width()+1) && (y == 0 || y == this->chip_height()+1)) return "corner";
// The sides on the 5k devices are unsupported tile types.
if (this->device == "5k" && (x == 0 || x == this->chip_width()+1)) return "unsupported";
// The sides on the 5k devices are IPConnect or DSP tiles
if (this->device == "5k" && (x == 0 || x == this->chip_width()+1)) {
if( (y == 5) || (y == 10) || (y == 15) || (y == 23)) //check ordering here, tile 23-26 might be reversed
return "dsp0";
if( (y == 6) || (y == 11) || (y == 16) || (y == 24))
return "dsp1";
if( (y == 7) || (y == 12) || (y == 17) || (y == 25))
return "dsp2";
if( (y == 8) || (y == 13) || (y == 18) || (y == 26))
return "dsp3";
return "ipconn";
}
if ((x == 0 || x == this->chip_width()+1) || (y == 0 || y == this->chip_height()+1)) return "io";
if (this->device == "384") return "logic";
@ -1011,7 +1021,9 @@ int FpgaConfig::tile_width(const string &type) const
if (type == "ramb") return 42;
if (type == "ramt") return 42;
if (type == "io") return 18;
if (type == "unsupported") return 76;
if (type.substr(0, 3) == "dsp") return 54;
if (type == "ipconn") return 54;
panic("Unknown tile type '%s'.\n", type.c_str());
}