mirror of https://github.com/YosysHQ/icestorm.git
Seperate different DSP configs in timing data
This commit is contained in:
David Shah
parent
78e5b89e7c
commit
8a30b4bbd4
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@ -77,7 +77,7 @@ endif
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timings:
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ifeq ($(DEVICECLASS),5k)
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cp tmedges.txt tmedges.tmp
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set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; sed '/defparam/d' < $$f > $$f.fixed; yosys -q -f verilog -s tmedges.ys $$f.fixed; done
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set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; sed '/defparam/d' < $$f > $$f.fixed; yosys -q -f verilog -s tmedges.ys $$f.fixed; python3 rename_dsps.py $$f; done
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sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp
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python3 timings.py -t timings_up5k.txt work_*/*.sdf > timings_up5k.new
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mv timings_up5k.new timings_up5k.txt
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@ -19,14 +19,41 @@ def randbin(n):
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#Only certain combinations are allowed in icecube, list them here
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#This is not a complete set, but enough to cover all bits except cbit13, which
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#is not set in any allowed config (?)
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allowed_configs = ["0010000010000001001110110", "1110000010000001001110110", "0010000010000001000000000", "1110000010000001000000000",
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"0000000011000001111110110", "1100000011000001111110110", "0000000011000001110000110", "0010000101000010111111111",
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"0000001001100100111111111", "0001001001100100111111111", "0001101001100100111111111", "0001111000101100000000000"]
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allowed_configs = [("0010000010000001001110110", "SB_MAC16_MUL_U_8X8_ALL_PIPELINE"),
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("1110000010000001001110110", "SB_MAC16_MUL_S_8X8_ALL_PIPELINE"),
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("0010000010000001000000000", "SB_MAC16_MUL_U_8X8_BYPASS"),
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("1110000010000001000000000", "SB_MAC16_MUL_S_8X8_BYPASS"),
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("0000000011000001111110110", "SB_MAC16_MUL_U_16X16_ALL_PIPELINE"),
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("1100000011000001111110110", "SB_MAC16_MUL_S_16X16_ALL_PIPELINE"),
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("0000000011000001110000110", "SB_MAC16_MUL_U_16X16_IM_BYPASS"),
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("1100000011000001110000110", "SB_MAC16_MUL_S_16X16_IM_BYPASS"),
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("0000000011000001100000000", "SB_MAC16_MUL_U_16X16_BYPASS"),
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("1100000011000001100000000", "SB_MAC16_MUL_S_16X16_BYPASS"),
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("0010000101000010111111111", "SB_MAC16_MAC_U_8X8_ALL_PIPELINE"),
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("0010000101000010100001111", "SB_MAC16_MAC_U_8X8_IM_BYPASS"),
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("0010000101000010100000000", "SB_MAC16_MAC_U_8X8_BYPASS"),
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("0000001001100100111111111", "SB_MAC16_MAC_U_16X16_ALL_PIPELINE"),
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("0001001001100100111111111", "SB_MAC16_MAC_U_16X16_CASC_ALL_PIPELINE"),
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("0001101001100100111111111", "SB_MAC16_MAC_U_16X16_CIN_ALL_PIPELINE"),
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("0000001001100100110001111", "SB_MAC16_MAC_U_16X16_IM_BYPASS"),
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("0000001001100100100000000", "SB_MAC16_MAC_U_16X16_BYPASS"),
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("1100001001100100110001111", "SB_MAC16_MAC_S_16X16_IM_BYPASS"),
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("0010000001000000100001111", "SB_MAC16_ACC_U_16P16_ALL_PIPELINE"),
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("0010000001000000100000000", "SB_MAC16_ACC_U_16P16_BYPASS"),
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("0010000001100000100001111", "SB_MAC16_ACC_U_32P32_ALL_PIPELINE"),
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("0010000001100000100000000", "SB_MAC16_ACC_U_32P32_BYPASS"),
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("0010010001001000100001111", "SB_MAC16_ADS_U_16P16_ALL_PIPELINE"),
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("0010010000001000000000000", "SB_MAC16_ADS_U_16P16_BYPASS"),
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("0010010001101000100001111", "SB_MAC16_ADS_U_32P32_ALL_PIPELINE"),
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("0010010000101000000000000", "SB_MAC16_ADS_U_32P32_BYPASS"),
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("0010010101001010111111111", "SB_MAC16_MAS_U_8X8_ALL_PIPELINE")]
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coverage = set()
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for c in allowed_configs:
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cfg, name = c
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for i in range(25):
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if c[i] == "1":
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if cfg[i] == "1":
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coverage.add(i)
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assert len(coverage) >= 24
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@ -37,6 +64,13 @@ assert len(coverage) >= 24
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for idx in range(num):
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with open(working_dir + "/dsp_%02d.v" % idx, "w") as f:
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glbs = ["glb[%d]" % i for i in range(np.random.randint(8)+1)]
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config = allowed_configs[np.random.randint(len(allowed_configs))]
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params, cfgname = config
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with open(working_dir + "/dsp_%02d.dsp" % idx, "w") as dspf:
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dspf.write(cfgname + "\n")
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params = params[::-1]
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# TODO: ce should be on this list, but causes routing failures
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glbs_choice = ["clk", "a", "b", "c", "d,", "ah", "bh", "ch", "dh", "irt", "irb", "ort", "orb", "olt", "olb", "ast", "asb", "oht", "ohb", "sei"]
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print("""
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@ -118,8 +152,7 @@ for idx in range(num):
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bits_d = "{%s}" % ", ".join(bits_d)
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negclk = randbin(1)
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params = np.random.choice(allowed_configs)
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params = params[::-1]
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print("""
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wire [34:0] out_%d;
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SB_MAC16 #(
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@ -0,0 +1,19 @@
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#!/usr/bin/env python3
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import sys, os
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dsptype = None
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dsppath = sys.argv[1].replace(".vsb", ".dsp")
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if os.path.exists(dsppath):
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with open(dsppath, 'r') as f:
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dsptype = f.readline().strip()
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with open("tmedges.tmp", "a") as outfile:
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with open("tmedges_unrenamed.tmp", "r") as infile:
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for line in infile:
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if "SB_MAC16" in line:
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if dsptype is not None:
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outfile.write(line.replace("SB_MAC16", dsptype))
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else:
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outfile.write(line)
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@ -0,0 +1,768 @@
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Reading file 'sb_io_i3c.asc'..
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Fabric size (without IO tiles): 24 x 30
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.io_tile 1 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 2 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 3 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 4 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 5 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 6 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 7 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 8 0
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IOB_0 PINTYPE_0
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IoCtrl IE_1
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IoCtrl REN_1
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IoCtrl cf_bit_35
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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buffer io_0/D_IN_0 span12_vert_0
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.io_tile 9 0
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IOB_0 PINTYPE_0
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IOB_1 PINTYPE_0
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IoCtrl IE_0
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IoCtrl IE_1
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IoCtrl REN_0
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IoCtrl REN_1
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IoCtrl cf_bit_35
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IoCtrl cf_bit_39
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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buffer io_0/D_IN_0 span12_vert_8
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buffer io_1/D_IN_0 span12_vert_4
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.io_tile 10 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 11 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 12 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 13 0
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IOB_1 PINTYPE_0
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IoCtrl IE_0
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IoCtrl REN_0
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IoCtrl cf_bit_39
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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buffer io_1/D_IN_0 span12_vert_4
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.io_tile 14 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 15 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 16 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 17 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 18 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 19 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 20 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 21 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 22 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 23 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 24 0
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 1 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 2 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 3 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 4 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 5 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 6 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 7 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 8 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 9 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 10 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 11 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 12 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 13 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 14 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 15 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 16 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 17 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 18 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 19 31
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IOB_0 PINTYPE_0
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IOB_1 PINTYPE_0
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IoCtrl cf_bit_32
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IoCtrl cf_bit_36
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 20 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 21 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 22 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 23 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.io_tile 24 31
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IoCtrl padeb_test_0
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IoCtrl padeb_test_1
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.logic_tile 8 1
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routing sp12_v_b_0 sp12_v_t_23
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.logic_tile 9 3
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routing sp12_v_b_0 sp12_h_r_0
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.logic_tile 13 3
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routing sp12_v_b_0 sp12_h_r_0
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.logic_tile 21 3
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routing sp12_h_l_23 sp12_v_t_23
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.logic_tile 9 5
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routing sp12_v_b_0 sp12_h_r_0
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.logic_tile 21 5
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routing sp12_h_l_23 sp12_v_t_23
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.logic_tile 8 13
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routing sp12_v_b_0 sp12_v_t_23
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.logic_tile 21 15
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routing sp12_v_b_0 sp12_v_t_23
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.logic_tile 21 17
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routing sp12_v_b_0 sp12_v_t_23
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.logic_tile 21 22
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buffer sp12_v_b_15 sp4_v_b_19
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.logic_tile 21 23
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routing sp4_v_b_6 sp4_h_r_0
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.logic_tile 8 25
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routing sp12_v_b_0 sp12_h_r_0
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.logic_tile 18 25
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buffer sp12_h_r_20 sp4_h_r_22
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.logic_tile 21 25
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routing sp4_h_l_46 sp4_h_r_7
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.logic_tile 21 27
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routing sp12_v_b_0 sp12_h_r_0
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.dsp0_tile 25 15
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routing sp12_v_b_0 sp12_v_t_23
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.dsp0_tile 25 23
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routing sp4_h_l_37 sp4_v_t_37
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.dsp2_tile 25 25
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routing sp4_h_l_42 sp4_v_t_37
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.ipcon_tile 0 1
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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.ipcon_tile 25 1
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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.ipcon_tile 0 2
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
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LC_2 0000111100001111 0000
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LC_3 0000111100001111 0000
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LC_4 0000111100001111 0000
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LC_5 0000111100001111 0000
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LC_6 0000111100001111 0000
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LC_7 0000111100001111 0000
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.ipcon_tile 25 2
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Cascade IPCON_LC00_inmux02_5
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Cascade IPCON_LC01_inmux02_5
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Cascade IPCON_LC02_inmux02_5
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Cascade IPCON_LC03_inmux02_5
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Cascade IPCON_LC04_inmux02_5
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Cascade IPCON_LC05_inmux02_5
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Cascade IPCON_LC06_inmux02_5
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Cascade IPCON_LC07_inmux02_5
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LC_0 0000111100001111 0000
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LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 3
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 3
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
routing sp12_h_l_23 sp12_v_t_23
|
||||
|
||||
.ipcon_tile 0 4
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 4
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 9
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 9
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 14
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 19
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 19
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 20
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 20
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 21
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 21
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 22
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 22
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 27
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 27
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
buffer local_g0_0 lutff_4/in_0
|
||||
buffer local_g1_0 lutff_7/in_0
|
||||
buffer local_g2_0 lutff_6/in_0
|
||||
buffer local_g3_0 lutff_5/in_0
|
||||
buffer sp12_h_r_8 local_g0_0
|
||||
buffer sp12_v_b_0 local_g3_0
|
||||
buffer sp4_v_b_0 local_g1_0
|
||||
buffer sp4_v_b_24 local_g2_0
|
||||
|
||||
.ipcon_tile 0 28
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 28
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 29
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 29
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 0 30
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
.ipcon_tile 25 30
|
||||
Cascade IPCON_LC00_inmux02_5
|
||||
Cascade IPCON_LC01_inmux02_5
|
||||
Cascade IPCON_LC02_inmux02_5
|
||||
Cascade IPCON_LC03_inmux02_5
|
||||
Cascade IPCON_LC04_inmux02_5
|
||||
Cascade IPCON_LC05_inmux02_5
|
||||
Cascade IPCON_LC06_inmux02_5
|
||||
Cascade IPCON_LC07_inmux02_5
|
||||
LC_0 0000111100001111 0000
|
||||
LC_1 0000111100001111 0000
|
||||
LC_2 0000111100001111 0000
|
||||
LC_3 0000111100001111 0000
|
||||
LC_4 0000111100001111 0000
|
||||
LC_5 0000111100001111 0000
|
||||
LC_6 0000111100001111 0000
|
||||
LC_7 0000111100001111 0000
|
||||
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
# ******************************************************************************
|
||||
|
||||
# iCEcube Static Timer
|
||||
|
||||
# Version: 2017.08.27940
|
||||
|
||||
# Build Date: Sep 12 2017 08:03:55
|
||||
|
||||
# File Generated: Jan 13 2018 18:40:35
|
||||
|
||||
# Purpose: Timing Report with critical paths info
|
||||
|
||||
# Copyright (C) 2006-2010 by Lattice Semiconductor Corp. All rights reserved.
|
||||
|
||||
# ******************************************************************************
|
||||
|
||||
Device: iCE40UP5KUP5K
|
||||
Derating factors (Best:Typical:Worst) :- ( 1 : 1 : 1 )
|
||||
Derating factor used to generate this timing report: Worst
|
||||
Based on the following operating conditions
|
||||
Junction Temperature(degree Celsius): 0
|
||||
Core Voltage(V): -1
|
||||
Process Corner: Worst
|
||||
NOTE:
|
||||
Please check both worst-case and best-case scenarios for "Setup Times"
|
||||
and "Hold Times" checks
|
||||
Maximum Operating Frequency is: N/A
|
||||
|
||||
|
||||
#####################################################################
|
||||
3::Datasheet Report
|
||||
|
||||
All values are in Picoseconds
|
||||
=====================================================================
|
||||
|
||||
3.1::Setup Times
|
||||
----------------
|
||||
|
||||
Data Port Clock Port Setup Times Clock Reference:Phase
|
||||
--------- ---------- ----------- ---------------------
|
||||
|
||||
|
||||
3.2::Clock to Out
|
||||
-----------------
|
||||
|
||||
Data Port Clock Port Clock to Out Clock Reference:Phase
|
||||
--------- ---------- ------------ ---------------------
|
||||
|
||||
|
||||
3.3::Pad to Pad
|
||||
---------------
|
||||
|
||||
Port Name (Input) Port Name (Output) Pad to Pad
|
||||
----------------- ------------------ ----------
|
||||
|
||||
|
||||
3.4::Hold Times
|
||||
---------------
|
||||
|
||||
Data Port Clock Port Hold Times Clock Reference:Phase
|
||||
--------- ---------- ---------- ---------------------
|
||||
|
||||
|
||||
3.5::Minimum Clock to Out
|
||||
-------------------------
|
||||
|
||||
Data Port Clock Port Minimum Clock to Out Clock Reference:Phase
|
||||
--------- ---------- -------------------- ---------------------
|
||||
|
||||
|
||||
3.6::Minimum Pad To Pad
|
||||
-----------------------
|
||||
|
||||
Port Name (Input) Port Name (Output) Minimum Pad To Pad
|
||||
----------------- ------------------ ------------------
|
||||
|
||||
=====================================================================
|
||||
End of Datasheet Report
|
||||
#####################################################################
|
||||
|
||||
#####################################################################
|
||||
6::Path Details for DataSheet
|
||||
=====================================================================
|
||||
|
||||
|
||||
|
||||
=====================================================================
|
||||
End of Path Details for Datasheet
|
||||
#####################################################################
|
||||
|
||||
#####################################################################
|
||||
Detailed Setup Report for all timing paths
|
||||
=====================================================================
|
||||
=====================================================================
|
||||
End of Detailed Setup Report for all timing paths
|
||||
#####################################################################
|
||||
|
||||
#####################################################################
|
||||
Detailed Hold Report for all timing paths
|
||||
=====================================================================
|
||||
=====================================================================
|
||||
End of Detailed Hold Report for all timing paths
|
||||
#####################################################################
|
||||
|
||||
#####################################################################
|
||||
End of Timing Report
|
||||
#####################################################################
|
||||
|
||||
|
|
@ -0,0 +1,278 @@
|
|||
// Reading file 'sb_io_i3c.asc'..
|
||||
|
||||
module chip (input pin_23_puen, input pin_25_puen, input pin_23_wkpuen, input pin_25_wkpuen, input pin_23, input pin_25);
|
||||
|
||||
wire pin_23_puen;
|
||||
// (7, 1, 'neigh_op_bnr_0')
|
||||
// (7, 1, 'neigh_op_bnr_4')
|
||||
// (8, 0, 'io_0/D_IN_0')
|
||||
// (8, 0, 'io_0/PAD')
|
||||
// (8, 0, 'span12_vert_0')
|
||||
// (8, 1, 'neigh_op_bot_0')
|
||||
// (8, 1, 'neigh_op_bot_4')
|
||||
// (8, 1, 'sp12_v_b_0')
|
||||
// (8, 1, 'sp12_v_t_23')
|
||||
// (8, 2, 'sp12_v_b_23')
|
||||
// (8, 3, 'sp12_v_b_20')
|
||||
// (8, 4, 'sp12_v_b_19')
|
||||
// (8, 5, 'sp12_v_b_16')
|
||||
// (8, 6, 'sp12_v_b_15')
|
||||
// (8, 7, 'sp12_v_b_12')
|
||||
// (8, 8, 'sp12_v_b_11')
|
||||
// (8, 9, 'sp12_v_b_8')
|
||||
// (8, 10, 'sp12_v_b_7')
|
||||
// (8, 11, 'sp12_v_b_4')
|
||||
// (8, 12, 'sp12_v_b_3')
|
||||
// (8, 13, 'sp12_v_b_0')
|
||||
// (8, 13, 'sp12_v_t_23')
|
||||
// (8, 14, 'sp12_v_b_23')
|
||||
// (8, 15, 'sp12_v_b_20')
|
||||
// (8, 16, 'sp12_v_b_19')
|
||||
// (8, 17, 'sp12_v_b_16')
|
||||
// (8, 18, 'sp12_v_b_15')
|
||||
// (8, 19, 'sp12_v_b_12')
|
||||
// (8, 20, 'sp12_v_b_11')
|
||||
// (8, 21, 'sp12_v_b_8')
|
||||
// (8, 22, 'sp12_v_b_7')
|
||||
// (8, 23, 'sp12_v_b_4')
|
||||
// (8, 24, 'sp12_v_b_3')
|
||||
// (8, 25, 'sp12_h_r_0')
|
||||
// (8, 25, 'sp12_v_b_0')
|
||||
// (9, 1, 'neigh_op_bnl_0')
|
||||
// (9, 1, 'neigh_op_bnl_4')
|
||||
// (9, 25, 'sp12_h_r_3')
|
||||
// (10, 25, 'sp12_h_r_4')
|
||||
// (11, 25, 'sp12_h_r_7')
|
||||
// (12, 25, 'sp12_h_r_8')
|
||||
// (13, 25, 'sp12_h_r_11')
|
||||
// (14, 25, 'sp12_h_r_12')
|
||||
// (15, 25, 'sp12_h_r_15')
|
||||
// (16, 25, 'sp12_h_r_16')
|
||||
// (17, 25, 'sp12_h_r_19')
|
||||
// (17, 25, 'sp4_h_r_11')
|
||||
// (18, 25, 'sp12_h_r_20')
|
||||
// (18, 25, 'sp4_h_r_22')
|
||||
// (19, 25, 'sp12_h_r_23')
|
||||
// (19, 25, 'sp4_h_r_35')
|
||||
// (20, 25, 'sp12_h_l_23')
|
||||
// (20, 25, 'sp4_h_r_46')
|
||||
// (21, 25, 'sp4_h_l_46')
|
||||
// (21, 25, 'sp4_h_r_7')
|
||||
// (22, 25, 'sp4_h_r_18')
|
||||
// (23, 25, 'sp4_h_r_31')
|
||||
// (24, 25, 'sp4_h_r_42')
|
||||
// (24, 26, 'sp4_r_v_b_37')
|
||||
// (24, 27, 'sp4_r_v_b_24')
|
||||
// (24, 28, 'sp4_r_v_b_13')
|
||||
// (24, 29, 'sp4_r_v_b_0')
|
||||
// (25, 25, 'sp4_h_l_42')
|
||||
// (25, 25, 'sp4_v_t_37')
|
||||
// (25, 26, 'sp4_v_b_37')
|
||||
// (25, 27, 'local_g2_0')
|
||||
// (25, 27, 'lutff_6/in_0')
|
||||
// (25, 27, 'sp4_v_b_24')
|
||||
// (25, 28, 'sp4_v_b_13')
|
||||
// (25, 29, 'sp4_v_b_0')
|
||||
|
||||
wire pin_25_puen;
|
||||
// (8, 1, 'neigh_op_bnr_0')
|
||||
// (8, 1, 'neigh_op_bnr_4')
|
||||
// (9, 0, 'io_0/D_IN_0')
|
||||
// (9, 0, 'io_0/PAD')
|
||||
// (9, 0, 'span12_vert_8')
|
||||
// (9, 1, 'neigh_op_bot_0')
|
||||
// (9, 1, 'neigh_op_bot_4')
|
||||
// (9, 1, 'sp12_v_b_8')
|
||||
// (9, 2, 'sp12_v_b_7')
|
||||
// (9, 3, 'sp12_v_b_4')
|
||||
// (9, 4, 'sp12_v_b_3')
|
||||
// (9, 5, 'sp12_h_r_0')
|
||||
// (9, 5, 'sp12_v_b_0')
|
||||
// (10, 1, 'neigh_op_bnl_0')
|
||||
// (10, 1, 'neigh_op_bnl_4')
|
||||
// (10, 5, 'sp12_h_r_3')
|
||||
// (11, 5, 'sp12_h_r_4')
|
||||
// (12, 5, 'sp12_h_r_7')
|
||||
// (13, 5, 'sp12_h_r_8')
|
||||
// (14, 5, 'sp12_h_r_11')
|
||||
// (15, 5, 'sp12_h_r_12')
|
||||
// (16, 5, 'sp12_h_r_15')
|
||||
// (17, 5, 'sp12_h_r_16')
|
||||
// (18, 5, 'sp12_h_r_19')
|
||||
// (19, 5, 'sp12_h_r_20')
|
||||
// (20, 5, 'sp12_h_r_23')
|
||||
// (20, 20, 'sp4_r_v_b_43')
|
||||
// (20, 21, 'sp4_r_v_b_30')
|
||||
// (20, 22, 'sp4_r_v_b_19')
|
||||
// (20, 23, 'sp4_r_v_b_6')
|
||||
// (21, 5, 'sp12_h_l_23')
|
||||
// (21, 5, 'sp12_v_t_23')
|
||||
// (21, 6, 'sp12_v_b_23')
|
||||
// (21, 7, 'sp12_v_b_20')
|
||||
// (21, 8, 'sp12_v_b_19')
|
||||
// (21, 9, 'sp12_v_b_16')
|
||||
// (21, 10, 'sp12_v_b_15')
|
||||
// (21, 11, 'sp12_v_b_12')
|
||||
// (21, 12, 'sp12_v_b_11')
|
||||
// (21, 13, 'sp12_v_b_8')
|
||||
// (21, 14, 'sp12_v_b_7')
|
||||
// (21, 15, 'sp12_v_b_4')
|
||||
// (21, 16, 'sp12_v_b_3')
|
||||
// (21, 17, 'sp12_v_b_0')
|
||||
// (21, 17, 'sp12_v_t_23')
|
||||
// (21, 18, 'sp12_v_b_23')
|
||||
// (21, 19, 'sp12_v_b_20')
|
||||
// (21, 19, 'sp4_v_t_43')
|
||||
// (21, 20, 'sp12_v_b_19')
|
||||
// (21, 20, 'sp4_v_b_43')
|
||||
// (21, 21, 'sp12_v_b_16')
|
||||
// (21, 21, 'sp4_v_b_30')
|
||||
// (21, 22, 'sp12_v_b_15')
|
||||
// (21, 22, 'sp4_v_b_19')
|
||||
// (21, 23, 'sp12_v_b_12')
|
||||
// (21, 23, 'sp4_h_r_0')
|
||||
// (21, 23, 'sp4_v_b_6')
|
||||
// (21, 24, 'sp12_v_b_11')
|
||||
// (21, 25, 'sp12_v_b_8')
|
||||
// (21, 26, 'sp12_v_b_7')
|
||||
// (21, 27, 'sp12_v_b_4')
|
||||
// (21, 28, 'sp12_v_b_3')
|
||||
// (21, 29, 'sp12_v_b_0')
|
||||
// (22, 23, 'sp4_h_r_13')
|
||||
// (23, 23, 'sp4_h_r_24')
|
||||
// (24, 23, 'sp4_h_r_37')
|
||||
// (24, 24, 'sp4_r_v_b_37')
|
||||
// (24, 25, 'sp4_r_v_b_24')
|
||||
// (24, 26, 'sp4_r_v_b_13')
|
||||
// (24, 27, 'sp4_r_v_b_0')
|
||||
// (25, 23, 'sp4_h_l_37')
|
||||
// (25, 23, 'sp4_v_t_37')
|
||||
// (25, 24, 'sp4_v_b_37')
|
||||
// (25, 25, 'sp4_v_b_24')
|
||||
// (25, 26, 'sp4_v_b_13')
|
||||
// (25, 27, 'local_g1_0')
|
||||
// (25, 27, 'lutff_7/in_0')
|
||||
// (25, 27, 'sp4_v_b_0')
|
||||
|
||||
wire pin_23_wkpuen;
|
||||
// (8, 1, 'neigh_op_bnr_2')
|
||||
// (8, 1, 'neigh_op_bnr_6')
|
||||
// (9, 0, 'io_1/D_IN_0')
|
||||
// (9, 0, 'io_1/PAD')
|
||||
// (9, 0, 'span12_vert_4')
|
||||
// (9, 1, 'neigh_op_bot_2')
|
||||
// (9, 1, 'neigh_op_bot_6')
|
||||
// (9, 1, 'sp12_v_b_4')
|
||||
// (9, 2, 'sp12_v_b_3')
|
||||
// (9, 3, 'sp12_h_r_0')
|
||||
// (9, 3, 'sp12_v_b_0')
|
||||
// (10, 1, 'neigh_op_bnl_2')
|
||||
// (10, 1, 'neigh_op_bnl_6')
|
||||
// (10, 3, 'sp12_h_r_3')
|
||||
// (11, 3, 'sp12_h_r_4')
|
||||
// (12, 3, 'sp12_h_r_7')
|
||||
// (13, 3, 'sp12_h_r_8')
|
||||
// (14, 3, 'sp12_h_r_11')
|
||||
// (15, 3, 'sp12_h_r_12')
|
||||
// (16, 3, 'sp12_h_r_15')
|
||||
// (17, 3, 'sp12_h_r_16')
|
||||
// (18, 3, 'sp12_h_r_19')
|
||||
// (19, 3, 'sp12_h_r_20')
|
||||
// (20, 3, 'sp12_h_r_23')
|
||||
// (21, 3, 'sp12_h_l_23')
|
||||
// (21, 3, 'sp12_v_t_23')
|
||||
// (21, 4, 'sp12_v_b_23')
|
||||
// (21, 5, 'sp12_v_b_20')
|
||||
// (21, 6, 'sp12_v_b_19')
|
||||
// (21, 7, 'sp12_v_b_16')
|
||||
// (21, 8, 'sp12_v_b_15')
|
||||
// (21, 9, 'sp12_v_b_12')
|
||||
// (21, 10, 'sp12_v_b_11')
|
||||
// (21, 11, 'sp12_v_b_8')
|
||||
// (21, 12, 'sp12_v_b_7')
|
||||
// (21, 13, 'sp12_v_b_4')
|
||||
// (21, 14, 'sp12_v_b_3')
|
||||
// (21, 15, 'sp12_v_b_0')
|
||||
// (21, 15, 'sp12_v_t_23')
|
||||
// (21, 16, 'sp12_v_b_23')
|
||||
// (21, 17, 'sp12_v_b_20')
|
||||
// (21, 18, 'sp12_v_b_19')
|
||||
// (21, 19, 'sp12_v_b_16')
|
||||
// (21, 20, 'sp12_v_b_15')
|
||||
// (21, 21, 'sp12_v_b_12')
|
||||
// (21, 22, 'sp12_v_b_11')
|
||||
// (21, 23, 'sp12_v_b_8')
|
||||
// (21, 24, 'sp12_v_b_7')
|
||||
// (21, 25, 'sp12_v_b_4')
|
||||
// (21, 26, 'sp12_v_b_3')
|
||||
// (21, 27, 'sp12_h_r_0')
|
||||
// (21, 27, 'sp12_v_b_0')
|
||||
// (22, 27, 'sp12_h_r_3')
|
||||
// (23, 27, 'sp12_h_r_4')
|
||||
// (24, 27, 'sp12_h_r_7')
|
||||
// (25, 27, 'local_g0_0')
|
||||
// (25, 27, 'lutff_4/in_0')
|
||||
// (25, 27, 'sp12_h_r_8')
|
||||
|
||||
wire pin_25_wkpuen;
|
||||
// (12, 1, 'neigh_op_bnr_2')
|
||||
// (12, 1, 'neigh_op_bnr_6')
|
||||
// (13, 0, 'io_1/D_IN_0')
|
||||
// (13, 0, 'io_1/PAD')
|
||||
// (13, 0, 'span12_vert_4')
|
||||
// (13, 1, 'neigh_op_bot_2')
|
||||
// (13, 1, 'neigh_op_bot_6')
|
||||
// (13, 1, 'sp12_v_b_4')
|
||||
// (13, 2, 'sp12_v_b_3')
|
||||
// (13, 3, 'sp12_h_r_0')
|
||||
// (13, 3, 'sp12_v_b_0')
|
||||
// (14, 1, 'neigh_op_bnl_2')
|
||||
// (14, 1, 'neigh_op_bnl_6')
|
||||
// (14, 3, 'sp12_h_r_3')
|
||||
// (15, 3, 'sp12_h_r_4')
|
||||
// (16, 3, 'sp12_h_r_7')
|
||||
// (17, 3, 'sp12_h_r_8')
|
||||
// (18, 3, 'sp12_h_r_11')
|
||||
// (19, 3, 'sp12_h_r_12')
|
||||
// (20, 3, 'sp12_h_r_15')
|
||||
// (21, 3, 'sp12_h_r_16')
|
||||
// (22, 3, 'sp12_h_r_19')
|
||||
// (23, 3, 'sp12_h_r_20')
|
||||
// (24, 3, 'sp12_h_r_23')
|
||||
// (25, 3, 'sp12_h_l_23')
|
||||
// (25, 3, 'sp12_v_t_23')
|
||||
// (25, 4, 'sp12_v_b_23')
|
||||
// (25, 5, 'sp12_v_b_20')
|
||||
// (25, 6, 'sp12_v_b_19')
|
||||
// (25, 7, 'sp12_v_b_16')
|
||||
// (25, 8, 'sp12_v_b_15')
|
||||
// (25, 9, 'sp12_v_b_12')
|
||||
// (25, 10, 'sp12_v_b_11')
|
||||
// (25, 11, 'sp12_v_b_8')
|
||||
// (25, 12, 'sp12_v_b_7')
|
||||
// (25, 13, 'sp12_v_b_4')
|
||||
// (25, 14, 'sp12_v_b_3')
|
||||
// (25, 15, 'sp12_v_b_0')
|
||||
// (25, 15, 'sp12_v_t_23')
|
||||
// (25, 16, 'sp12_v_b_23')
|
||||
// (25, 17, 'sp12_v_b_20')
|
||||
// (25, 18, 'sp12_v_b_19')
|
||||
// (25, 19, 'sp12_v_b_16')
|
||||
// (25, 20, 'sp12_v_b_15')
|
||||
// (25, 21, 'sp12_v_b_12')
|
||||
// (25, 22, 'sp12_v_b_11')
|
||||
// (25, 23, 'sp12_v_b_8')
|
||||
// (25, 24, 'sp12_v_b_7')
|
||||
// (25, 25, 'sp12_v_b_4')
|
||||
// (25, 26, 'sp12_v_b_3')
|
||||
// (25, 27, 'local_g3_0')
|
||||
// (25, 27, 'lutff_5/in_0')
|
||||
// (25, 27, 'sp12_v_b_0')
|
||||
|
||||
// Debug Symbols
|
||||
|
||||
|
||||
// Warning: unmatched port 'pin_23'
|
||||
// Warning: unmatched port 'pin_25'
|
||||
|
||||
endmodule
|
||||
|
|
@ -227,6 +227,12 @@ for filename in sdf_inputs:
|
|||
for stmt in cell:
|
||||
if stmt[0] == "CELLTYPE":
|
||||
celltype = rewrite_celltype(stmt[1][1:-1])
|
||||
if celltype == "SB_MAC16":
|
||||
try:
|
||||
with open(filename.replace(".sdf", ".dsp"), "r") as dspf:
|
||||
celltype = dspf.readline().strip()
|
||||
except:
|
||||
break
|
||||
database.setdefault(celltype, set())
|
||||
|
||||
if stmt[0] == "DELAY":
|
||||
|
|
|
|||
11971
icefuzz/timings_up5k.txt
11971
icefuzz/timings_up5k.txt
File diff suppressed because it is too large
Load Diff
2629
icefuzz/tmedges.txt
2629
icefuzz/tmedges.txt
File diff suppressed because it is too large
Load Diff
|
|
@ -29,4 +29,4 @@ hierarchy -generate gio2CtrlBuf i:I o:O
|
|||
hierarchy -generate CascadeBuf i:I o:O
|
||||
|
||||
hierarchy -check
|
||||
tee -a tmedges.tmp edgetypes
|
||||
tee -o tmedges_unrenamed.tmp edgetypes
|
||||
|
|
|
|||
|
|
@ -0,0 +1,268 @@
|
|||
CascadeMux.O LogicCell40.in2
|
||||
ClkMux.O DummyBuf.I
|
||||
ClkMux.O SB_SPRAM256KA.CLOCK
|
||||
DummyBuf.O Odrv4.I
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDADDR0
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDADDR1
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDADDR2
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDADDR3
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDCLK
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDCS
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT0
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT1
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT2
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT3
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT4
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT5
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT6
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDAT7
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDDEN
|
||||
DummyBuf.O SB_LEDDA_IP.LEDDEXE
|
||||
GND.Y LogicCell40.carryin
|
||||
GND.Y LogicCell40.clk
|
||||
GND.Y LogicCell40.in0
|
||||
GND.Y LogicCell40.in1
|
||||
GND.Y LogicCell40.in2
|
||||
GND.Y LogicCell40.in3
|
||||
GND.Y LogicCell40.sr
|
||||
Glb2LocalMux.O LocalMux.I
|
||||
GlobalMux.O ClkMux.I
|
||||
GlobalMux.O Glb2LocalMux.I
|
||||
ICE_CARRY_IN_MUX.carryinitout InMux.I
|
||||
ICE_CARRY_IN_MUX.carryinitout LogicCell40.carryin
|
||||
ICE_GB.GLOBALBUFFEROUTPUT gio2CtrlBuf.I
|
||||
IO_PAD.DOUT PRE_IO.PADIN
|
||||
IO_PAD.PACKAGEPIN IO_PAD.PACKAGEPIN
|
||||
InMux.O CascadeMux.I
|
||||
InMux.O DummyBuf.I
|
||||
InMux.O LogicCell40.in0
|
||||
InMux.O LogicCell40.in1
|
||||
InMux.O LogicCell40.in3
|
||||
InMux.O SB_HFOSC.CLKHFEN
|
||||
InMux.O SB_HFOSC.CLKHFPU
|
||||
InMux.O SB_LFOSC.CLKLFEN
|
||||
InMux.O SB_LFOSC.CLKLFPU
|
||||
InMux.O SB_RGBA_DRV.CURREN
|
||||
InMux.O SB_RGBA_DRV.RGB0PWM
|
||||
InMux.O SB_RGBA_DRV.RGB1PWM
|
||||
InMux.O SB_RGBA_DRV.RGB2PWM
|
||||
InMux.O SB_RGBA_DRV.RGBLEDEN
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[0]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[10]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[11]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[12]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[13]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[1]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[2]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[3]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[4]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[5]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[6]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[7]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[8]
|
||||
InMux.O SB_SPRAM256KA.ADDRESS[9]
|
||||
InMux.O SB_SPRAM256KA.CHIPSELECT
|
||||
InMux.O SB_SPRAM256KA.DATAIN[0]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[10]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[11]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[12]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[13]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[14]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[15]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[1]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[2]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[3]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[4]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[5]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[6]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[7]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[8]
|
||||
InMux.O SB_SPRAM256KA.DATAIN[9]
|
||||
InMux.O SB_SPRAM256KA.MASKWREN[0]
|
||||
InMux.O SB_SPRAM256KA.MASKWREN[1]
|
||||
InMux.O SB_SPRAM256KA.MASKWREN[2]
|
||||
InMux.O SB_SPRAM256KA.MASKWREN[3]
|
||||
InMux.O SB_SPRAM256KA.POWEROFF
|
||||
InMux.O SB_SPRAM256KA.SLEEP
|
||||
InMux.O SB_SPRAM256KA.STANDBY
|
||||
InMux.O SB_SPRAM256KA.WREN
|
||||
IoInMux.O ICE_GB.USERSIGNALTOGLOBALBUFFER
|
||||
IoInMux.O PRE_IO.DOUT0
|
||||
IoSpan4Mux.O IoSpan4Mux.I
|
||||
IoSpan4Mux.O LocalMux.I
|
||||
IoSpan4Mux.O Span4Mux_h.I
|
||||
IoSpan4Mux.O Span4Mux_s3_h.I
|
||||
IoSpan4Mux.O Span4Mux_v.I
|
||||
LocalMux.O ClkMux.I
|
||||
LocalMux.O InMux.I
|
||||
LocalMux.O IoInMux.I
|
||||
LogicCell40.carryout ICE_CARRY_IN_MUX.carryinitin
|
||||
LogicCell40.carryout InMux.I
|
||||
LogicCell40.carryout LogicCell40.carryin
|
||||
LogicCell40.lcout LocalMux.I
|
||||
LogicCell40.lcout Odrv12.I
|
||||
LogicCell40.lcout Odrv4.I
|
||||
LogicCell40.ltout CascadeMux.I
|
||||
Odrv12.O LocalMux.I
|
||||
Odrv12.O Sp12to4.I
|
||||
Odrv12.O Span12Mux_h.I
|
||||
Odrv12.O Span12Mux_s0_h.I
|
||||
Odrv12.O Span12Mux_s10_h.I
|
||||
Odrv12.O Span12Mux_s10_v.I
|
||||
Odrv12.O Span12Mux_s11_h.I
|
||||
Odrv12.O Span12Mux_s11_v.I
|
||||
Odrv12.O Span12Mux_s1_v.I
|
||||
Odrv12.O Span12Mux_s2_v.I
|
||||
Odrv12.O Span12Mux_s3_h.I
|
||||
Odrv12.O Span12Mux_s3_v.I
|
||||
Odrv12.O Span12Mux_s4_h.I
|
||||
Odrv12.O Span12Mux_s4_v.I
|
||||
Odrv12.O Span12Mux_s5_v.I
|
||||
Odrv12.O Span12Mux_s6_h.I
|
||||
Odrv12.O Span12Mux_s6_v.I
|
||||
Odrv12.O Span12Mux_s7_h.I
|
||||
Odrv12.O Span12Mux_s7_v.I
|
||||
Odrv12.O Span12Mux_s8_h.I
|
||||
Odrv12.O Span12Mux_s8_v.I
|
||||
Odrv12.O Span12Mux_s9_h.I
|
||||
Odrv12.O Span12Mux_s9_v.I
|
||||
Odrv12.O Span12Mux_v.I
|
||||
Odrv4.O IoSpan4Mux.I
|
||||
Odrv4.O LocalMux.I
|
||||
Odrv4.O Span4Mux_h.I
|
||||
Odrv4.O Span4Mux_s0_v.I
|
||||
Odrv4.O Span4Mux_s1_v.I
|
||||
Odrv4.O Span4Mux_s2_h.I
|
||||
Odrv4.O Span4Mux_s2_v.I
|
||||
Odrv4.O Span4Mux_s3_h.I
|
||||
Odrv4.O Span4Mux_s3_v.I
|
||||
Odrv4.O Span4Mux_v.I
|
||||
PRE_IO.DIN0 LocalMux.I
|
||||
PRE_IO.DIN0 Odrv12.I
|
||||
PRE_IO.DIN0 Odrv4.I
|
||||
PRE_IO.PADOEN IO_PAD.OE
|
||||
PRE_IO.PADOUT IO_PAD.DIN
|
||||
SB_HFOSC.CLKHF GlobalMux.I
|
||||
SB_LEDDA_IP.PWMOUT0 DummyBuf.I
|
||||
SB_LFOSC.CLKLF GlobalMux.I
|
||||
Sp12to4.O IoSpan4Mux.I
|
||||
Sp12to4.O LocalMux.I
|
||||
Sp12to4.O Span4Mux_h.I
|
||||
Sp12to4.O Span4Mux_s0_v.I
|
||||
Sp12to4.O Span4Mux_s1_h.I
|
||||
Sp12to4.O Span4Mux_s2_h.I
|
||||
Sp12to4.O Span4Mux_s2_v.I
|
||||
Sp12to4.O Span4Mux_s3_h.I
|
||||
Sp12to4.O Span4Mux_s3_v.I
|
||||
Sp12to4.O Span4Mux_v.I
|
||||
Span12Mux_h.O LocalMux.I
|
||||
Span12Mux_h.O Sp12to4.I
|
||||
Span12Mux_h.O Span12Mux_s10_v.I
|
||||
Span12Mux_h.O Span12Mux_s11_v.I
|
||||
Span12Mux_h.O Span12Mux_s1_v.I
|
||||
Span12Mux_h.O Span12Mux_s2_h.I
|
||||
Span12Mux_h.O Span12Mux_s3_h.I
|
||||
Span12Mux_h.O Span12Mux_s3_v.I
|
||||
Span12Mux_h.O Span12Mux_s6_v.I
|
||||
Span12Mux_h.O Span12Mux_s7_h.I
|
||||
Span12Mux_h.O Span12Mux_s7_v.I
|
||||
Span12Mux_h.O Span12Mux_s8_v.I
|
||||
Span12Mux_h.O Span12Mux_s9_v.I
|
||||
Span12Mux_h.O Span12Mux_v.I
|
||||
Span12Mux_s0_h.O Sp12to4.I
|
||||
Span12Mux_s10_h.O LocalMux.I
|
||||
Span12Mux_s10_h.O Sp12to4.I
|
||||
Span12Mux_s10_v.O LocalMux.I
|
||||
Span12Mux_s10_v.O Sp12to4.I
|
||||
Span12Mux_s11_h.O LocalMux.I
|
||||
Span12Mux_s11_h.O Sp12to4.I
|
||||
Span12Mux_s11_v.O LocalMux.I
|
||||
Span12Mux_s11_v.O Sp12to4.I
|
||||
Span12Mux_s1_v.O LocalMux.I
|
||||
Span12Mux_s1_v.O Span12Mux_v.I
|
||||
Span12Mux_s2_h.O LocalMux.I
|
||||
Span12Mux_s2_h.O Sp12to4.I
|
||||
Span12Mux_s2_v.O LocalMux.I
|
||||
Span12Mux_s2_v.O Sp12to4.I
|
||||
Span12Mux_s3_h.O LocalMux.I
|
||||
Span12Mux_s3_h.O Sp12to4.I
|
||||
Span12Mux_s3_v.O LocalMux.I
|
||||
Span12Mux_s3_v.O Sp12to4.I
|
||||
Span12Mux_s4_h.O LocalMux.I
|
||||
Span12Mux_s4_h.O Sp12to4.I
|
||||
Span12Mux_s4_v.O LocalMux.I
|
||||
Span12Mux_s5_h.O Sp12to4.I
|
||||
Span12Mux_s5_v.O LocalMux.I
|
||||
Span12Mux_s6_h.O LocalMux.I
|
||||
Span12Mux_s6_h.O Sp12to4.I
|
||||
Span12Mux_s6_v.O LocalMux.I
|
||||
Span12Mux_s6_v.O Sp12to4.I
|
||||
Span12Mux_s7_h.O LocalMux.I
|
||||
Span12Mux_s7_h.O Sp12to4.I
|
||||
Span12Mux_s7_v.O LocalMux.I
|
||||
Span12Mux_s7_v.O Sp12to4.I
|
||||
Span12Mux_s8_h.O LocalMux.I
|
||||
Span12Mux_s8_h.O Sp12to4.I
|
||||
Span12Mux_s8_v.O LocalMux.I
|
||||
Span12Mux_s8_v.O Sp12to4.I
|
||||
Span12Mux_s9_h.O LocalMux.I
|
||||
Span12Mux_s9_h.O Sp12to4.I
|
||||
Span12Mux_s9_v.O LocalMux.I
|
||||
Span12Mux_s9_v.O Sp12to4.I
|
||||
Span12Mux_v.O LocalMux.I
|
||||
Span12Mux_v.O Sp12to4.I
|
||||
Span12Mux_v.O Span12Mux_h.I
|
||||
Span12Mux_v.O Span12Mux_s0_h.I
|
||||
Span12Mux_v.O Span12Mux_s10_h.I
|
||||
Span12Mux_v.O Span12Mux_s10_v.I
|
||||
Span12Mux_v.O Span12Mux_s11_h.I
|
||||
Span12Mux_v.O Span12Mux_s11_v.I
|
||||
Span12Mux_v.O Span12Mux_s2_h.I
|
||||
Span12Mux_v.O Span12Mux_s3_h.I
|
||||
Span12Mux_v.O Span12Mux_s4_h.I
|
||||
Span12Mux_v.O Span12Mux_s5_h.I
|
||||
Span12Mux_v.O Span12Mux_s6_h.I
|
||||
Span12Mux_v.O Span12Mux_s7_h.I
|
||||
Span12Mux_v.O Span12Mux_s7_v.I
|
||||
Span12Mux_v.O Span12Mux_s8_h.I
|
||||
Span12Mux_v.O Span12Mux_s9_v.I
|
||||
Span12Mux_v.O Span12Mux_v.I
|
||||
Span4Mux_h.O LocalMux.I
|
||||
Span4Mux_h.O Span4Mux_h.I
|
||||
Span4Mux_h.O Span4Mux_s0_v.I
|
||||
Span4Mux_h.O Span4Mux_s1_h.I
|
||||
Span4Mux_h.O Span4Mux_s1_v.I
|
||||
Span4Mux_h.O Span4Mux_s2_h.I
|
||||
Span4Mux_h.O Span4Mux_s2_v.I
|
||||
Span4Mux_h.O Span4Mux_s3_h.I
|
||||
Span4Mux_h.O Span4Mux_s3_v.I
|
||||
Span4Mux_h.O Span4Mux_v.I
|
||||
Span4Mux_s0_v.O IoSpan4Mux.I
|
||||
Span4Mux_s0_v.O LocalMux.I
|
||||
Span4Mux_s0_v.O Span4Mux_v.I
|
||||
Span4Mux_s1_h.O LocalMux.I
|
||||
Span4Mux_s1_v.O IoSpan4Mux.I
|
||||
Span4Mux_s1_v.O LocalMux.I
|
||||
Span4Mux_s2_h.O LocalMux.I
|
||||
Span4Mux_s2_h.O Span4Mux_v.I
|
||||
Span4Mux_s2_v.O IoSpan4Mux.I
|
||||
Span4Mux_s2_v.O LocalMux.I
|
||||
Span4Mux_s2_v.O Span4Mux_h.I
|
||||
Span4Mux_s2_v.O Span4Mux_v.I
|
||||
Span4Mux_s3_h.O LocalMux.I
|
||||
Span4Mux_s3_h.O Span4Mux_v.I
|
||||
Span4Mux_s3_v.O IoSpan4Mux.I
|
||||
Span4Mux_s3_v.O LocalMux.I
|
||||
Span4Mux_s3_v.O Span4Mux_h.I
|
||||
Span4Mux_s3_v.O Span4Mux_v.I
|
||||
Span4Mux_v.O LocalMux.I
|
||||
Span4Mux_v.O Span4Mux_h.I
|
||||
Span4Mux_v.O Span4Mux_s0_v.I
|
||||
Span4Mux_v.O Span4Mux_s1_h.I
|
||||
Span4Mux_v.O Span4Mux_s1_v.I
|
||||
Span4Mux_v.O Span4Mux_s2_h.I
|
||||
Span4Mux_v.O Span4Mux_s2_v.I
|
||||
Span4Mux_v.O Span4Mux_s3_h.I
|
||||
Span4Mux_v.O Span4Mux_s3_v.I
|
||||
Span4Mux_v.O Span4Mux_v.I
|
||||
gio2CtrlBuf.O GlobalMux.I
|
||||
Loading…
Reference in New Issue