AngeloJacobo
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e5bd0d74c3
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use SIM_MODEL directive to use models during vivado simulation
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2025-05-25 09:03:16 +08:00 |
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AngeloJacobo
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4be9a30ff8
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added files needed for icarus simulation (not yet working)
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2025-05-18 15:24:10 +08:00 |
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AngeloJacobo
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5c52351bce
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uncommented default_nettype
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2025-03-01 19:32:35 +08:00 |
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AngeloJacobo
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99eaa7d103
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added IODELAY_GROUP for ODELAY,IDELAY,and IDELAYCTRL
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2025-03-01 14:41:00 +08:00 |
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AngeloJacobo
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058da90bfc
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changed SKIP_INTERNAL_TEST to BIST_MODE (0,1, or 2)
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2025-02-09 09:45:30 +08:00 |
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AngeloJacobo
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d8cb6d16d9
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update copyright date
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2025-01-02 13:18:42 +08:00 |
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AngeloJacobo
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3b2ef2afa8
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odt[1] generated by separate oserdes to make it routable
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2024-12-21 18:24:12 +08:00 |
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AngeloJacobo
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7367182640
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dual rank enabled is now passing formal and simulation!
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2024-12-20 18:56:21 +08:00 |
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AngeloJacobo
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e89b06defd
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paremeterized IOSERDES loopback option
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2024-10-13 16:42:31 +08:00 |
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Angelo Jacobo
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95820556c2
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replace ioserdes loopback with logic
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2024-10-12 09:43:27 +08:00 |
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AngeloJacobo
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8fb24dd180
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add copyright on headers
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2024-06-09 12:01:30 +08:00 |
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AngeloJacobo
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593f56ac4a
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resolve warning in implementation: not connected to load
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2024-06-02 19:20:10 +08:00 |
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Angelo Jacobo
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d489b867d7
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fixed rtoi error in vivado
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2024-04-20 12:20:20 +08:00 |
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AngeloJacobo
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29ec2d0714
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changed to picosecond-based instead of nanoseconds
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2023-11-14 14:13:41 +08:00 |
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AngeloJacobo
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0cfd8243ab
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remove all IODELAY_GROUP lines
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2023-11-11 11:32:14 +08:00 |
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AngeloJacobo
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922d185643
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now passes internal test calibration on klusterboard
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2023-09-15 19:58:36 +08:00 |
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AngeloJacobo
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2ee7e35bc5
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add dci reset and optional DCIEN IO buffers
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2023-09-05 18:32:30 +08:00 |
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AngeloJacobo
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e2653d5793
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reset for IO is released only after IDELAYCTRL is ready, added also IODELAY_GROUP
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2023-08-20 11:09:38 +08:00 |
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AngeloJacobo
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411febc1a8
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add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY)
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2023-08-15 19:35:44 +08:00 |
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AngeloJacobo
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72dc00742b
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correct generate indexes
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2023-08-04 07:52:31 +08:00 |
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AngeloJacobo
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e38859ef78
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resolved warning from vivado on IOBDELAY
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2023-07-19 18:47:24 +08:00 |
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AngeloJacobo
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137e30ba36
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resolve vivado warnings
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2023-07-17 21:39:07 +08:00 |
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AngeloJacobo
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b80bda4a46
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resolve warning from verilator linting
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2023-07-16 08:38:20 +08:00 |
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AngeloJacobo
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3250d8d368
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write dqs toggles for half slow clk cycle at the end, needed when DQ is set to be delayed (non-zero flyby delay)
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2023-07-05 16:41:55 +08:00 |
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AngeloJacobo
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272711762e
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add phy for data mask (oserdes -> odelay -> obuf)
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2023-06-22 19:51:06 +08:00 |
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AngeloJacobo
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b9204332b1
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made delay tap loadable
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2023-06-08 13:52:04 +08:00 |
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Angelo Jacobo
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0a43b04f9e
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added phy for generating differential o_ddr3_clk
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2023-05-29 21:51:48 +08:00 |
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Angelo Jacobo
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400a277cdc
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added 52ns sync reset (IDELAYCTRL requirement)
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2023-05-29 16:19:32 +08:00 |
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Angelo Jacobo
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f648035e4e
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added phy interface (separated from controller)
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2023-05-28 16:19:47 +08:00 |