Commit Graph

349 Commits

Author SHA1 Message Date
James Cherry aca2c51e96 minor cleanup 2021-02-07 17:33:53 -07:00
James Cherry 6359bd6fc5 leaks 2021-02-07 17:22:59 +00:00
James Cherry e3d60f0b8c gcc compiler warnings 2021-02-06 22:59:57 +00:00
James Cherry 40737739a6 liberty equiv cells match pg_pins 2021-01-28 16:30:58 -07:00
James Cherry d22358fc3c LibertyCell::isBuffer prune level shifters 2021-01-22 20:40:02 -07:00
James Cherry 00bc28a1c9 Liberty is_level_shifter 2021-01-22 20:32:47 -07:00
James Cherry ed7d2dcc36 default_operating_condition allow forward ref 2021-01-19 15:40:09 -07:00
James Cherry b22a48f5e5 gcc compiler warnings 2021-01-04 18:14:04 -08:00
James Cherry af887c3112 debugPrint use __VA_ARGS__ 2021-01-01 11:46:51 -08:00
James Cherry a005ccb0e2 Report::printLine. no more \n's in print stmts 2020-12-30 19:51:50 -08:00
James Cherry 20f01e417b rm \n from print stmts 2020-12-28 09:04:57 -08:00
James Cherry 8cb6445ec0 LibertyReader::libWarn 2020-12-26 10:47:11 -08:00
James Cherry ee86a30338 error/warn 2020-12-25 14:00:11 -08:00
James Cherry 6fb6c93847 liberty warning wording 2020-12-24 15:55:51 -08:00
James Cherry 0137916b85 \n in error msgs 2020-12-24 15:55:10 -08:00
James Cherry 14bacb30cf cudd/ssta compile errors 2020-12-20 08:31:33 -07:00
James Cherry 78d29c8f90 error/warn IDs 2020-12-13 18:21:35 -07:00
James Cherry b0f0de488f TimingArc::intrinsicDelay, driveResistance 2020-11-20 09:16:14 -07:00
James Cherry 7e4e92076a power muli-corner support 2020-11-11 11:31:47 -07:00
James Cherry b4851a6c7d flex disable register decls 2020-11-11 08:32:25 -07:00
James Cherry c9296a0d1f disable flex register warnings 2020-11-09 21:11:29 -07:00
James Cherry a83e42500d pocv2 early/late error 2020-11-02 10:44:13 -08:00
James Cherry f457b75304 get_property lib_pin intrinsic_delay 2020-10-25 14:59:54 -07:00
James Cherry 2c0e653dc1 LibExprParser::copyInput warning 2020-09-25 16:09:26 -07:00
James Cherry 7d31cfac8f flex disable register declarations 2020-09-17 05:50:12 -07:00
James Cherry 2ce82bd187 include Machine.hh in headers that use __attribute__ 2020-07-18 19:54:10 -07:00
James Cherry b7a572cfe2 LibertyPort::capacitance() 2020-07-09 16:10:21 -07:00
James Cherry 46d2446f88 LibertyCell::isInverter 2020-07-09 08:42:52 -07:00
James Cherry 7f037334bf compiler warning 2020-07-06 18:35:36 -07:00
James Cherry 07e1262186 report_units 2020-06-23 17:11:48 -07:00
James Cherry 035c9c3cee liberty scale scalar values 2020-06-12 19:58:35 -07:00
James Cherry 4c0225acc3 liberty is_memory_cell 2020-06-09 20:02:59 -07:00
James Cherry 32adfad72e liberty default_fanout_load, fanout_load for report -max_fanout 2020-06-08 20:11:15 -07:00
James Cherry b49b957ad0 liberty reader func parsing issue with missing pin 2020-05-22 16:35:57 -07:00
James Cherry fdb9ad44ab liberty default_max_slew only applies to outputs 2020-05-12 17:57:04 -07:00
James Cherry d562879a27 liberty bus port slew/cap/fanout limits 2020-05-11 07:14:36 -07:00
James Cherry 1d3ae30600 LibertyCell::internalPowers(port) 2020-04-06 18:27:40 -07:00
James Cherry ee326f165c public headers in include/sta 2020-04-05 14:53:44 -07:00
James Cherry 804953e317 mv public headers to include/sta 2020-04-05 11:35:51 -07:00
James Cherry 4a017e86eb update copyright 2020-03-06 18:50:37 -08:00
James Cherry 3d6d6e9580 use #pragma once 2020-02-15 17:13:16 -07:00
James Cherry 1068813b59 UseSWIG cmake support for swig 2020-01-25 10:38:03 -07:00
James Cherry 0d01effea1 remove undefined protos 2020-01-22 20:03:39 -07:00
James Cherry d22eaea30c flush Makefile.am 2020-01-04 19:00:51 -08:00
James Cherry b18ae6f74f deprecate TimingArcSet::timingArcIterator(), Sdc::clockIterator() 2019-12-29 09:54:42 -08:00
James Cherry 3502671d17 pocv early sigma used for late 2019-12-20 17:23:48 -07:00
James Cherry cc1bd6b5ab TransRiseFall -> RiseFall 2019-11-11 15:30:19 -07:00
James Cherry bdab2acb09 use operator= instead of copy 2019-11-11 13:03:38 -07:00
James Cherry e7d8689f70 resizer support 2019-11-05 10:14:35 -07:00
James Cherry 6934b4ebcd updates for resizer 2019-11-05 07:51:54 -07:00
James Cherry 3ae920be7d write_verilog escaped bus name 2019-08-13 21:34:35 -07:00
James Cherry e16696c347 wire_load fanout_length values in quotes ucsd20190808 2019-08-08 14:12:07 -07:00
James Cherry 9d93130ff2 range iterators 2019-07-18 06:19:00 -07:00
James Cherry fa849908d7 set_cmd_units 2019-07-08 11:50:41 -07:00
James Cherry f34fc4162d base class destructors public virtual or protected non-virtual 2019-06-30 22:30:53 -07:00
James Cherry 93f5f9d664 no need for virtuals in Concrete network objects 2019-06-28 13:38:56 -07:00
James Cherry 12494398e9 set_clock_sense -> set_sense, LibertyPort::driveResistance 2019-06-23 19:52:29 -07:00
James Cherry b9a7b349eb template tcl typemap(in) seqs/sets 2019-06-22 11:17:13 -07:00
James Cherry 337fab4c44 equiv cells dont_use turd 2019-06-21 13:21:37 -07:00
James Cherry 5f23536b17 support equiv cells across libraries 2019-06-20 21:41:49 -07:00
James Cherry db2a06c430 findCmdLineFlag/Key 2019-06-17 16:42:26 -07:00
James Cherry 49b2c3cea7 rm redundant StaState args 2019-06-17 08:32:28 -07:00
James Cherry d9237aa3e5 Liberty cell drive_resistance property 2019-06-16 10:20:51 -07:00
James Cherry 96fcf1d8b2 ConcreteCell/Port pointers to corresponding liberty 2019-06-15 22:20:54 -07:00
James Cherry 61b1ac4d12 sync 2019-06-04 08:12:22 -07:00
James Cherry 736a977a6d Liberty equiv cells in LibertyCell instead of map 2019-05-28 07:45:05 -07:00
James Cherry 53df9472d7 resizer support 2019-05-27 22:46:24 -07:00
James Cherry 8242035b22 LibertyCell::isBuffer() 2019-05-25 20:02:33 -07:00
James Cherry 6a194ef6ee LibertyCell::higherDrive(), slowerDrive() 2019-05-25 17:08:53 -07:00
James Cherry a988588dac sync 2019-05-19 17:06:06 -06:00
James Cherry c6db5eb0ae power don't required related_pg_pin in internal_power 2019-05-11 07:11:27 -06:00
James Cherry d1a602cefc 2.0.15 2019-04-29 08:39:05 -07:00
James Cherry 12ca613886 2.0.14 2019-04-18 18:01:10 -07:00
James Cherry 4fc8801e76 or20190411 write_path_spice with no voltage_map, pg_pins 2019-04-13 15:01:14 -07:00
James Cherry 2d519b4740 ucsd 20190410 seg fault accessing/setting power_default_signal_toggle_rate 2019-04-10 20:36:48 -07:00
James Cherry fcfec7ae54 2.0.13 2019-04-01 09:05:07 -07:00
James Cherry ed3ad4fb30 copyright etc 2019-03-29 14:18:08 -07:00
James Cherry 75bf56b1f1 normalized_voltage template var misspelled 2019-03-27 15:01:11 -07:00
James Cherry 28799b9b09 sync 03/26/2019 2019-03-26 16:07:32 -07:00
James Cherry e2d02839a3 examples 2019-03-21 10:48:50 -07:00
James Cherry 5a5164276e read_liberty check timing arcs 2019-03-19 21:30:19 -07:00
James Cherry e5c9bc43fd 2.0.10 2019-03-12 17:25:53 -07:00
James Cherry dae85f08e0 misspelled "Deescription", gcc warnings 2019-03-03 17:50:56 -08:00
James Cherry 0f2dba7eff sync 2019-02-26 08:26:12 -08:00
James Cherry d8146af755 remove autotools/configure support 2019-02-16 12:07:59 -08:00
James Cherry 3f65204717 2.0.6 2019-01-26 23:03:01 -08:00
James Cherry f2a28bdcaf write_path_spice register path support 2019-01-22 20:41:32 -08:00
James Cherry 316742202f sync 2019-01-16 15:37:31 -08:00
James Cherry 9e5aac37f4 cmake, write_path_spice 2019-01-03 16:14:15 -08:00
James Cherry b075ccc783 update copyright 2019-01-01 12:26:11 -08:00
James Cherry 9435640d5a write_spice alpha 2019-01-01 12:25:25 -08:00
James Cherry a6e21377e6 2.0.2 2018-12-26 11:03:31 -08:00
James Cherry 4f381f6669 2018/12/24 all_fanout from input port 2018-12-24 13:07:10 -08:00
James Cherry e1059eac12 find_timing_paths 2018-12-20 22:41:54 -08:00
James Cherry f49dc75d32 sync 2018-12-05 14:18:41 -08:00
James Cherry ddf897d4e6 report_power, pocv support 2018-11-26 09:15:52 -08:00
James Cherry e9bde796ec 2018/11/08 corners > 2 causes internal error, 2018/11/09 Verilog ignore attributes (* blah *) 2018-11-09 10:04:16 -08:00
James Cherry e68203dcf4 ^/v for arc display 2018-10-02 16:20:18 -07:00
James Cherry 1154fb89fd and then there was light... 2018-09-28 08:54:21 -07:00