examples
This commit is contained in:
James Cherry
parent
5a5164276e
commit
e2d02839a3
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doc/OpenSTA.odt
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doc/OpenSTA.odt
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doc/OpenSTA.pdf
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doc/OpenSTA.pdf
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@ -0,0 +1,93 @@
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(DELAYFILE
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(SDFVERSION "OVI 2.1")
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(DESIGN "top")
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(DATE "Thu Mar 2 20:33:26 2000")
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(VENDOR "slow")
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(PROGRAM "Hand job")
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(VERSION "69")
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(DIVIDER /)
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(VOLTAGE 2.25:2.25:2.25)
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(PROCESS "1.000:1.000:1.000")
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(TEMPERATURE 125.00:125.00:125.00)
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(TIMESCALE 1ns)
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(CELL
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(CELLTYPE "top")
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(INSTANCE)
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(DELAY
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(ABSOLUTE
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// Offset in1 vs in2, rise vs fall arrivals so results are deterministic.
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(INTERCONNECT in1 r1/D (0.011:0.011:0.011) (0.01:0.01:0.01))
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(INTERCONNECT in2 r2/D (0.021:0.021:0.021) (0.02:0.02:0.02))
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(INTERCONNECT clk1 r1/CK (0.0:0.0:0.0) (0.0:0.0:0.0))
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(INTERCONNECT clk2 r2/CK (0.0:0.0:0.0) (0.0:0.0:0.0))
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(INTERCONNECT clk3 r3/CK (0.0:0.0:0.0) (0.0:0.0:0.0))
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(INTERCONNECT r1/Q u2/A1 (0.0:0.0:0.0) (0.0:0.0:0.0))
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(INTERCONNECT r2/Q u1/A (0.0:0.0:0.0) (0.0:0.0:0.0))
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(INTERCONNECT u1/Z u2/A2 (0.0:0.0:0.0) (0.0:0.0:0.0))
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(INTERCONNECT u2/ZN r3/D (0.0:0.0:0.0) (0.0:0.0:0.0))
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(INTERCONNECT r3/Q out (0.0:0.0:0.0) (0.0:0.0:0.0))
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)
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)
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)
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(CELL
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(CELLTYPE "DFF_X1")
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(INSTANCE r1)
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(DELAY
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(ABSOLUTE
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(IOPATH CK Q (1:1:1) (1.1:1.1:1.1))
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)
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)
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(TIMINGCHECK
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(SETUP D (posedge CK) (.5:.5:.5))
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(HOLD D (posedge CK) (.1:.1:.1))
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(PERIOD (posedge CK) (1.0:2.0:3.0))
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)
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)
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(CELL
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(CELLTYPE "DFF_X1")
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(INSTANCE r2)
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(DELAY
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(ABSOLUTE
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(IOPATH CK Q (1:1:1) (1.1:1.1:1.1))
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)
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)
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(TIMINGCHECK
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(SETUP D (posedge CK) (.5:.5:.5))
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(HOLD D (posedge CK) (.1:.1:.1))
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(PERIOD (posedge CK) (1.0:2.0:3.0))
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)
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)
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(CELL
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(CELLTYPE "DFF_X1")
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(INSTANCE r3)
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(DELAY
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(ABSOLUTE
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(IOPATH CK Q (1:1:1) (1.1:1.1:1.1))
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)
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)
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(TIMINGCHECK
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(SETUP D (posedge CK) (.5:.5:.5))
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(HOLD D (posedge CK) (.1:.1:.1))
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(PERIOD (posedge CK) (1.0:2.0:3.0))
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)
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)
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(CELL
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(CELLTYPE "BUF_X1")
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(INSTANCE u1)
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(DELAY
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(ABSOLUTE
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(IOPATH A Z (1:1:1) (1.1:1.1:1.1))
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)
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)
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)
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(CELL
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(CELLTYPE "AND2_X1")
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(INSTANCE u2)
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(DELAY
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(ABSOLUTE
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(IOPATH A1 ZN (1:1:1) (1.1:1.1:1.1))
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(IOPATH A2 ZN (1:1:1) (1.1:1.1:1.1))
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)
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)
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)
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)
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@ -0,0 +1,8 @@
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# sdf example
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read_liberty example1_slow.lib
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read_verilog example1.v
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link_design top
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read_sdf example1.sdf
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 {in1 in2}
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report_checks
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@ -0,0 +1,11 @@
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module top (in1, in2, clk1, clk2, clk3, out);
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input in1, in2, clk1, clk2, clk3;
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output out;
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wire r1q, r2q, u1z, u2z;
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DFF_X1 r1 (.D(in1), .CK(clk1), .Q(r1q));
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DFF_X1 r2 (.D(in2), .CK(clk2), .Q(r2q));
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BUF_X1 u1 (.A(r2q), .Z(u1z));
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AND2_X1 u2 (.A1(r1q), .A2(u1z), .ZN(u2z));
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DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out));
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endmodule // top
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@ -0,0 +1,7 @@
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# delay calc example
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read_liberty example1_slow.lib
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read_verilog example1.v
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link_design top
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 {in1 in2}
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report_checks
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@ -0,0 +1,8 @@
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# min/max delay calc example
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read_liberty -max example1_slow.lib
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read_liberty -min example1_fast.lib
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read_verilog example1.v
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link_design top
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 {in1 in2}
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report_checks -path_delay min_max
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@ -0,0 +1,8 @@
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# delay calc example with parasitics
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read_liberty example1_slow.lib
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read_verilog example1.v
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link_design top
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read_spef example1.dspef
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 {in1 in2}
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report_checks
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@ -0,0 +1,13 @@
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# 3 corner with +/- 10% derating example
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define_corners wc typ bc
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read_liberty -corner wc example1_slow.lib
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read_liberty -corner typ example1_typ.lib
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read_liberty -corner bc example1_fast.lib
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read_verilog example1.v
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link_design top
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set_timing_derate -early 0.9
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set_timing_derate -early 1.1
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 {in1 in2}
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report_checks -path_delay min_max
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report_checks -corner typ
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@ -128,11 +128,8 @@ LibertyLibrary::~LibertyLibrary()
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delete units_;
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ocv_derate_map_.deleteContents();
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SupplyVoltageMap::Iterator supply_iter(supply_voltage_map_);
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while (supply_iter.hasNext()) {
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const char *supply_name;
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float voltage;
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supply_iter.next(supply_name, voltage);
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for (auto name_volt : supply_voltage_map_) {
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const char *supply_name = name_volt.first;
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stringDelete(supply_name);
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}
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}
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@ -725,10 +722,8 @@ LibertyLibrary::makeCornerMap(LibertyCell *cell1,
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cell2->name());
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}
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LibertyCellTimingArcSetIterator set_iter1(cell1);
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while (set_iter1.hasNext()) {
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TimingArcSet *arc_set1 = set_iter1.next();
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TimingArcSet *arc_set2 = cell2->findTimingArcSet(arc_set1);
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for (auto arc_set1 : cell1->timing_arc_sets_) {
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auto arc_set2 = cell2->findTimingArcSet(arc_set1);
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if (arc_set2) {
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if (link) {
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TimingArcSetArcIterator arc_iter1(arc_set1);
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@ -847,18 +842,8 @@ LibertyCell::LibertyCell(LibertyLibrary *library,
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has_internal_ports_(false),
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interface_timing_(false),
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clock_gate_type_(ClockGateType::none),
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timing_arc_sets_(nullptr),
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port_timing_arc_set_map_(nullptr),
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timing_arc_set_from_map_(nullptr),
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timing_arc_set_to_map_(nullptr),
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has_infered_reg_timing_arcs_(false),
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internal_powers_(nullptr),
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leakage_powers_(nullptr),
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sequentials_(nullptr),
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port_to_seq_map_(nullptr),
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mode_defs_(nullptr),
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scale_factors_(nullptr),
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scaled_cells_(nullptr),
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test_cell_(nullptr),
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ocv_arc_depth_(0.0),
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ocv_derate_(nullptr),
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@ -869,59 +854,22 @@ LibertyCell::LibertyCell(LibertyLibrary *library,
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LibertyCell::~LibertyCell()
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{
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if (mode_defs_) {
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mode_defs_->deleteContents();
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delete mode_defs_;
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}
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mode_defs_.deleteContents();
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latch_d_to_q_map_.deleteContents();
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deleteTimingArcAttrs();
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if (timing_arc_sets_) {
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timing_arc_sets_->deleteContents();
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delete timing_arc_sets_;
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delete timing_arc_set_map_;
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LibertyPortPairTimingArcMap::Iterator port_map_iter(port_timing_arc_set_map_);
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while (port_map_iter.hasNext()) {
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LibertyPortPair *port_pair;
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TimingArcSetSeq *sets;
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port_map_iter.next(port_pair, sets);
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delete port_pair;
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delete sets;
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}
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delete port_timing_arc_set_map_;
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timing_arc_set_from_map_->deleteContents();
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delete timing_arc_set_from_map_;
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timing_arc_set_to_map_->deleteContents();
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delete timing_arc_set_to_map_;
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}
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timing_arc_sets_.deleteContents();
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port_timing_arc_set_map_.deleteContents();
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timing_arc_set_from_map_.deleteContents();
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timing_arc_set_to_map_.deleteContents();
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deleteInternalPowerAttrs();
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if (internal_powers_) {
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internal_powers_->deleteContents();
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delete internal_powers_;
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}
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if (leakage_powers_) {
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leakage_powers_->deleteContents();
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delete leakage_powers_;
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}
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if (sequentials_) {
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sequentials_->deleteContents();
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delete sequentials_;
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delete port_to_seq_map_;
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}
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internal_powers_.deleteContents();
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leakage_powers_.deleteContents();
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sequentials_.deleteContents();
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bus_dcls_.deleteContents();
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if (scaled_cells_) {
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scaled_cells_->deleteContents();
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delete scaled_cells_;
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}
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scaled_cells_.deleteContents();
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delete test_cell_;
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ocv_derate_map_.deleteContents();
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@ -935,9 +883,7 @@ LibertyCell::~LibertyCell()
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void
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LibertyCell::deleteTimingArcAttrs()
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{
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TimingArcAttrsSeq::Iterator attr_iter(timing_arc_attrs_);
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while (attr_iter.hasNext()) {
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TimingArcAttrs *attrs = attr_iter.next();
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for (auto attrs : timing_arc_attrs_) {
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attrs->deleteContents();
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delete attrs;
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}
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@ -992,16 +938,14 @@ ModeDef *
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LibertyCell::makeModeDef(const char *name)
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{
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ModeDef *mode = new ModeDef(name);
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if (mode_defs_ == nullptr)
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mode_defs_ = new ModeDefMap;
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(*mode_defs_)[mode->name()] = mode;
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mode_defs_[mode->name()] = mode;
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return mode;
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}
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ModeDef *
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LibertyCell::findModeDef(const char *name)
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{
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return mode_defs_->findKey(name);
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return mode_defs_.findKey(name);
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}
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void
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@ -1085,13 +1029,10 @@ LibertyCell::setClockGateType(ClockGateType type)
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unsigned
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LibertyCell::addTimingArcSet(TimingArcSet *arc_set)
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{
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if (timing_arc_sets_ == nullptr) {
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timing_arc_sets_ = new TimingArcSetSeq;
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}
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int set_index = timing_arc_sets_->size();
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int set_index = timing_arc_sets_.size();
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if (set_index > timing_arc_set_index_max)
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internalError("timing arc set max index exceeded");
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timing_arc_sets_->push_back(arc_set);
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timing_arc_sets_.push_back(arc_set);
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LibertyPort *from = arc_set->from();
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TimingRole *role = arc_set->role();
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@ -1112,9 +1053,7 @@ LibertyCell::addTimingArcAttrs(TimingArcAttrs *attrs)
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void
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LibertyCell::addInternalPower(InternalPower *power)
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{
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if (internal_powers_ == nullptr)
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internal_powers_ = new InternalPowerSeq;
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internal_powers_->push_back(power);
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internal_powers_.push_back(power);
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}
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void
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@ -1126,21 +1065,16 @@ LibertyCell::addInternalPowerAttrs(InternalPowerAttrs *attrs)
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void
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LibertyCell::deleteInternalPowerAttrs()
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{
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InternalPowerAttrsSeq::Iterator attr_iter(internal_power_attrs_);
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while (attr_iter.hasNext()) {
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InternalPowerAttrs *attrs = attr_iter.next();
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for (auto attrs : internal_power_attrs_) {
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attrs->deleteContents();
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delete attrs;
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}
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}
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void
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LibertyCell::addLeakagePower(LeakagePower *power)
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{
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if (leakage_powers_ == nullptr)
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leakage_powers_ = new LeakagePowerSeq;
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leakage_powers_->push_back(power);
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leakage_powers_.push_back(power);
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}
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void
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@ -1155,12 +1089,10 @@ LibertyCell::finish(bool infer_latches,
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Debug *debug)
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{
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translatePresetClrCheckRoles();
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if (timing_arc_sets_) {
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makeTimingArcMap(report);
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makeTimingArcPortMaps();
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findDefaultCondArcs();
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makeLatchEnables(report, debug);
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}
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makeTimingArcMap(report);
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makeTimingArcPortMaps();
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findDefaultCondArcs();
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makeLatchEnables(report, debug);
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if (infer_latches
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&& !interface_timing_)
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inferLatchRoles(debug);
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@ -1169,24 +1101,17 @@ LibertyCell::finish(bool infer_latches,
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void
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LibertyCell::findDefaultCondArcs()
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{
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LibertyPortPairTimingArcMap::Iterator set_iter1(port_timing_arc_set_map_);
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while (set_iter1.hasNext()) {
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LibertyPortPair *port_pair;
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TimingArcSetSeq *sets;
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set_iter1.next(port_pair, sets);
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for (auto port_pair_set : port_timing_arc_set_map_) {
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TimingArcSetSeq *sets = port_pair_set.second;
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bool has_cond_arcs = false;
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TimingArcSetSeq::Iterator set_iter2(sets);
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while (set_iter2.hasNext()) {
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TimingArcSet *set = set_iter2.next();
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for (auto set : *sets) {
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if (set->cond()) {
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has_cond_arcs = true;
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break;
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}
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}
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if (has_cond_arcs) {
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TimingArcSetSeq::Iterator set_iter3(sets);
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while (set_iter3.hasNext()) {
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TimingArcSet *set = set_iter3.next();
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for (auto set : *sets) {
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if (!set->cond())
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set->setIsCondDefault(true);
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}
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@ -1201,22 +1126,18 @@ void
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LibertyCell::translatePresetClrCheckRoles()
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{
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LibertyPortSet pre_clr_ports;
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LibertyCellTimingArcSetIterator set_iter(this);
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while (set_iter.hasNext()) {
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TimingArcSet *set = set_iter.next();
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if (set->role() == TimingRole::regSetClr())
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pre_clr_ports.insert(set->from());
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for (auto arc_set : timing_arc_sets_) {
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if (arc_set->role() == TimingRole::regSetClr())
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pre_clr_ports.insert(arc_set->from());
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}
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if (!pre_clr_ports.empty()) {
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LibertyCellTimingArcSetIterator set_iter(this);
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while (set_iter.hasNext()) {
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TimingArcSet *set = set_iter.next();
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if (pre_clr_ports.findKey(set->to())) {
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if (set->role() == TimingRole::setup())
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set->setRole(TimingRole::recovery());
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else if (set->role() == TimingRole::hold())
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set->setRole(TimingRole::removal());
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for (auto arc_set : timing_arc_sets_) {
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if (pre_clr_ports.findKey(arc_set->to())) {
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if (arc_set->role() == TimingRole::setup())
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arc_set->setRole(TimingRole::recovery());
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else if (arc_set->role() == TimingRole::hold())
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arc_set->setRole(TimingRole::removal());
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}
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}
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}
|
||||
|
|
@ -1225,17 +1146,16 @@ LibertyCell::translatePresetClrCheckRoles()
|
|||
void
|
||||
LibertyCell::makeTimingArcMap(Report *)
|
||||
{
|
||||
timing_arc_set_map_ = new TimingArcSetMap;
|
||||
// Filter duplicate timing arcs, keeping the later definition.
|
||||
for (auto arc_set : *timing_arc_sets_)
|
||||
for (auto arc_set : timing_arc_sets_)
|
||||
// The last definition will be left in the set.
|
||||
timing_arc_set_map_->insert(arc_set);
|
||||
timing_arc_set_map_.insert(arc_set);
|
||||
|
||||
// Prune the arc sets not in the map.
|
||||
int j = 0;
|
||||
for (int i = 0; i < timing_arc_sets_->size(); i++) {
|
||||
TimingArcSet *arc_set = (*timing_arc_sets_)[i];
|
||||
TimingArcSet *match = timing_arc_set_map_->findKey(arc_set);
|
||||
for (int i = 0; i < timing_arc_sets_.size(); i++) {
|
||||
TimingArcSet *arc_set = timing_arc_sets_[i];
|
||||
TimingArcSet *match = timing_arc_set_map_.findKey(arc_set);
|
||||
if (match != arc_set) {
|
||||
// Unfortunately these errors are common in some brain damaged
|
||||
// libraries.
|
||||
|
|
@ -1248,45 +1168,40 @@ LibertyCell::makeTimingArcMap(Report *)
|
|||
}
|
||||
else
|
||||
// Shift arc sets down to fill holes left by removed duplicates.
|
||||
(*timing_arc_sets_)[j++] = arc_set;
|
||||
timing_arc_sets_[j++] = arc_set;
|
||||
}
|
||||
timing_arc_sets_->resize(j);
|
||||
timing_arc_sets_.resize(j);
|
||||
|
||||
if (timing_arc_set_map_->size() != timing_arc_sets_->size())
|
||||
if (timing_arc_set_map_.size() != timing_arc_sets_.size())
|
||||
internalError("timing arc count mismatch\n");
|
||||
}
|
||||
|
||||
void
|
||||
LibertyCell::makeTimingArcPortMaps()
|
||||
{
|
||||
port_timing_arc_set_map_ = new LibertyPortPairTimingArcMap;
|
||||
timing_arc_set_from_map_ = new LibertyPortTimingArcMap;
|
||||
timing_arc_set_to_map_ = new LibertyPortTimingArcMap;
|
||||
|
||||
for (auto arc_set : *timing_arc_sets_) {
|
||||
for (auto arc_set : timing_arc_sets_) {
|
||||
LibertyPort *from = arc_set->from();
|
||||
LibertyPort *to = arc_set->to();
|
||||
LibertyPortPair port_pair(from, to);
|
||||
TimingArcSetSeq *sets = port_timing_arc_set_map_->findKey(&port_pair);
|
||||
TimingArcSetSeq *sets = port_timing_arc_set_map_.findKey(port_pair);
|
||||
if (sets == nullptr) {
|
||||
// First arc set for from/to ports.
|
||||
sets = new TimingArcSetSeq;
|
||||
LibertyPortPair *port_pair1 = new LibertyPortPair(from, to);
|
||||
(*port_timing_arc_set_map_)[port_pair1] = sets;
|
||||
port_timing_arc_set_map_[port_pair] = sets;
|
||||
}
|
||||
sets->push_back(arc_set);
|
||||
|
||||
sets = timing_arc_set_from_map_->findKey(from);
|
||||
sets = timing_arc_set_from_map_.findKey(from);
|
||||
if (sets == nullptr) {
|
||||
sets = new TimingArcSetSeq;
|
||||
(*timing_arc_set_from_map_)[from] = sets;
|
||||
timing_arc_set_from_map_[from] = sets;
|
||||
}
|
||||
sets->push_back(arc_set);
|
||||
|
||||
sets = timing_arc_set_to_map_->findKey(to);
|
||||
sets = timing_arc_set_to_map_.findKey(to);
|
||||
if (sets == nullptr) {
|
||||
sets = new TimingArcSetSeq;
|
||||
(*timing_arc_set_to_map_)[to] = sets;
|
||||
timing_arc_set_to_map_[to] = sets;
|
||||
}
|
||||
sets->push_back(arc_set);
|
||||
}
|
||||
|
|
@ -1296,49 +1211,41 @@ TimingArcSetSeq *
|
|||
LibertyCell::timingArcSets(const LibertyPort *from,
|
||||
const LibertyPort *to) const
|
||||
{
|
||||
if (timing_arc_sets_) {
|
||||
if (from && to) {
|
||||
LibertyPortPair port_pair(from, to);
|
||||
return port_timing_arc_set_map_->findKey(&port_pair);
|
||||
}
|
||||
else if (from)
|
||||
return timing_arc_set_from_map_->findKey(from);
|
||||
else if (to)
|
||||
return timing_arc_set_to_map_->findKey(to);
|
||||
if (from && to) {
|
||||
LibertyPortPair port_pair(from, to);
|
||||
return port_timing_arc_set_map_.findKey(port_pair);
|
||||
}
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
TimingArcSet *
|
||||
LibertyCell::findTimingArcSet(TimingArcSet *key) const
|
||||
{
|
||||
if (timing_arc_sets_)
|
||||
return timing_arc_set_map_->findKey(key);
|
||||
else if (from)
|
||||
return timing_arc_set_from_map_.findKey(from);
|
||||
else if (to)
|
||||
return timing_arc_set_to_map_.findKey(to);
|
||||
else
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
TimingArcSet *
|
||||
LibertyCell::findTimingArcSet(TimingArcSet *key) const
|
||||
{
|
||||
return timing_arc_set_map_.findKey(key);
|
||||
}
|
||||
|
||||
TimingArcSet *
|
||||
LibertyCell::findTimingArcSet(unsigned arc_set_index) const
|
||||
{
|
||||
return (*timing_arc_sets_)[arc_set_index];
|
||||
return timing_arc_sets_[arc_set_index];
|
||||
}
|
||||
|
||||
size_t
|
||||
LibertyCell::timingArcSetCount() const
|
||||
{
|
||||
if (timing_arc_sets_)
|
||||
return timing_arc_sets_->size();
|
||||
else
|
||||
return 0;
|
||||
return timing_arc_sets_.size();
|
||||
}
|
||||
|
||||
bool
|
||||
LibertyCell::hasTimingArcs(LibertyPort *port) const
|
||||
{
|
||||
return timing_arc_sets_
|
||||
&& (timing_arc_set_from_map_->findKey(port)
|
||||
|| timing_arc_set_to_map_->findKey(port));
|
||||
return timing_arc_set_from_map_.findKey(port)
|
||||
|| timing_arc_set_to_map_.findKey(port);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -1376,38 +1283,29 @@ LibertyCell::makeSequential(int size,
|
|||
clear_bit,preset_bit,
|
||||
clr_preset_out, clr_preset_out_inv,
|
||||
out_bit, out_inv_bit);
|
||||
if (sequentials_ == nullptr) {
|
||||
sequentials_ = new SequentialSeq;
|
||||
port_to_seq_map_ = new PortToSequentialMap;
|
||||
}
|
||||
sequentials_->push_back(seq);
|
||||
(*port_to_seq_map_)[seq->output()] = seq;
|
||||
(*port_to_seq_map_)[seq->outputInv()] = seq;
|
||||
sequentials_.push_back(seq);
|
||||
port_to_seq_map_[seq->output()] = seq;
|
||||
port_to_seq_map_[seq->outputInv()] = seq;
|
||||
}
|
||||
}
|
||||
|
||||
Sequential *
|
||||
LibertyCell::outputPortSequential(LibertyPort *port)
|
||||
{
|
||||
if (port_to_seq_map_)
|
||||
return port_to_seq_map_->findKey(port);
|
||||
else
|
||||
return nullptr;
|
||||
return port_to_seq_map_.findKey(port);
|
||||
}
|
||||
|
||||
bool
|
||||
LibertyCell::hasSequentials() const
|
||||
{
|
||||
return sequentials_ && !sequentials_->empty();
|
||||
return !sequentials_.empty();
|
||||
}
|
||||
|
||||
void
|
||||
LibertyCell::addScaledCell(OperatingConditions *op_cond,
|
||||
LibertyCell *scaled_cell)
|
||||
{
|
||||
if (scaled_cells_ == nullptr)
|
||||
scaled_cells_ = new ScaledCellMap;
|
||||
(*scaled_cells_)[op_cond] = scaled_cell;
|
||||
scaled_cells_[op_cond] = scaled_cell;
|
||||
|
||||
LibertyCellPortBitIterator port_iter1(this);
|
||||
LibertyCellPortBitIterator port_iter2(scaled_cell);
|
||||
|
|
@ -1523,14 +1421,14 @@ LibertyCell::addOcvDerate(OcvDerate *derate)
|
|||
////////////////////////////////////////////////////////////////
|
||||
|
||||
LibertyCellTimingArcSetIterator::LibertyCellTimingArcSetIterator(const LibertyCell *cell) :
|
||||
TimingArcSetSeq::Iterator(cell->timing_arc_sets_)
|
||||
TimingArcSetSeq::ConstIterator(&cell->timing_arc_sets_)
|
||||
{
|
||||
}
|
||||
|
||||
LibertyCellTimingArcSetIterator::LibertyCellTimingArcSetIterator(const LibertyCell *cell,
|
||||
const LibertyPort *from,
|
||||
const LibertyPort *to):
|
||||
TimingArcSetSeq::Iterator(cell->timingArcSets(from, to))
|
||||
TimingArcSetSeq::ConstIterator(cell->timingArcSets(from, to))
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -1598,9 +1496,7 @@ LibertyCell::makeLatchEnables(Report *report,
|
|||
{
|
||||
if (hasSequentials()
|
||||
|| hasInferedRegTimingArcs()) {
|
||||
LibertyCellTimingArcSetIterator set_iter(this);
|
||||
while (set_iter.hasNext()) {
|
||||
TimingArcSet *en_to_q = set_iter.next();
|
||||
for (auto en_to_q : timing_arc_sets_) {
|
||||
if (en_to_q->role() == TimingRole::latchEnToQ()) {
|
||||
LibertyPort *en = en_to_q->from();
|
||||
LibertyPort *q = en_to_q->to();
|
||||
|
|
@ -1617,7 +1513,7 @@ LibertyCell::makeLatchEnables(Report *report,
|
|||
en_to_q,
|
||||
setup_check,
|
||||
debug);
|
||||
TimingArcSetArcIterator check_arc_iter( setup_check);
|
||||
TimingArcSetArcIterator check_arc_iter(setup_check);
|
||||
if (check_arc_iter.hasNext()) {
|
||||
TimingArc *check_arc = check_arc_iter.next();
|
||||
TransRiseFall *en_tr = latch_enable->enableTransition();
|
||||
|
|
@ -1668,9 +1564,7 @@ FuncExpr *
|
|||
LibertyCell::findLatchEnableFunc(LibertyPort *data,
|
||||
LibertyPort *enable) const
|
||||
{
|
||||
LibertyCellSequentialIterator iter(this);
|
||||
while (iter.hasNext()) {
|
||||
Sequential *seq = iter.next();
|
||||
for (auto seq : sequentials_) {
|
||||
if (seq->isLatch()
|
||||
&& seq->data()
|
||||
&& seq->data()->hasPort(data)
|
||||
|
|
@ -2264,6 +2158,15 @@ LibertyPortPairLess::operator()(const LibertyPortPair *pair1,
|
|||
&& pair1->second < pair2->second);
|
||||
}
|
||||
|
||||
bool
|
||||
LibertyPortPairLess::operator()(const LibertyPortPair &pair1,
|
||||
const LibertyPortPair &pair2) const
|
||||
{
|
||||
return pair1.first < pair2.first
|
||||
|| (pair1.first == pair2.first
|
||||
&& pair1.second < pair2.second);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
LibertyPortMemberIterator::LibertyPortMemberIterator(const LibertyPort *port) :
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ typedef Map<const char*, OperatingConditions*,
|
|||
typedef Map<LibertyPort*, Sequential*> PortToSequentialMap;
|
||||
typedef Vector<TimingArcSet*> TimingArcSetSeq;
|
||||
typedef Set<TimingArcSet*, TimingArcSetLess> TimingArcSetMap;
|
||||
typedef Map<LibertyPortPair*, TimingArcSetSeq*,
|
||||
typedef Map<LibertyPortPair, TimingArcSetSeq*,
|
||||
LibertyPortPairLess> LibertyPortPairTimingArcMap;
|
||||
typedef Vector<InternalPower*> InternalPowerSeq;
|
||||
typedef Vector<LeakagePower*> LeakagePowerSeq;
|
||||
|
|
@ -427,8 +427,8 @@ public:
|
|||
TimingArcSet *findTimingArcSet(TimingArcSet *key) const;
|
||||
TimingArcSet *findTimingArcSet(unsigned arc_set_index) const;
|
||||
bool hasTimingArcs(LibertyPort *port) const;
|
||||
InternalPowerSeq *internalPowers() const { return internal_powers_; }
|
||||
LeakagePowerSeq *leakagePowers() const { return leakage_powers_; }
|
||||
InternalPowerSeq *internalPowers() { return &internal_powers_; }
|
||||
LeakagePowerSeq *leakagePowers() { return &leakage_powers_; }
|
||||
float leakagePower() const { return leakage_power_; }
|
||||
bool hasSequentials() const;
|
||||
void makeSequential(int size,
|
||||
|
|
@ -507,23 +507,23 @@ protected:
|
|||
bool has_internal_ports_;
|
||||
bool interface_timing_;
|
||||
ClockGateType clock_gate_type_;
|
||||
TimingArcSetSeq *timing_arc_sets_;
|
||||
TimingArcSetSeq timing_arc_sets_;
|
||||
// Used to find matching arc sets in equivalent cells.
|
||||
TimingArcSetMap *timing_arc_set_map_;
|
||||
LibertyPortPairTimingArcMap *port_timing_arc_set_map_;
|
||||
LibertyPortTimingArcMap *timing_arc_set_from_map_;
|
||||
LibertyPortTimingArcMap *timing_arc_set_to_map_;
|
||||
TimingArcSetMap timing_arc_set_map_;
|
||||
LibertyPortPairTimingArcMap port_timing_arc_set_map_;
|
||||
LibertyPortTimingArcMap timing_arc_set_from_map_;
|
||||
LibertyPortTimingArcMap timing_arc_set_to_map_;
|
||||
TimingArcAttrsSeq timing_arc_attrs_;
|
||||
bool has_infered_reg_timing_arcs_;
|
||||
InternalPowerSeq *internal_powers_;
|
||||
InternalPowerSeq internal_powers_;
|
||||
InternalPowerAttrsSeq internal_power_attrs_;
|
||||
LeakagePowerSeq *leakage_powers_;
|
||||
SequentialSeq *sequentials_;
|
||||
PortToSequentialMap *port_to_seq_map_;
|
||||
LeakagePowerSeq leakage_powers_;
|
||||
SequentialSeq sequentials_;
|
||||
PortToSequentialMap port_to_seq_map_;
|
||||
BusDclMap bus_dcls_;
|
||||
ModeDefMap *mode_defs_;
|
||||
ModeDefMap mode_defs_;
|
||||
ScaleFactors *scale_factors_;
|
||||
ScaledCellMap *scaled_cells_;
|
||||
ScaledCellMap scaled_cells_;
|
||||
TestCell *test_cell_;
|
||||
// Latch D->Q to LatchEnable.
|
||||
LatchEnableMap latch_d_to_q_map_;
|
||||
|
|
@ -577,7 +577,7 @@ private:
|
|||
ConcreteCellPortBitIterator *iter_;
|
||||
};
|
||||
|
||||
class LibertyCellTimingArcSetIterator : public TimingArcSetSeq::Iterator
|
||||
class LibertyCellTimingArcSetIterator : public TimingArcSetSeq::ConstIterator
|
||||
{
|
||||
public:
|
||||
LibertyCellTimingArcSetIterator(const LibertyCell *cell);
|
||||
|
|
@ -596,14 +596,14 @@ public:
|
|||
class LibertyCellLeakagePowerIterator : public LeakagePowerSeq::Iterator
|
||||
{
|
||||
public:
|
||||
LibertyCellLeakagePowerIterator(const LibertyCell *cell) :
|
||||
LibertyCellLeakagePowerIterator(LibertyCell *cell) :
|
||||
LeakagePowerSeq::Iterator(cell->leakagePowers()) {}
|
||||
};
|
||||
|
||||
class LibertyCellInternalPowerIterator : public InternalPowerSeq::Iterator
|
||||
{
|
||||
public:
|
||||
LibertyCellInternalPowerIterator(const LibertyCell *cell) :
|
||||
LibertyCellInternalPowerIterator(LibertyCell *cell) :
|
||||
InternalPowerSeq::Iterator(cell->internalPowers()) {}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -148,6 +148,8 @@ class LibertyPortPairLess
|
|||
public:
|
||||
bool operator()(const LibertyPortPair *pair1,
|
||||
const LibertyPortPair *pair2) const;
|
||||
bool operator()(const LibertyPortPair &pair1,
|
||||
const LibertyPortPair &pair2) const;
|
||||
};
|
||||
|
||||
bool
|
||||
|
|
|
|||
|
|
@ -4345,6 +4345,8 @@ LibertyReader::getAttrEarlyLate(LibertyAttr *attr)
|
|||
return EarlyLateAll::min();
|
||||
else if (stringEq(value, "late"))
|
||||
return EarlyLateAll::max();
|
||||
else if (stringEq(value, "early_and_late"))
|
||||
return EarlyLateAll::all();
|
||||
else {
|
||||
libWarn(attr, "unknown early/late value.\n");
|
||||
return EarlyLateAll::all();
|
||||
|
|
|
|||
Loading…
Reference in New Issue