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debugPrint use __VA_ARGS__

This commit is contained in:
James Cherry 2021-01-01 11:46:51 -08:00
parent e03bfaa73a
commit af887c3112
33 changed files with 639 additions and 679 deletions
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4
CMakeLists.txt
View File

@ -455,8 +455,8 @@ target_include_directories(OpenSTA
target_compile_options(OpenSTA
PRIVATE
$<$<CXX_COMPILER_ID:GNU>:-Wall -Wextra -pedantic -Wcast-qual -Wredundant-decls -Wformat-security>
$<$<CXX_COMPILER_ID:AppleClang>:-Wall -Wextra -pedantic -Wcast-qual -Wredundant-decls -Wformat-security>
$<$<CXX_COMPILER_ID:Clang>:-Wall -Wextra -pedantic -Wcast-qual -Wredundant-decls -Wformat-security>
$<$<CXX_COMPILER_ID:AppleClang>:-Wall -Wextra -pedantic -Wcast-qual -Wredundant-decls -Wformat-security -Wno-gnu-zero-variadic-macro-arguments>
$<$<CXX_COMPILER_ID:Clang>:-Wall -Wextra -pedantic -Wcast-qual -Wredundant-decls -Wformat-security -Wno-gnu-zero-variadic-macro-arguments>
)
# Disable compiler specific extensions like gnu++11.

58
dcalc/ArnoldiDelayCalc.cc
View File

@ -880,7 +880,7 @@ ArnoldiDelayCalc::pr_solve1(double s,
// ignoring a typical error at drive node, that comes
// from slight inaccuracies in rr
if (!(rr[order-1]>1.0 && p[order-1]>500.0 && va>v1-0.002))
debugPrint0(debug_, "arnoldi", 1, "err, pr_solve1, va<v1");
debugPrint(debug_, "arnoldi", 1, "err, pr_solve1, va<v1");
}
tmin = ta; vmin = va;
} else {
@ -893,7 +893,7 @@ ArnoldiDelayCalc::pr_solve1(double s,
pr_get_v(ta,s,order,p,rr,&va);
}
if (va>v1)
debugPrint0(debug_, "arnoldi", 1, "err, pr_solve1, va>v1");
debugPrint(debug_, "arnoldi", 1, "err, pr_solve1, va>v1");
tmax = ta; vmax = va;
}
} else {
@ -1141,7 +1141,7 @@ ra_hinv(double y,
ex = exp(-x);
f = x+ex-1.0-y;
if (f<-1e-8 || f>1e-8)
debugPrint2(debug, "arnoldi", 1, "y f %g %g" ,y, f);
debugPrint(debug, "arnoldi", 1, "y f %g %g", y, f);
return x;
}
@ -1275,11 +1275,10 @@ ArnoldiDelayCalc::ra_solve_for_s(delay_work *D,
s = s - f/df;
if (abs(f)>.5e-12) // .5ps
debugPrint3(debug_, "arnoldi", 1,
"ra_solve_for_s p %g tlohi %s err %s",
p,
units_->timeUnit()->asString(tlohi),
units_->timeUnit()->asString(f));
debugPrint(debug_, "arnoldi", 1, "ra_solve_for_s p %g tlohi %s err %s",
p,
units_->timeUnit()->asString(tlohi),
units_->timeUnit()->asString(f));
}
/////////////////////////////////////////////////////////////////////
@ -1396,8 +1395,8 @@ ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D,
ArcDelay df;
Slew sf;
debugPrint1(debug_, "arnoldi", 1, "\nctot=%s",
units_->capacitanceUnit()->asString(ctot));
debugPrint(debug_, "arnoldi", 1, "ctot=%s",
units_->capacitanceUnit()->asString(ctot));
rdelay = ra_rdelay_1(tab,ctot);
if (rdelay == 0.0) {
@ -1419,22 +1418,21 @@ ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D,
double p = 1.0/(r*ctot);
double thix,tlox;
if (bad) printf("bad\n");
debugPrint2(debug_, "arnoldi", 1, "at r=%s s=%s",
units_->resistanceUnit()->asString(r),
units_->timeUnit()->asString(s));
debugPrint(debug_, "arnoldi", 1, "at r=%s s=%s",
units_->resistanceUnit()->asString(r),
units_->timeUnit()->asString(s));
thix = ra_solve_for_t(p,s,vhi);
tlox = ra_solve_for_t(p,s,vlo);
tab->table->gateDelay(tab->cell, tab->pvt,tab->in_slew,
ctot, tab->relcap, pocv_enabled_, df, sf);
debugPrint3(debug_, "arnoldi", 1,
"table slew (in_slew %s ctot %s) = %s",
units_->timeUnit()->asString(tab->in_slew),
units_->capacitanceUnit()->asString(ctot),
delayAsString(sf, this));
debugPrint(debug_, "arnoldi", 1, "table slew (in_slew %s ctot %s) = %s",
units_->timeUnit()->asString(tab->in_slew),
units_->capacitanceUnit()->asString(ctot),
delayAsString(sf, this));
tlohi = slew_derate*delayAsFloat(sf);
debugPrint2(debug_, "arnoldi", 1, "tlohi %s %s",
units_->timeUnit()->asString(tlohi),
units_->timeUnit()->asString(tlox-thix));
debugPrint(debug_, "arnoldi", 1, "tlohi %s %s",
units_->timeUnit()->asString(tlohi),
units_->timeUnit()->asString(tlox-thix));
}
ceff = ctot;
tab->table->gateDelay(tab->cell, tab->pvt, tab->in_slew,
@ -1462,22 +1460,22 @@ ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D,
ceff = pr_ceff(s,r,mod->order,p,rr,ceff_time);
if((ceff-1e-20) < 0.0) { // 1e-8pf
debugPrint0(debug_, "arnoldi", 1,
"Invalid effective capacitance, using total capacitance");
debugPrint(debug_, "arnoldi", 1,
"Invalid effective capacitance, using total capacitance");
ceff = ctot;
}
// new mvs at ceff
s = ra_get_s(D,tab,r,ceff);
debugPrint1(debug_, "arnoldi", 1, "new mvs s = %s",
units_->timeUnit()->asString(s));
debugPrint(debug_, "arnoldi", 1, "new mvs s = %s",
units_->timeUnit()->asString(s));
}
}
debugPrint4(debug_, "arnoldi", 1, "r %s s %s ceff_time %s ceff %s",
units_->resistanceUnit()->asString(r),
units_->timeUnit()->asString(s),
units_->timeUnit()->asString(ceff_time),
units_->capacitanceUnit()->asString(ceff));
debugPrint(debug_, "arnoldi", 1, "r %s s %s ceff_time %s ceff %s",
units_->resistanceUnit()->asString(r),
units_->timeUnit()->asString(s),
units_->timeUnit()->asString(ceff_time),
units_->capacitanceUnit()->asString(ceff));
tab->table->gateDelay(tab->cell, tab->pvt, tab->in_slew, ceff,
tab->relcap, pocv_enabled_, df, sf);

36
dcalc/ArnoldiReduce.cc
View File

@ -404,8 +404,8 @@ ArnoldiReduce::makeRcmodelDfs(ts_point *pdrv)
} // while (stackN)
if (loop)
debugPrint1(debug_, "arnoldi", 1, "net %s loop",
network_->pathName(drvr_pin_));
debugPrint(debug_, "arnoldi", 1, "net %s loop",
network_->pathName(drvr_pin_));
}
// makeRcmodelGetRC
@ -431,10 +431,10 @@ ArnoldiReduce::getRC()
if (p->in_edge && p->in_edge->resistor_)
p->r = parasitics_->value(p->in_edge->resistor_, ap_);
if (!(p->r>=0.0 && p->r<100e+3)) { // 0 < r < 100kohm
debugPrint2(debug_, "arnoldi", 1,
"R value %g out of range, drvr pin %s",
p->r,
network_->pathName(drvr_pin_));
debugPrint(debug_, "arnoldi", 1,
"R value %g out of range, drvr pin %s",
p->r,
network_->pathName(drvr_pin_));
}
}
}
@ -485,20 +485,20 @@ ArnoldiReduce::makeRcmodelFromTs()
if (debug_->check("arnoldi", 1)) {
for (k=0;k<ts_ordN;k++) {
p = ts_pordV[k];
debugPrint3(debug_, "arnoldi", 1, "T%d,P%ld c=%s",
p->ts,
p-p0,
units_->capacitanceUnit()->asString(p->c));
debugPrint(debug_, "arnoldi", 1, "T%d,P%ld c=%s",
p->ts,
p-p0,
units_->capacitanceUnit()->asString(p->c));
if (p->is_term)
debugPrint1(debug_, "arnoldi", 1, " term %d", p->tindex);
debugPrint(debug_, "arnoldi", 1, " term %d", p->tindex);
if (p->in_edge)
debugPrint3(debug_, "arnoldi", 1, " from T%d,P%ld r=%s",
p->in_edge->from->ts,
p->in_edge->from-p0,
units_->resistanceUnit()->asString(p->r));
debugPrint(debug_, "arnoldi", 1, " from T%d,P%ld r=%s",
p->in_edge->from->ts,
p->in_edge->from-p0,
units_->resistanceUnit()->asString(p->r));
}
for (i=0;i<nterms;i++)
debugPrint2(debug_, "arnoldi", 1, "outV[%d] = T%d", i, outV[i]);
debugPrint(debug_, "arnoldi", 1, "outV[%d] = T%d", i, outV[i]);
}
int max_order = 5;
@ -521,8 +521,8 @@ ArnoldiReduce::makeRcmodelFromTs()
sum = 0.0;
for (j=0;j<n;j++) sum += c[j];
debugPrint1(debug_, "arnoldi", 1, "ctot = %s",
units_->capacitanceUnit()->asString(sum));
debugPrint(debug_, "arnoldi", 1, "ctot = %s",
units_->capacitanceUnit()->asString(sum));
ctot_ = sum;
sqc_ = sqrt(sum);
double sqrt_ctot_inv = 1.0/sqc_;

34
dcalc/DmpCeff.cc
View File

@ -355,10 +355,10 @@ DmpAlg::findDriverParams(double ceff)
this, fvec_, fjac_, index_, p_, scale_);
t0_ = x_[DmpParam::t0];
dt_ = x_[DmpParam::dt];
debugPrint3(debug_, "dmp_ceff", 3, " t0 = %s dt = %s ceff = %s",
units_->timeUnit()->asString(t0_),
units_->timeUnit()->asString(dt_),
units_->capacitanceUnit()->asString(x_[DmpParam::ceff]));
debugPrint(debug_, "dmp_ceff", 3, " t0 = %s dt = %s ceff = %s",
units_->timeUnit()->asString(t0_),
units_->timeUnit()->asString(dt_),
units_->capacitanceUnit()->asString(x_[DmpParam::ceff]));
if (debug_->check("dmp_ceff", 4))
showVo();
}
@ -729,7 +729,7 @@ DmpCap::init(const LibertyLibrary *drvr_library,
double rpi,
double c1)
{
debugPrint0(debug_, "dmp_ceff", 3, "Using DMP cap");
debugPrint(debug_, "dmp_ceff", 3, "Using DMP cap");
DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, rf,
rd, in_slew, related_out_cap, c2, rpi, c1);
ceff_ = c1 + c2;
@ -739,8 +739,8 @@ void
DmpCap::gateDelaySlew(double &delay,
double &slew)
{
debugPrint1(debug_, "dmp_ceff", 3, " ceff = %s",
units_->capacitanceUnit()->asString(ceff_));
debugPrint(debug_, "dmp_ceff", 3, " ceff = %s",
units_->capacitanceUnit()->asString(ceff_));
gateCapDelaySlew(ceff_, delay, slew);
gate_slew_ = slew;
}
@ -870,7 +870,7 @@ DmpPi::init(const LibertyLibrary *drvr_library,
double rpi,
double c1)
{
debugPrint0(debug_, "dmp_ceff", 3, "Using DMP Pi");
debugPrint(debug_, "dmp_ceff", 3, "Using DMP Pi");
DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, rf, rd,
in_slew, related_out_cap, c2, rpi, c1);
@ -1184,7 +1184,7 @@ DmpZeroC2::init(const LibertyLibrary *drvr_library,
double rpi,
double c1)
{
debugPrint0(debug_, "dmp_ceff", 3, "Using DMP C2=0");
debugPrint(debug_, "dmp_ceff", 3, "Using DMP C2=0");
DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, rf, rd,
in_slew, related_out_cap, c2, rpi, c1);
ceff_ = c1;
@ -1626,14 +1626,14 @@ DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library,
dmp_alg_ = dmp_cap_;
dmp_alg_->init(drvr_library, drvr_cell, pvt, gate_model,
drvr_rf_, rd, in_slew, related_out_cap, c2, rpi, c1);
debugPrint6(debug_, "dmp_ceff", 3,
" DMP in_slew = %s c2 = %s rpi = %s c1 = %s Rd = %s (%s alg)",
units_->timeUnit()->asString(in_slew),
units_->capacitanceUnit()->asString(c2),
units_->resistanceUnit()->asString(rpi),
units_->capacitanceUnit()->asString(c1),
units_->resistanceUnit()->asString(rd),
dmp_alg_->name());
debugPrint(debug_, "dmp_ceff", 3,
" DMP in_slew = %s c2 = %s rpi = %s c1 = %s Rd = %s (%s alg)",
units_->timeUnit()->asString(in_slew),
units_->capacitanceUnit()->asString(c2),
units_->resistanceUnit()->asString(rpi),
units_->capacitanceUnit()->asString(c1),
units_->resistanceUnit()->asString(rd),
dmp_alg_->name());
}
float

128
dcalc/GraphDelayCalc1.cc
View File

@ -287,7 +287,7 @@ GraphDelayCalc1::setObserver(DelayCalcObserver *observer)
void
GraphDelayCalc1::delaysInvalid()
{
debugPrint0(debug_, "delay_calc", 1, "delays invalid");
debugPrint(debug_, "delay_calc", 1, "delays invalid");
delays_exist_ = false;
delays_seeded_ = false;
incremental_ = false;
@ -323,8 +323,8 @@ GraphDelayCalc1::delayInvalid(const Pin *pin)
void
GraphDelayCalc1::delayInvalid(Vertex *vertex)
{
debugPrint1(debug_, "delay_calc", 2, "delays invalid %s",
vertex->name(sdc_network_));
debugPrint(debug_, "delay_calc", 2, "delays invalid %s",
vertex->name(sdc_network_));
if (graph_ && incremental_) {
invalid_delays_.insert(vertex);
// Invalidate driver that triggers dcalc for multi-driver nets.
@ -404,7 +404,7 @@ GraphDelayCalc1::findDelays(Level level)
if (arc_delay_calc_) {
Stats stats(debug_, report_);
int dcalc_count = 0;
debugPrint1(debug_, "delay_calc", 1, "find delays to level %d", level);
debugPrint(debug_, "delay_calc", 1, "find delays to level %d", level);
if (!delays_seeded_) {
iter_->clear();
ensureMultiDrvrNetsFound();
@ -427,7 +427,7 @@ GraphDelayCalc1::findDelays(Level level)
delays_exist_ = true;
incremental_ = true;
debugPrint1(debug_, "delay_calc", 1, "found %d delays", dcalc_count);
debugPrint(debug_, "delay_calc", 1, "found %d delays", dcalc_count);
stats.report("Delay calc");
}
}
@ -510,7 +510,7 @@ GraphDelayCalc1::ensureMultiDrvrNetsFound()
void
GraphDelayCalc1::makeMultiDrvrNet(PinSet &drvr_pins)
{
debugPrint0(debug_, "delay_calc", 3, "multi-driver net");
debugPrint(debug_, "delay_calc", 3, "multi-driver net");
VertexSet *drvr_vertices = new VertexSet;
MultiDrvrNet *multi_drvr = new MultiDrvrNet(drvr_vertices);
Level max_drvr_level = 0;
@ -519,8 +519,8 @@ GraphDelayCalc1::makeMultiDrvrNet(PinSet &drvr_pins)
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
Vertex *drvr_vertex = graph_->pinDrvrVertex(pin);
debugPrint1(debug_, "delay_calc", 3, " %s",
network_->pathName(pin));
debugPrint(debug_, "delay_calc", 3, " %s",
network_->pathName(pin));
multi_drvr_net_map_[drvr_vertex] = multi_drvr;
drvr_vertices->insert(drvr_vertex);
Level drvr_level = drvr_vertex->level();
@ -575,8 +575,8 @@ GraphDelayCalc1::seedDrvrSlew(Vertex *drvr_vertex,
ArcDelayCalc *arc_delay_calc)
{
const Pin *drvr_pin = drvr_vertex->pin();
debugPrint1(debug_, "delay_calc", 2, "seed driver slew %s",
drvr_vertex->name(sdc_network_));
debugPrint(debug_, "delay_calc", 2, "seed driver slew %s",
drvr_vertex->name(sdc_network_));
InputDrive *drive = 0;
if (network_->isTopLevelPort(drvr_pin)) {
Port *port = network_->port(drvr_pin);
@ -679,8 +679,8 @@ void
GraphDelayCalc1::seedLoadSlew(Vertex *vertex)
{
const Pin *pin = vertex->pin();
debugPrint1(debug_, "delay_calc", 2, "seed load slew %s",
vertex->name(sdc_network_));
debugPrint(debug_, "delay_calc", 2, "seed load slew %s",
vertex->name(sdc_network_));
ClockSet *clks = sdc_->findLeafPinClocks(pin);
initSlew(vertex);
for (auto tr : RiseFall::range()) {
@ -757,9 +757,9 @@ GraphDelayCalc1::findInputDriverDelay(LibertyCell *drvr_cell,
LibertyPort *to_port,
DcalcAnalysisPt *dcalc_ap)
{
debugPrint2(debug_, "delay_calc", 2, " driver cell %s %s",
drvr_cell->name(),
rf->asString());
debugPrint(debug_, "delay_calc", 2, " driver cell %s %s",
drvr_cell->name(),
rf->asString());
LibertyCellTimingArcSetIterator set_iter(drvr_cell);
while (set_iter.hasNext()) {
TimingArcSet *arc_set = set_iter.next();
@ -789,12 +789,12 @@ GraphDelayCalc1::findInputArcDelay(LibertyCell *drvr_cell,
float from_slew,
DcalcAnalysisPt *dcalc_ap)
{
debugPrint5(debug_, "delay_calc", 3, " %s %s -> %s %s (%s)",
arc->from()->name(),
arc->fromTrans()->asString(),
arc->to()->name(),
arc->toTrans()->asString(),
arc->role()->asString());
debugPrint(debug_, "delay_calc", 3, " %s %s -> %s %s (%s)",
arc->from()->name(),
arc->fromTrans()->asString(),
arc->to()->name(),
arc->toTrans()->asString(),
arc->role()->asString());
RiseFall *drvr_rf = arc->toTrans()->asRiseFall();
if (drvr_rf) {
DcalcAPIndex ap_index = dcalc_ap->index();
@ -817,11 +817,11 @@ GraphDelayCalc1::findInputArcDelay(LibertyCell *drvr_cell,
drvr_parasitic, 0.0, pvt, dcalc_ap,
gate_delay, gate_slew);
ArcDelay load_delay = gate_delay - intrinsic_delay;
debugPrint3(debug_, "delay_calc", 3,
" gate delay = %s intrinsic = %s slew = %s",
delayAsString(gate_delay, this),
delayAsString(intrinsic_delay, this),
delayAsString(gate_slew, this));
debugPrint(debug_, "delay_calc", 3,
" gate delay = %s intrinsic = %s slew = %s",
delayAsString(gate_delay, this),
delayAsString(intrinsic_delay, this),
delayAsString(gate_slew, this));
graph_->setSlew(drvr_vertex, drvr_rf, ap_index, gate_slew);
annotateLoadDelays(drvr_vertex, drvr_rf, load_delay, false, dcalc_ap,
arc_delay_calc_);
@ -842,9 +842,9 @@ GraphDelayCalc1::findVertexDelay(Vertex *vertex,
const Pin *pin = vertex->pin();
// Don't clobber root slews.
if (!vertex->isRoot()) {
debugPrint2(debug_, "delay_calc", 2, "find delays %s (%s)",
vertex->name(sdc_network_),
network_->cellName(network_->instance(pin)));
debugPrint(debug_, "delay_calc", 2, "find delays %s (%s)",
vertex->name(sdc_network_),
network_->cellName(network_->instance(pin)));
if (network_->isLeaf(pin)) {
if (vertex->isDriver(network_)) {
bool delay_changed = findDriverDelays(vertex, arc_delay_calc);
@ -1194,15 +1194,15 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell,
RiseFall *drvr_rf = arc->toTrans()->asRiseFall();
if (from_rf && drvr_rf) {
DcalcAPIndex ap_index = dcalc_ap->index();
debugPrint7(debug_, "delay_calc", 3,
" %s %s -> %s %s (%s) corner:%s/%s",
arc->from()->name(),
arc->fromTrans()->asString(),
arc->to()->name(),
arc->toTrans()->asString(),
arc->role()->asString(),
dcalc_ap->corner()->name(),
dcalc_ap->delayMinMax()->asString());
debugPrint(debug_, "delay_calc", 3,
" %s %s -> %s %s (%s) corner:%s/%s",
arc->from()->name(),
arc->fromTrans()->asString(),
arc->to()->name(),
arc->toTrans()->asString(),
arc->role()->asString(),
dcalc_ap->corner()->name(),
dcalc_ap->delayMinMax()->asString());
// Delay calculation is done even when the gate delays/slews are
// annotated because the wire delays may not be annotated.
const Slew from_slew = edgeFromSlew(from_vertex, from_rf, edge, dcalc_ap);
@ -1223,10 +1223,10 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell,
related_out_cap, pvt, dcalc_ap,
gate_delay, gate_slew);
}
debugPrint2(debug_, "delay_calc", 3,
" gate delay = %s slew = %s",
delayAsString(gate_delay, this),
delayAsString(gate_slew, this));
debugPrint(debug_, "delay_calc", 3,
" gate delay = %s slew = %s",
delayAsString(gate_delay, this),
delayAsString(gate_slew, this));
// Merge slews.
const Slew &drvr_slew = graph_->slew(drvr_vertex, drvr_rf, ap_index);
const MinMax *slew_min_max = dcalc_ap->slewMinMax();
@ -1416,11 +1416,11 @@ GraphDelayCalc1::annotateLoadDelays(Vertex *drvr_vertex,
ArcDelay wire_delay;
Slew load_slew;
arc_delay_calc->loadDelay(load_pin, wire_delay, load_slew);
debugPrint3(debug_, "delay_calc", 3,
" %s load delay = %s slew = %s",
load_vertex->name(sdc_network_),
delayAsString(wire_delay, this),
delayAsString(load_slew, this));
debugPrint(debug_, "delay_calc", 3,
" %s load delay = %s slew = %s",
load_vertex->name(sdc_network_),
delayAsString(wire_delay, this),
delayAsString(load_slew, this));
if (!load_vertex->slewAnnotated(drvr_rf, slew_min_max)) {
if (drvr_vertex->slewAnnotated(drvr_rf, slew_min_max)) {
// Copy the driver slew to the load if it is annotated.
@ -1461,9 +1461,9 @@ void
GraphDelayCalc1::findCheckDelays(Vertex *vertex,
ArcDelayCalc *arc_delay_calc)
{
debugPrint2(debug_, "delay_calc", 2, "find checks %s (%s)",
vertex->name(sdc_network_),
network_->cellName(network_->instance(vertex->pin())));
debugPrint(debug_, "delay_calc", 2, "find checks %s (%s)",
vertex->name(sdc_network_),
network_->cellName(network_->instance(vertex->pin())));
if (vertex->hasChecks()) {
VertexInEdgeIterator edge_iter(vertex, graph_);
while (edge_iter.hasNext()) {
@ -1524,17 +1524,17 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge,
dcalc_ap);
int slew_index = dcalc_ap->checkDataSlewIndex();
const Slew &to_slew = graph_->slew(to_vertex, to_rf, slew_index);
debugPrint5(debug_, "delay_calc", 3,
" %s %s -> %s %s (%s)",
arc_set->from()->name(),
arc->fromTrans()->asString(),
arc_set->to()->name(),
arc->toTrans()->asString(),
arc_set->role()->asString());
debugPrint2(debug_, "delay_calc", 3,
" from_slew = %s to_slew = %s",
delayAsString(from_slew, this),
delayAsString(to_slew, this));
debugPrint(debug_, "delay_calc", 3,
" %s %s -> %s %s (%s)",
arc_set->from()->name(),
arc->fromTrans()->asString(),
arc_set->to()->name(),
arc->toTrans()->asString(),
arc_set->role()->asString());
debugPrint(debug_, "delay_calc", 3,
" from_slew = %s to_slew = %s",
delayAsString(from_slew, this),
delayAsString(to_slew, this));
float related_out_cap = 0.0;
if (related_out_pin) {
Parasitic *related_out_parasitic =
@ -1549,9 +1549,9 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge,
related_out_cap,
pvt, dcalc_ap,
check_delay);
debugPrint1(debug_, "delay_calc", 3,
" check_delay = %s",
delayAsString(check_delay, this));
debugPrint(debug_, "delay_calc", 3,
" check_delay = %s",
delayAsString(check_delay, this));
graph_->setArcDelay(edge, arc, ap_index, check_delay);
delay_changed = true;
}

10
dcalc/LumpedCapDelayCalc.cc
View File

@ -154,11 +154,11 @@ LumpedCapDelayCalc::gateDelay(const LibertyCell *drvr_cell,
Slew &drvr_slew)
{
GateTimingModel *model = gateModel(arc, dcalc_ap);
debugPrint3(debug_, "delay_calc", 3,
" in_slew = %s load_cap = %s related_load_cap = %s lumped",
delayAsString(in_slew, this),
units()->capacitanceUnit()->asString(load_cap),
units()->capacitanceUnit()->asString(related_out_cap));
debugPrint(debug_, "delay_calc", 3,
" in_slew = %s load_cap = %s related_load_cap = %s lumped",
delayAsString(in_slew, this),
units()->capacitanceUnit()->asString(load_cap),
units()->capacitanceUnit()->asString(related_out_cap));
if (model) {
ArcDelay gate_delay1;
Slew drvr_slew1;

57
include/sta/Debug.hh
View File

@ -69,56 +69,13 @@ debugCheck(const Debug *debug,
}
// Inlining a varargs function would eval the args, which can
// be expensive, so use macros.
#define debugPrint0(debug, what, level, msg) \
if (sta::debug_on && debug->check(what, level)) { \
debug->reportLine(what, "%s", msg); \
}
#define debugPrint1(debug, what, level, fmt, arg1) \
if (sta::debug_on && debug->check(what, level)) { \
debug->reportLine(what, fmt, arg1); \
}
#define debugPrint2(debug, what, level, fmt, arg1, arg2) \
if (sta::debug_on && debug->check(what, level)) { \
debug->reportLine(what, fmt, arg1, arg2); \
}
#define debugPrint3(debug, what, level, fmt, arg1, arg2, arg3) \
if (sta::debug_on && debug->check(what, level)) { \
debug->reportLine(what, fmt, arg1, arg2, arg3); \
}
#define debugPrint4(debug, what, level, fmt, arg1, arg2, arg3, arg4) \
if (sta::debug_on && debug->check(what, level)) { \
debug->reportLine(what, fmt, arg1, arg2, arg3, arg4); \
}
#define debugPrint5(debug, what, level, fmt, arg1, arg2, arg3, arg4, arg5) \
if (sta::debug_on && debug->check(what, level)) { \
debug->reportLine(what, fmt, arg1, arg2, arg3, arg4, arg5); \
}
#define debugPrint6(debug,what,level,fmt,arg1,arg2,arg3,arg4,arg5,arg6) \
if (sta::debug_on && debug->check(what, level)) { \
debug->reportLine(what, fmt, arg1, arg2, arg3, arg4, arg5, arg6); \
}
#define debugPrint7(debug,what,level,fmt,arg1,arg2,arg3,arg4,arg5,arg6,arg7) \
if (sta::debug_on && debug->check(what, level)) { \
debug->reportLine(what, fmt, arg1, arg2, arg3, arg4, arg5, arg6, arg7); \
}
#define debugPrint8(debug,what,level,fmt,arg1,arg2,arg3,arg4,arg5,arg6,arg7,arg8) \
if (sta::debug_on && debug->check(what, level)) { \
debug->reportLine(what, fmt, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8); \
}
#define debugPrint9(debug,what,level,fmt,arg1,arg2,arg3,arg4,arg5,arg6,arg7,arg8,arg9) \
if (sta::debug_on && debug->check(what, level)) { \
debug->reportLine(what, fmt, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9); \
// be expensive, so use a macro.
// Note that "##__VA_ARGS__" is a gcc extension to support zero arguments (no comma).
// clang -Wno-gnu-zero-variadic-macro-arguments suppresses the warning.
// c++20 has "__VA_OPT__" to deal with the zero arg case so this is temporary.
#define debugPrint(debug, what, level, msg, ...) \
if (sta::debug_on && debug->check(what, level)) { \
debug->reportLine(what, msg, ##__VA_ARGS__); \
}
} // namespace

5
include/sta/Report.hh
View File

@ -119,6 +119,7 @@ public:
static Report *defaultReport() { return default_; }
protected:
// All sta print functions have an implicit return printed by this function.
virtual void printLine(const char *line,
size_t length);
// Primitive to print output on the console.
@ -126,7 +127,9 @@ protected:
virtual size_t printConsole(const char *buffer,
size_t length) = 0;
void printToBuffer(const char *fmt,
...);
...)
__attribute__((format (printf, 2, 3)));
void printToBuffer(const char *fmt,
va_list args);
void printToBufferAppend(const char *fmt,

4
liberty/Liberty.cc
View File

@ -1713,8 +1713,8 @@ LibertyCell::makeLatchEnable(LibertyPort *d,
latch_d_to_q_map_[d_to_q] = latch_enable;
latch_check_map_[setup_check] = latch_enable;
latch_data_ports_.insert(d);
debugPrint3(debug, "liberty", 2, "latch d=%s en=%s q=%s",
d->name(), en->name(), q->name());
debugPrint(debug, "liberty", 2, "latch d=%s en=%s q=%s",
d->name(), en->name(), q->name());
return latch_enable;
}

24
liberty/LibertyReader.cc
View File

@ -1782,7 +1782,7 @@ LibertyReader::beginCell(LibertyGroup *group)
{
const char *name = group->firstName();
if (name) {
debugPrint1(debug_, "liberty", 1, "cell %s", name);
debugPrint(debug_, "liberty", 1, "cell %s", name);
cell_ = builder_->makeCell(library_, name, filename_);
in_bus_ = false;
in_bundle_ = false;
@ -2059,8 +2059,8 @@ LibertyReader::beginScaledCell(LibertyGroup *group)
if (op_cond_name) {
op_cond_ = library_->findOperatingConditions(op_cond_name);
if (op_cond_) {
debugPrint2(debug_, "liberty", 1, "scaled cell %s %s",
name, op_cond_name);
debugPrint(debug_, "liberty", 1, "scaled cell %s %s",
name, op_cond_name);
cell_ = library_->makeScaledCell(name, filename_);
}
else
@ -2131,8 +2131,8 @@ LibertyReader::makeTimingArcs(LibertyPort *to_port,
const char *from_port_name = related_port_iter.next();
PortNameBitIterator from_port_iter(cell_, from_port_name, this, line);
if (from_port_iter.hasNext()) {
debugPrint2(debug_, "liberty", 2, " timing %s -> %s",
from_port_name, to_port->name());
debugPrint(debug_, "liberty", 2, " timing %s -> %s",
from_port_name, to_port->name());
makeTimingArcs(from_port_name, from_port_iter, to_port,
related_out_port, timing);
}
@ -2304,8 +2304,8 @@ LibertyReader::makeInternalPowers(LibertyPort *port,
const char *related_port_name = related_port_iter.next();
PortNameBitIterator related_port_iter(cell_, related_port_name, this, line);
if (related_port_iter.hasNext()) {
debugPrint2(debug_, "liberty", 2, " power %s -> %s",
related_port_name, port->name());
debugPrint(debug_, "liberty", 2, " power %s -> %s",
related_port_name, port->name());
makeInternalPowers(port, related_port_name, related_port_iter, power_group);
}
}
@ -2504,7 +2504,7 @@ LibertyReader::beginPin(LibertyGroup *group)
LibertyAttrValue *param = param_iter.next();
if (param->isString()) {
const char *name = param->stringValue();
debugPrint1(debug_, "liberty", 1, " port %s", name);
debugPrint(debug_, "liberty", 1, " port %s", name);
PortNameBitIterator port_iter(cell_, name, this, group->line());
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
@ -2524,7 +2524,7 @@ LibertyReader::beginPin(LibertyGroup *group)
LibertyAttrValue *param = param_iter.next();
if (param->isString()) {
const char *name = param->stringValue();
debugPrint1(debug_, "liberty", 1, " port %s", name);
debugPrint(debug_, "liberty", 1, " port %s", name);
LibertyPort *port = findPort(name);
if (port == nullptr)
port = builder_->makePort(cell_, name);
@ -2544,7 +2544,7 @@ LibertyReader::beginPin(LibertyGroup *group)
LibertyAttrValue *param = param_iter.next();
if (param->isString()) {
const char *name = param->stringValue();
debugPrint1(debug_, "liberty", 1, " port %s", name);
debugPrint(debug_, "liberty", 1, " port %s", name);
if (isBusName(name, brkt_left, brkt_right, escape_))
// Pins not inside a bus group with bus names are not really
// busses, so escape the brackets.
@ -2680,7 +2680,7 @@ LibertyReader::visitBusType(LibertyAttr *attr)
StringSeq::Iterator name_iter(bus_names_);
while (name_iter.hasNext()) {
const char *name = name_iter.next();
debugPrint1(debug_, "liberty", 1, " bus %s", name);
debugPrint(debug_, "liberty", 1, " bus %s", name);
LibertyPort *port = builder_->makeBusPort(cell_, name,
bus_dcl->from(),
bus_dcl->to());
@ -2723,7 +2723,7 @@ LibertyReader::visitMembers(LibertyAttr *attr)
StringSeq::Iterator name_iter(bus_names_);
while (name_iter.hasNext()) {
const char *name = name_iter.next();
debugPrint1(debug_, "liberty", 1, " bundle %s", name);
debugPrint(debug_, "liberty", 1, " bundle %s", name);
ConcretePortSeq *members = new ConcretePortSeq;
LibertyAttrValueIterator value_iter(attr->values());
while (value_iter.hasNext()) {

8
parasitics/ConcreteParasitics.cc
View File

@ -1592,8 +1592,8 @@ ConcreteParasitics::reduceToPiElmore(Parasitic *parasitic,
const MinMax *cnst_min_max,
const ParasiticAnalysisPt *ap)
{
debugPrint1(debug_, "parasitic_reduce", 1, "Reduce net %s",
network_->pathName(net));
debugPrint(debug_, "parasitic_reduce", 1, "Reduce net %s",
network_->pathName(net));
NetConnectedPinIterator *pin_iter = network_->connectedPinIterator(net);
while (pin_iter->hasNext()) {
const Pin *pin = pin_iter->next();
@ -1625,8 +1625,8 @@ ConcreteParasitics::reduceToPiPoleResidue2(Parasitic *parasitic,
const MinMax *cnst_min_max,
const ParasiticAnalysisPt *ap)
{
debugPrint1(debug_, "parasitic_reduce", 1, "Reduce net %s",
network_->pathName(net));
debugPrint(debug_, "parasitic_reduce", 1, "Reduce net %s",
network_->pathName(net));
NetConnectedPinIterator *pin_iter = network_->connectedPinIterator(net);
while (pin_iter->hasNext()) {
const Pin *pin = pin_iter->next();

50
parasitics/ReduceParasitics.cc
View File

@ -131,9 +131,9 @@ ReduceToPi::reduceToPi(const Pin *drvr_pin,
c2 = y1 - y2 * y2 / y3;
rpi = -y3 * y3 / (y2 * y2 * y2);
}
debugPrint3(debug_, "parasitic_reduce", 2,
" Pi model c2=%.3g rpi=%.3g c1=%.3g",
c2, rpi, c1);
debugPrint(debug_, "parasitic_reduce", 2,
" Pi model c2=%.3g rpi=%.3g c1=%.3g",
c2, rpi, c1);
}
// Find admittance moments.
@ -173,8 +173,8 @@ ReduceToPi::reducePiDfs(const Pin *drvr_pin,
&& device != from_res) {
if (isVisited(onode)) {
// Resistor loop.
debugPrint1(debug_, "parasitic_reduce", 2, " loop detected thru resistor %s",
parasitics_->name(device));
debugPrint(debug_, "parasitic_reduce", 2, " loop detected thru resistor %s",
parasitics_->name(device));
markLoopResistor(device);
}
else {
@ -195,9 +195,9 @@ ReduceToPi::reducePiDfs(const Pin *drvr_pin,
setDownstreamCap(node, dwn_cap);
leave(node);
debugPrint5(debug_, "parasitic_reduce", 3,
" node %s y1=%.3g y2=%.3g y3=%.3g cap=%.3g",
parasitics_->name(node), y1, y2, y3, dwn_cap);
debugPrint(debug_, "parasitic_reduce", 3,
" node %s y1=%.3g y2=%.3g y3=%.3g cap=%.3g",
parasitics_->name(node), y1, y2, y3, dwn_cap);
}
float
@ -301,8 +301,8 @@ reduceToPiElmore(Parasitic *parasitic_network,
ParasiticNode *drvr_node = parasitics->findNode(parasitic_network,
drvr_pin);
if (drvr_node) {
debugPrint1(sta->debug(), "parasitic_reduce", 1, "Reduce driver %s",
sta->network()->pathName(drvr_pin));
debugPrint(sta->debug(), "parasitic_reduce", 1, "Reduce driver %s",
sta->network()->pathName(drvr_pin));
ReduceToPiElmore reducer(sta);
reducer.makePiElmore(parasitic_network, drvr_pin, drvr_node,
coupling_cap_factor, RiseFall::rise(),
@ -355,9 +355,9 @@ ReduceToPiElmore::reduceElmoreDfs(const Pin *drvr_pin,
const Pin *pin = parasitics_->connectionPin(node);
if (from_res && pin) {
if (network_->isLoad(pin)) {
debugPrint2(debug_, "parasitic_reduce", 2, " Load %s elmore=%.3g",
network_->pathName(pin),
elmore);
debugPrint(debug_, "parasitic_reduce", 2, " Load %s elmore=%.3g",
network_->pathName(pin),
elmore);
parasitics_->setElmore(pi_elmore, pin, elmore);
}
}
@ -466,8 +466,8 @@ reduceToPiPoleResidue2(Parasitic *parasitic_network,
Parasitics *parasitics = sta->parasitics();
ParasiticNode *drvr_node = parasitics->findNode(parasitic_network, drvr_pin);
if (drvr_node) {
debugPrint1(sta->debug(), "parasitic_reduce", 1, "Reduce driver %s",
sta->network()->pathName(drvr_pin));
debugPrint(sta->debug(), "parasitic_reduce", 1, "Reduce driver %s",
sta->network()->pathName(drvr_pin));
ReduceToPiPoleResidue2 reducer(sta);
reducer.makePiPoleResidue2(parasitic_network, drvr_pin, drvr_node,
coupling_cap_factor, RiseFall::rise(),
@ -587,7 +587,7 @@ ReduceToPiPoleResidue2::findBranchCurrents(const Pin *drvr_pin,
leave(node);
if (from_res) {
setCurrent(from_res, branch_i);
debugPrint1(debug_, "parasitic_reduce", 3, " res i=%.3g", branch_i);
debugPrint(debug_, "parasitic_reduce", 3, " res i=%.3g", branch_i);
}
return branch_i;
}
@ -615,10 +615,10 @@ ReduceToPiPoleResidue2::findMoments(const Pin *drvr_pin,
double r_volt = r * current(device);
double onode_volt = from_volt - r_volt;
setMoment(onode, onode_volt, moment_index);
debugPrint3(debug_, "parasitic_reduce", 3, " moment %s %d %.3g",
parasitics_->name(onode),
moment_index,
onode_volt);
debugPrint(debug_, "parasitic_reduce", 3, " moment %s %d %.3g",
parasitics_->name(onode),
moment_index,
onode_volt);
findMoments(drvr_pin, onode, onode_volt, device, moment_index, ap);
}
}
@ -683,8 +683,8 @@ ReduceToPiPoleResidue2::findPolesResidues(Parasitic *pi_pole_residue,
|| m1 / m2 == m2 / m3) {
double p1 = -1.0 / m1;
double k1 = 1.0;
debugPrint3(debug_, "parasitic_reduce", 3, " load %s p1=%.3g k1=%.3g",
network_->pathName(load_pin), p1, k1);
debugPrint(debug_, "parasitic_reduce", 3, " load %s p1=%.3g k1=%.3g",
network_->pathName(load_pin), p1, k1);
ComplexFloatSeq *poles = new ComplexFloatSeq(1);
ComplexFloatSeq *residues = new ComplexFloatSeq(1);
(*poles)[0] = ComplexFloat(p1, 0.0);
@ -702,9 +702,9 @@ ReduceToPiPoleResidue2::findPolesResidues(Parasitic *pi_pole_residue,
p1 = p;
k1 = k;
}
debugPrint5(debug_, "parasitic_reduce", 3,
" load %s p1=%.3g p2=%.3g k1=%.3g k2=%.3g",
network_->pathName(load_pin), p1, p2, k1, k2);
debugPrint(debug_, "parasitic_reduce", 3,
" load %s p1=%.3g p2=%.3g k1=%.3g k2=%.3g",
network_->pathName(load_pin), p1, p2, k1, k2);
ComplexFloatSeq *poles = new ComplexFloatSeq(2);
ComplexFloatSeq *residues = new ComplexFloatSeq(2);

86
sdc/CycleAccting.cc
View File

@ -46,9 +46,9 @@ CycleAccting::findDelays(StaState *sta)
{
Debug *debug = sta->debug();
const Unit *time_unit = sta->units()->timeUnit();
debugPrint2(debug, "cycle_acct", 1, "%s -> %s",
src_->name(),
tgt_->name());
debugPrint(debug, "cycle_acct", 1, "%s -> %s",
src_->name(),
tgt_->name());
const int setup_index = TimingRole::setup()->index();
const int latch_setup_index = TimingRole::latchSetup()->index();
const int data_check_setup_index = TimingRole::dataCheckSetup()->index();
@ -88,33 +88,33 @@ CycleAccting::findDelays(StaState *sta)
if (tgt_past_src && src_past_tgt
// Synchronicity achieved.
&& fuzzyEqual(src_cycle_start, tgt_cycle_start)) {
debugPrint2(debug, "cycle_acct", 1, " setup = %s, required = %s",
time_unit->asString(delay_[setup_index]),
time_unit->asString(required_[setup_index]));
debugPrint2(debug, "cycle_acct", 1, " hold = %s, required = %s",
time_unit->asString(delay_[hold_index]),
time_unit->asString(required_[hold_index]));
debugPrint2(debug, "cycle_acct", 1,
" converged at src cycles = %d tgt cycles = %d",
src_cycle, tgt_cycle);
debugPrint(debug, "cycle_acct", 1, " setup = %s, required = %s",
time_unit->asString(delay_[setup_index]),
time_unit->asString(required_[setup_index]));
debugPrint(debug, "cycle_acct", 1, " hold = %s, required = %s",
time_unit->asString(delay_[hold_index]),
time_unit->asString(required_[hold_index]));
debugPrint(debug, "cycle_acct", 1,
" converged at src cycles = %d tgt cycles = %d",
src_cycle, tgt_cycle);
return;
}
if (fuzzyGreater(src_cycle_start, tgt_cycle_start + tgt_period)
&& src_past_tgt)
break;
debugPrint5(debug, "cycle_acct", 2, " %s src cycle %d %s + %s = %s",
src_->name(),
src_cycle,
time_unit->asString(src_cycle_start),
time_unit->asString(src_->time()),
time_unit->asString(src_time));
debugPrint5(debug, "cycle_acct", 2, " %s tgt cycle %d %s + %s = %s",
tgt_->name(),
tgt_cycle,
time_unit->asString(tgt_cycle_start),
time_unit->asString(tgt_->time()),
time_unit->asString(tgt_time));
debugPrint(debug, "cycle_acct", 2, " %s src cycle %d %s + %s = %s",
src_->name(),
src_cycle,
time_unit->asString(src_cycle_start),
time_unit->asString(src_->time()),
time_unit->asString(src_time));
debugPrint(debug, "cycle_acct", 2, " %s tgt cycle %d %s + %s = %s",
tgt_->name(),
tgt_cycle,
time_unit->asString(tgt_cycle_start),
time_unit->asString(tgt_->time()),
time_unit->asString(tgt_time));
// For setup checks, target has to be AFTER source.
if (fuzzyGreater(tgt_time, src_time)) {
@ -123,10 +123,10 @@ CycleAccting::findDelays(StaState *sta)
if (fuzzyLess(delay, delay_[setup_index])) {
double required = tgt_time - src_cycle_start;
setSetupAccting(src_cycle, tgt_cycle, delay, required);
debugPrint2(debug, "cycle_acct", 2,
" setup min delay = %s, required = %s",
time_unit->asString(delay_[setup_index]),
time_unit->asString(required_[setup_index]));
debugPrint(debug, "cycle_acct", 2,
" setup min delay = %s, required = %s",
time_unit->asString(delay_[setup_index]),
time_unit->asString(required_[setup_index]));
}
}
@ -159,10 +159,10 @@ CycleAccting::findDelays(StaState *sta)
double required = latch_tgt_time - src_cycle_start;
setAccting(TimingRole::latchSetup(),
src_cycle, latch_tgt_cycle, delay, required);
debugPrint2(debug, "cycle_acct", 2,
" latch setup min delay = %s, required = %s",
time_unit->asString(delay_[latch_setup_index]),
time_unit->asString(required_[latch_setup_index]));
debugPrint(debug, "cycle_acct", 2,
" latch setup min delay = %s, required = %s",
time_unit->asString(delay_[latch_setup_index]),
time_unit->asString(required_[latch_setup_index]));
}
}
@ -173,10 +173,10 @@ CycleAccting::findDelays(StaState *sta)
if (fuzzyLess(delay, delay_[hold_index])) {
double required = tgt_time - src_cycle_start;
setHoldAccting(src_cycle, tgt_cycle, delay, required);
debugPrint2(debug, "cycle_acct", 2,
" hold min delay = %s, required = %s",
time_unit->asString(delay_[hold_index]),
time_unit->asString(required_[hold_index]));
debugPrint(debug, "cycle_acct", 2,
" hold min delay = %s, required = %s",
time_unit->asString(delay_[hold_index]),
time_unit->asString(required_[hold_index]));
}
}
@ -188,18 +188,18 @@ CycleAccting::findDelays(StaState *sta)
double required = tgt_time - src_cycle_start;
setAccting(TimingRole::gatedClockHold(),
src_cycle, tgt_cycle, delay, required);
debugPrint2(debug, "cycle_acct", 2,
" gated clk hold min delay = %s, required = %s",
time_unit->asString(delay_[gclk_hold_index]),
time_unit->asString(required_[gclk_hold_index]));
debugPrint(debug, "cycle_acct", 2,
" gated clk hold min delay = %s, required = %s",
time_unit->asString(delay_[gclk_hold_index]),
time_unit->asString(required_[gclk_hold_index]));
}
}
}
}
max_cycles_exceeded_ = true;
debugPrint2(debug, "cycle_acct", 1,
" max cycles exceeded after %d src cycles, %d tgt_cycles",
src_cycle, tgt_cycle);
debugPrint(debug, "cycle_acct", 1,
" max cycles exceeded after %d src cycles, %d tgt_cycles",
src_cycle, tgt_cycle);
}
else if (tgt_period > 0.0)
findDefaultArrivalSrcDelays();

64
sdc/Sdc.cc
View File

@ -4243,7 +4243,7 @@ Sdc::makeLoopExceptions()
void
Sdc::makeLoopExceptions(GraphLoop *loop)
{
debugPrint0(debug_, "loop", 2, "Loop false path");
debugPrint(debug_, "loop", 2, "Loop false path");
EdgeSeq::Iterator loop_edge_iter(loop->edges());
while (loop_edge_iter.hasNext()) {
Edge *edge = loop_edge_iter.next();
@ -4289,7 +4289,7 @@ void
Sdc::makeLoopExceptionThru(Pin *pin,
ExceptionThruSeq *thrus)
{
debugPrint1(debug_, "levelize", 2, " %s", network_->pathName(pin));
debugPrint(debug_, "levelize", 2, " %s", network_->pathName(pin));
PinSet *pins = new PinSet;
pins->insert(pin);
ExceptionThru *thru = makeExceptionThru(pins, nullptr, nullptr,
@ -4313,8 +4313,8 @@ Sdc::deleteLoopExceptions()
void
Sdc::addException(ExceptionPath *exception)
{
debugPrint1(debug_, "exception_merge", 1, "add exception for %s",
exception->asString(network_));
debugPrint(debug_, "exception_merge", 1, "add exception for %s",
exception->asString(network_));
if (exception->isPathDelay()) {
recordPathDelayInternalStartpoints(exception);
@ -4339,8 +4339,8 @@ Sdc::addException(ExceptionPath *exception)
ExceptionTo *to = exception->to();
ExceptionTo *to1 = to ? to->clone() : nullptr;
ExceptionPath *exception1 = exception->clone(from1, thrus1, to1, true);
debugPrint1(debug_, "exception_merge", 1, " split exception for %s",
exception1->asString(network_));
debugPrint(debug_, "exception_merge", 1, " split exception for %s",
exception1->asString(network_));
addException1(exception1);
ClockSet *clks2 = new ClockSet(*from->clks());
@ -4349,8 +4349,8 @@ Sdc::addException(ExceptionPath *exception)
ExceptionThruSeq *thrus2 = exceptionThrusClone(exception->thrus(), network_);
ExceptionTo *to2 = to ? to->clone() : nullptr;
ExceptionPath *exception2 = exception->clone(from2, thrus2, to2, true);
debugPrint1(debug_, "exception_merge", 1, " split exception for %s",
exception2->asString(network_));
debugPrint(debug_, "exception_merge", 1, " split exception for %s",
exception2->asString(network_));
addException1(exception2);
delete exception;
@ -4374,8 +4374,8 @@ Sdc::addException1(ExceptionPath *exception)
to->transition(),
to->endTransition(), true);
ExceptionPath *exception1 = exception->clone(from1, thrus1, to1, true);
debugPrint1(debug_, "exception_merge", 1, " split exception for %s",
exception1->asString(network_));
debugPrint(debug_, "exception_merge", 1, " split exception for %s",
exception1->asString(network_));
addException2(exception1);
ExceptionFrom *from2 = exception->from()->clone();
@ -4384,8 +4384,8 @@ Sdc::addException1(ExceptionPath *exception)
ExceptionTo *to2 = new ExceptionTo(nullptr, clks2, nullptr, to->transition(),
to->endTransition(), true);
ExceptionPath *exception2 = exception->clone(from2, thrus2, to2, true);
debugPrint1(debug_, "exception_merge", 1, " split exception for %s",
exception2->asString(network_));
debugPrint(debug_, "exception_merge", 1, " split exception for %s",
exception2->asString(network_));
addException2(exception2);
delete exception;
@ -4447,8 +4447,8 @@ Sdc::addException2(ExceptionPath *exception)
void
Sdc::deleteMatchingExceptions(ExceptionPath *exception)
{
debugPrint1(debug_, "exception_merge", 1, "find matches for %s",
exception->asString(network_));
debugPrint(debug_, "exception_merge", 1, "find matches for %s",
exception->asString(network_));
ExceptionPathSet matches;
findMatchingExceptions(exception, matches);
@ -4750,11 +4750,11 @@ Sdc::recordMergeHash(ExceptionPath *exception,
ExceptionPt *missing_pt)
{
size_t hash = exception->hash(missing_pt);
debugPrint3(debug_, "exception_merge", 3,
"record merge hash %zu %s missing %s",
hash,
exception->asString(network_),
missing_pt->asString(network_));
debugPrint(debug_, "exception_merge", 3,
"record merge hash %zu %s missing %s",
hash,
exception->asString(network_),
missing_pt->asString(network_));
ExceptionPathSet *set = exception_merge_hash_.findKey(hash);
if (set == nullptr) {
set = new ExceptionPathSet;
@ -4977,10 +4977,10 @@ Sdc::findMergeMatch(ExceptionPath *exception)
// search at the endpoint.
&& exception->mergeable(match)
&& match->mergeablePts(exception, missing_pt, match_missing_pt)) {
debugPrint1(debug_, "exception_merge", 1, "merge %s",
exception->asString(network_));
debugPrint1(debug_, "exception_merge", 1, " with %s",
match->asString(network_));
debugPrint(debug_, "exception_merge", 1, "merge %s",
exception->asString(network_));
debugPrint(debug_, "exception_merge", 1, " with %s",
match->asString(network_));
// Unrecord the exception that is being merged away.
unrecordException(exception);
unrecordMergeHashes(match);
@ -5158,8 +5158,8 @@ Sdc::deleteExceptionsReferencing(Clock *clk)
void
Sdc::deleteException(ExceptionPath *exception)
{
debugPrint1(debug_, "exception_merge", 2, "delete %s",
exception->asString(network_));
debugPrint(debug_, "exception_merge", 2, "delete %s",
exception->asString(network_));
unrecordException(exception);
delete exception;
}
@ -5187,11 +5187,11 @@ Sdc::unrecordMergeHash(ExceptionPath *exception,
ExceptionPt *missing_pt)
{
size_t hash = exception->hash(missing_pt);
debugPrint3(debug_, "exception_merge", 3,
"unrecord merge hash %zu %s missing %s",
hash,
exception->asString(network_),
missing_pt->asString(network_));
debugPrint(debug_, "exception_merge", 3,
"unrecord merge hash %zu %s missing %s",
hash,
exception->asString(network_),
missing_pt->asString(network_));
ExceptionPathSet *matches = exception_merge_hash_.findKey(hash);
if (matches)
matches->erase(exception);
@ -5380,8 +5380,8 @@ Sdc::resetPath(ExceptionFrom *from,
while (except_iter.hasNext()) {
ExceptionPath *match = except_iter.next();
if (match->resetMatch(from, thrus, to, min_max)) {
debugPrint1(debug_, "exception_match", 3, "reset match %s",
match->asString(network_));
debugPrint(debug_, "exception_match", 3, "reset match %s",
match->asString(network_));
ExceptionPathSet expansions;
expandException(match, expansions);
deleteException(match);

2
search/Bfs.cc
View File

@ -232,7 +232,7 @@ BfsIterator::findNext(Level to_level)
void
BfsIterator::enqueue(Vertex *vertex)
{
debugPrint1(debug_, "bfs", 2, "enqueue %s", vertex->name(sdc_network_));
debugPrint(debug_, "bfs", 2, "enqueue %s", vertex->name(sdc_network_));
if (!vertex->bfsInQueue(bfs_index_)) {
Level level = vertex->level();
UniqueLock lock(queue_lock_);

14
search/CheckMinPulseWidths.cc
View File

@ -253,7 +253,7 @@ visitMinPulseWidthChecks(MinPulseWidthCheckVisitor *visitor)
while (vertex_iter.hasNext()) {
Vertex *vertex = vertex_iter.next();
if (isClkEnd(vertex, graph)) {
debugPrint1(debug, "mpw", 1, "check mpw %s", vertex->name(sdc_network));
debugPrint(debug, "mpw", 1, "check mpw %s", vertex->name(sdc_network));
visitMinPulseWidthChecks(vertex, visitor);
}
}
@ -348,17 +348,17 @@ MinPulseWidthCheck::closePath(const StaState *sta,
open_tag->isSegmentStart(),
open_tag->states(),
false, sta);
debugPrint1(sta->debug(), "mpw", 3, " open %s",
open_tag->asString(sta));
debugPrint1(sta->debug(), "mpw", 3, " close %s",
close_tag.asString(sta));
debugPrint(sta->debug(), "mpw", 3, " open %s",
open_tag->asString(sta));
debugPrint(sta->debug(), "mpw", 3, " close %s",
close_tag.asString(sta));
VertexPathIterator close_iter(open_path_.vertex(sta), close_rf,
close_ap, sta);
while (close_iter.hasNext()) {
PathVertex *close_path = close_iter.next();
if (tagMatchNoPathAp(close_path->tag(sta), &close_tag)) {
debugPrint1(sta->debug(), "mpw", 3, " match %s",
close_path->tag(sta)->asString(sta));
debugPrint(sta->debug(), "mpw", 3, " match %s",
close_path->tag(sta)->asString(sta));
close = close_path;
break;
}

4
search/ClkNetwork.cc
View File

@ -51,7 +51,7 @@ ClkNetwork::clear()
void
ClkNetwork::clkPinsInvalid()
{
debugPrint0(debug_, "clk_network", 1, "clk network invalid");
debugPrint(debug_, "clk_network", 1, "clk network invalid");
clk_pins_valid_ = false;
}
@ -98,7 +98,7 @@ ClkSearchPred::searchTo(const Vertex *to)
void
ClkNetwork::findClkPins()
{
debugPrint0(debug_, "clk_network", 1, "find clk network");
debugPrint(debug_, "clk_network", 1, "find clk network");
clear();
findClkPins(false, pin_clks_map_);
findClkPins(true, pin_ideal_clks_map_);

28
search/ClkSkew.cc
View File

@ -277,16 +277,16 @@ ClkSkews::findClkSkew(Vertex *src_vertex,
&& tgt_path->pathAnalysisPt(this)->corner() == src_corner) {
ClkSkew probe(src_path, tgt_path, this);
ClkSkew *clk_skew = skews.findKey(src_clk);
debugPrint8(debug_, "clk_skew", 2,
"%s %s %s -> %s %s %s crpr = %s skew = %s",
network_->pathName(src_path->pin(this)),
src_path->transition(this)->asString(),
time_unit->asString(probe.srcLatency(this)),
network_->pathName(tgt_path->pin(this)),
tgt_path->transition(this)->asString(),
time_unit->asString(probe.tgtLatency(this)),
delayAsString(probe.crpr(this), this),
time_unit->asString(probe.skew()));
debugPrint(debug_, "clk_skew", 2,
"%s %s %s -> %s %s %s crpr = %s skew = %s",
network_->pathName(src_path->pin(this)),
src_path->transition(this)->asString(),
time_unit->asString(probe.srcLatency(this)),
network_->pathName(tgt_path->pin(this)),
tgt_path->transition(this)->asString(),
time_unit->asString(probe.tgtLatency(this)),
delayAsString(probe.crpr(this), this),
time_unit->asString(probe.skew()));
if (clk_skew == nullptr) {
clk_skew = new ClkSkew(probe);
skews[src_clk] = clk_skew;
@ -327,16 +327,16 @@ ClkSkews::findFanout(Vertex *from,
// Return value.
VertexSet &endpoints)
{
debugPrint1(debug_, "fanout", 1, "%s",
from->name(sdc_network_));
debugPrint(debug_, "fanout", 1, "%s",
from->name(sdc_network_));
FanOutSrchPred pred(this);
BfsFwdIterator fanout_iter(BfsIndex::other, &pred, this);
fanout_iter.enqueue(from);
while (fanout_iter.hasNext()) {
Vertex *fanout = fanout_iter.next();
if (fanout->hasChecks()) {
debugPrint1(debug_, "fanout", 1, " endpoint %s",
fanout->name(sdc_network_));
debugPrint(debug_, "fanout", 1, " endpoint %s",
fanout->name(sdc_network_));
endpoints.insert(fanout);
}
fanout_iter.enqueueAdjacentVertices(fanout);

18
search/Crpr.cc
View File

@ -257,8 +257,8 @@ CheckCrpr::findCrpr(const PathVertex *src_clk_path,
if (src_clk_path2 && tgt_clk_path2
&& (src_clk_path2->transition(this) == tgt_clk_path2->transition(this)
|| same_pin)) {
debugPrint1(debug_, "crpr", 2, "crpr pin %s",
network_->pathName(src_clk_path2->pin(this)));
debugPrint(debug_, "crpr", 2, "crpr pin %s",
network_->pathName(src_clk_path2->pin(this)));
crpr = findCrpr1(src_clk_path2, tgt_clk_path2);
crpr_pin = src_clk_path2->pin(this);
}
@ -311,14 +311,14 @@ CheckCrpr::findCrpr1(const PathVertex *src_clk_path,
// is the min of the source and target max-min delay.
float src_delta = crprArrivalDiff(src_clk_path);
float tgt_delta = crprArrivalDiff(tgt_clk_path);
debugPrint1(debug_, "crpr", 2, " src delta %s",
delayAsString(src_delta, this));
debugPrint1(debug_, "crpr", 2, " tgt delta %s",
delayAsString(tgt_delta, this));
debugPrint(debug_, "crpr", 2, " src delta %s",
delayAsString(src_delta, this));
debugPrint(debug_, "crpr", 2, " tgt delta %s",
delayAsString(tgt_delta, this));
float common_delay = min(src_delta, tgt_delta);
debugPrint2(debug_, "crpr", 2, " %s delta %s",
network_->pathName(src_clk_path->pin(this)),
delayAsString(common_delay, this));
debugPrint(debug_, "crpr", 2, " %s delta %s",
network_->pathName(src_clk_path->pin(this)),
delayAsString(common_delay, this));
return common_delay;
}
}

64
search/Genclks.cc
View File

@ -195,7 +195,7 @@ Genclks::ensureInsertionDelays()
{
if (!found_insertion_delays_) {
Stats stats(debug_, report_);
debugPrint0(debug_, "genclk", 1, "find generated clk insertion delays");
debugPrint(debug_, "genclk", 1, "find generated clk insertion delays");
ClockSeq gclks;
for (auto clk : sdc_->clks()) {
@ -314,9 +314,9 @@ Genclks::ensureMaster(Clock *gclk)
// Master source pin can actually be a clock source pin.
if (master_clk != gclk) {
gclk->setInferedMasterClk(master_clk);
debugPrint2(debug_, "genclk", 2, " %s master clk %s",
gclk->name(),
master_clk->name());
debugPrint(debug_, "genclk", 2, " %s master clk %s",
gclk->name(),
master_clk->name());
found_master = true;
master_clk_count++;
}
@ -341,9 +341,9 @@ Genclks::ensureMaster(Clock *gclk)
// Master source pin can actually be a clock source pin.
if (master_clk != gclk) {
gclk->setInferedMasterClk(master_clk);
debugPrint2(debug_, "genclk", 2, " %s master clk %s",
gclk->name(),
master_clk->name());
debugPrint(debug_, "genclk", 2, " %s master clk %s",
gclk->name(),
master_clk->name());
found_master = true;
master_clk_count++;
}
@ -366,9 +366,9 @@ Genclks::ensureMaster(Clock *gclk)
// Master source pin can actually be a clock source pin.
if (master_clk != gclk) {
gclk->setInferedMasterClk(master_clk);
debugPrint2(debug_, "genclk", 2, " %s master clk %s",
gclk->name(),
master_clk->name());
debugPrint(debug_, "genclk", 2, " %s master clk %s",
gclk->name(),
master_clk->name());
master_clk_count++;
break;
}
@ -463,8 +463,8 @@ Genclks::findFanin(Clock *gclk,
Vertex *vertex = iter.next();
if (!fanins->hasKey(vertex)) {
fanins->insert(vertex);
debugPrint2(debug_, "genclk", 2, "gen clk %s fanin %s",
gclk->name(), vertex->name(sdc_network_));
debugPrint(debug_, "genclk", 2, "gen clk %s fanin %s",
gclk->name(), vertex->name(sdc_network_));
iter.enqueueAdjacentVertices(vertex);
}
}
@ -568,8 +568,8 @@ GenClkInsertionSearchPred::isNonGeneratedClkPin(const Pin *pin) const
void
Genclks::findInsertionDelays(Clock *gclk)
{
debugPrint1(debug_, "genclk", 2, "find gen clk %s insertion",
gclk->name());
debugPrint(debug_, "genclk", 2, "find gen clk %s insertion",
gclk->name());
GenclkInfo *genclk_info = makeGenclkInfo(gclk);
FilterPath *src_filter = genclk_info->srcFilter();
GenClkInsertionSearchPred srch_pred(gclk, nullptr, genclk_info, this);
@ -670,9 +670,9 @@ Genclks::findLatchFdbkEdges(Vertex *from_vertex,
Edge *edge = edge_iter.next();
Vertex *to_vertex = edge->to(graph_);
if (path_vertices.hasKey(to_vertex)) {
debugPrint2(debug_, "genclk", 2, " found feedback edge %s -> %s",
from_vertex->name(sdc_network_),
to_vertex->name(sdc_network_));
debugPrint(debug_, "genclk", 2, " found feedback edge %s -> %s",
from_vertex->name(sdc_network_),
to_vertex->name(sdc_network_));
if (fdbk_edges == nullptr)
fdbk_edges = new EdgeSet;
fdbk_edges->insert(edge);
@ -716,8 +716,8 @@ Genclks::seedSrcPins(Clock *gclk,
Clock *master_clk = gclk->masterClk();
for (Pin *master_pin : master_clk->leafPins()) {
Vertex *vertex = graph_->pinDrvrVertex(master_pin);
debugPrint1(debug_, "genclk", 2, " seed src pin %s",
network_->pathName(master_pin));
debugPrint(debug_, "genclk", 2, " seed src pin %s",
network_->pathName(master_pin));
TagGroupBldr tag_bldr(true, this);
tag_bldr.init(vertex);
copyGenClkSrcPaths(vertex, &tag_bldr);
@ -868,8 +868,8 @@ GenclkSrcArrivalVisitor::visit(Vertex *vertex)
const Graph *graph = sta_->graph();
Search *search = sta_->search();
Genclks *genclks = search->genclks();
debugPrint1(debug, "genclk", 2, "find gen clk insert arrival %s",
vertex->name(sdc_network));
debugPrint(debug, "genclk", 2, "find gen clk insert arrival %s",
vertex->name(sdc_network));
tag_bldr_->init(vertex);
has_fanin_one_ = graph->hasFaninOne(vertex);
genclks->copyGenClkSrcPaths(vertex, tag_bldr_);
@ -973,11 +973,11 @@ Genclks::recordSrcPaths(Clock *gclk)
src_path.arrival(this),
early_late,
this))) {
debugPrint4(debug_, "genclk", 2, " %s insertion %s %s %s",
network_->pathName(gclk_pin),
early_late->asString(),
rf->asString(),
delayAsString(path->arrival(this), this));
debugPrint(debug_, "genclk", 2, " %s insertion %s %s %s",
network_->pathName(gclk_pin),
early_late->asString(),
rf->asString(),
delayAsString(path->arrival(this), this));
src_path.init(path, this);
found_src_paths = true;
}
@ -1096,8 +1096,8 @@ Genclks::insertionDelay(const Clock *clk,
void
Genclks::findPllDelays(Clock *gclk)
{
debugPrint1(debug_, "genclk", 2, "find gen clk %s pll delay",
gclk->name());
debugPrint(debug_, "genclk", 2, "find gen clk %s pll delay",
gclk->name());
FilterPath *pll_filter = makePllFilter(gclk);
GenclkInfo *genclk_info = genclkInfo(gclk);
genclk_info->setPllFilter(pll_filter);
@ -1131,8 +1131,8 @@ Genclks::seedPllPin(const Clock *gclk,
{
Pin *pll_out_pin = gclk->pllOut();
Vertex *vertex = graph_->pinDrvrVertex(pll_out_pin);
debugPrint1(debug_, "genclk", 2, " seed pllout pin %s",
network_->pathName(pll_out_pin));
debugPrint(debug_, "genclk", 2, " seed pllout pin %s",
network_->pathName(pll_out_pin));
TagGroupBldr tag_bldr(true, this);
tag_bldr.init(vertex);
copyGenClkSrcPaths(vertex, &tag_bldr);
@ -1191,8 +1191,8 @@ PllArrivalVisitor::visit(Vertex *vertex)
Graph *graph = sta_->graph();
Search *search = sta_->search();
Genclks *genclks = search->genclks();
debugPrint1(debug, "genclk", 2, "find gen clk pll arrival %s",
vertex->name(sdc_network));
debugPrint(debug, "genclk", 2, "find gen clk pll arrival %s",
vertex->name(sdc_network));
tag_bldr_->init(vertex);
genclks->copyGenClkSrcPaths(vertex, tag_bldr_);
has_fanin_one_ = graph->hasFaninOne(vertex);

8
search/Latches.cc
View File

@ -94,10 +94,10 @@ Latches::latchRequired(const Path *data_path,
+ PathEnd::checkSetupMcpAdjustment(data_clk_edge, enable_clk_edge, mcp,
1, sdc_)
+ open_crpr;
debugPrint3(debug_, "latch", 1, "latch data %s %s enable %s",
network_->pathName(data_path->pin(this)),
delayAsString(data_arrival, this),
delayAsString(enable_arrival, this));
debugPrint(debug_, "latch", 1, "latch data %s %s enable %s",
network_->pathName(data_path->pin(this)),
delayAsString(data_arrival, this),
delayAsString(enable_arrival, this));
if (delayLessEqual(data_arrival, enable_arrival, this)) {
// Data arrives before latch opens.
required = enable_arrival;

44
search/Levelize.cc
View File

@ -115,7 +115,7 @@ void
Levelize::levelize()
{
Stats stats(debug_, report_);
debugPrint0(debug_, "levelize", 1, "levelize");
debugPrint(debug_, "levelize", 1, "levelize");
max_level_ = 0;
clearLoopEdges();
deleteLoops();
@ -145,7 +145,7 @@ Levelize::findRoots()
Vertex *vertex = vertex_iter.next();
setLevel(vertex, 0);
if (isRoot(vertex)) {
debugPrint1(debug_, "levelize", 2, "root %s", vertex->name(sdc_network_));
debugPrint(debug_, "levelize", 2, "root %s", vertex->name(sdc_network_));
roots_.insert(vertex);
if (hasFanout(vertex, search_pred_, graph_))
// Color roots with no fanout black so that they are
@ -209,8 +209,8 @@ Levelize::visit(Vertex *vertex,
EdgeSeq &path)
{
Pin *from_pin = vertex->pin();
debugPrint2(debug_, "levelize", 3, "level %d %s",
level, vertex->name(sdc_network_));
debugPrint(debug_, "levelize", 3, "level %d %s",
level, vertex->name(sdc_network_));
vertex->setColor(LevelColor::gray);
setLevel(vertex, level);
max_level_ = max(level, max_level_);
@ -254,10 +254,10 @@ void
Levelize::recordLoop(Edge *edge,
EdgeSeq &path)
{
debugPrint3(debug_, "levelize", 2, "Loop edge %s -> %s (%s)",
edge->from(graph_)->name(sdc_network_),
edge->to(graph_)->name(sdc_network_),
edge->role()->asString());
debugPrint(debug_, "levelize", 2, "Loop edge %s -> %s (%s)",
edge->from(graph_)->name(sdc_network_),
edge->to(graph_)->name(sdc_network_),
edge->role()->asString());
// Do not record loops if they have been invalidated.
if (loops_) {
EdgeSeq *loop_edges = loopEdges(path, edge);
@ -276,7 +276,7 @@ EdgeSeq *
Levelize::loopEdges(EdgeSeq &path,
Edge *closing_edge)
{
debugPrint0(debug_, "loop", 2, "Loop");
debugPrint(debug_, "loop", 2, "Loop");
EdgeSeq *loop_edges = new EdgeSeq;
// Skip the "head" of the path up to where closing_edge closes the loop.
Pin *loop_pin = closing_edge->to(graph_)->pin();
@ -288,16 +288,16 @@ Levelize::loopEdges(EdgeSeq &path,
if (from_pin == loop_pin)
copy = true;
if (copy) {
debugPrint2(debug_, "loop", 2, " %s -> %s",
edge->from(graph_)->name(sdc_network_),
edge->to(graph_)->name(sdc_network_));
debugPrint(debug_, "loop", 2, " %s -> %s",
edge->from(graph_)->name(sdc_network_),
edge->to(graph_)->name(sdc_network_));
loop_edges->push_back(edge);
loop_edges_.insert(edge);
}
}
debugPrint2(debug_, "loop", 2, " %s -> %s",
closing_edge->from(graph_)->name(sdc_network_),
closing_edge->to(graph_)->name(sdc_network_));
debugPrint(debug_, "loop", 2, " %s -> %s",
closing_edge->from(graph_)->name(sdc_network_),
closing_edge->to(graph_)->name(sdc_network_));
loop_edges->push_back(closing_edge);
loop_edges_.insert(closing_edge);
return loop_edges;
@ -355,15 +355,15 @@ Levelize::levelizeCycles()
void
Levelize::invalid()
{
debugPrint0(debug_, "levelize", 1, "levels invalid");
debugPrint(debug_, "levelize", 1, "levels invalid");
clear();
}
void
Levelize::invalidFrom(Vertex *vertex)
{
debugPrint1(debug_, "levelize", 1, "level invalid from %s",
vertex->name(sdc_network_));
debugPrint(debug_, "levelize", 1, "level invalid from %s",
vertex->name(sdc_network_));
VertexInEdgeIterator edge_iter(vertex, graph_);
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
@ -384,8 +384,8 @@ Levelize::deleteVertexBefore(Vertex *vertex)
void
Levelize::relevelizeFrom(Vertex *vertex)
{
debugPrint1(debug_, "levelize", 1, "invalid relevelize from %s",
vertex->name(sdc_network_));
debugPrint(debug_, "levelize", 1, "invalid relevelize from %s",
vertex->name(sdc_network_));
relevelize_from_.insert(vertex);
levels_valid_ = false;
}
@ -416,8 +416,8 @@ Levelize::relevelize()
VertexSet::Iterator vertex_iter(relevelize_from_);
while (vertex_iter.hasNext()) {
Vertex *vertex = vertex_iter.next();
debugPrint1(debug_, "levelize", 1, "relevelize from %s",
vertex->name(sdc_network_));
debugPrint(debug_, "levelize", 1, "relevelize from %s",
vertex->name(sdc_network_));
if (search_pred_->searchFrom(vertex)) {
if (isRoot(vertex)) {
setLevel(vertex, 0);

40
search/PathEnum.cc
View File

@ -119,13 +119,13 @@ PathEnum::PathEnum(int group_count,
void
PathEnum::insert(PathEnd *path_end)
{
debugPrint1(debug_, "path_enum", 1, "insert %s",
path_end->path()->name(this));
debugPrint3(debug_, "path_enum", 2, "diversion %s %s %s",
path_end->path()->name(this),
cmp_slack_ ? "slack" : "delay",
delayAsString(cmp_slack_ ? path_end->slack(this) :
path_end->dataArrivalTime(this), this));
debugPrint(debug_, "path_enum", 1, "insert %s",
path_end->path()->name(this));
debugPrint(debug_, "path_enum", 2, "diversion %s %s %s",
path_end->path()->name(this),
cmp_slack_ ? "slack" : "delay",
delayAsString(cmp_slack_ ? path_end->slack(this) :
path_end->dataArrivalTime(this), this));
Diversion *div = new Diversion(path_end, path_end->path());
div_queue_.push(div);
div_count_++;
@ -195,8 +195,8 @@ PathEnum::findNext()
}
else {
// We have endpoint_count paths for this endpoint, so we are done with it.
debugPrint1(debug_, "path_enum", 1, "endpoint_count reached for %s",
vertex->name(sdc_network_));
debugPrint(debug_, "path_enum", 1, "endpoint_count reached for %s",
vertex->name(sdc_network_));
deleteDiversionPathEnd(div);
}
}
@ -330,12 +330,12 @@ PathEnumFaninVisitor::visitFromToPath(const Pin *,
const PathAnalysisPt *path_ap)
{
const Debug *debug = sta_->debug();
debugPrint4(debug, "path_enum", 3, "visit fanin %s -> %s %s %s",
from_path->name(sta_),
to_vertex->name(sta_->network()),
to_rf->asString(),
delayAsString(sta_->search()->deratedDelay(from_vertex, arc, edge,
false,path_ap),sta_));
debugPrint(debug, "path_enum", 3, "visit fanin %s -> %s %s %s",
from_path->name(sta_),
to_vertex->name(sta_->network()),
to_rf->asString(),
delayAsString(sta_->search()->deratedDelay(from_vertex, arc, edge,
false,path_ap),sta_));
// These paths fanin to before_div_ so we know to_vertex matches.
if (to_rf->index() == before_div_rf_index_
&& path_ap->index() == before_div_ap_index_
@ -434,7 +434,7 @@ PathEnum::makeDiversion(PathEnd *div_end,
void
PathEnum::pruneDiversionQueue()
{
debugPrint0(debug_, "path_enum", 2, "prune queue");
debugPrint(debug_, "path_enum", 2, "prune queue");
VertexPathCountMap path_counts;
int end_count = 0;
// Collect endpoint_count diversions per vertex.
@ -590,10 +590,10 @@ PathEnum::updatePathHeadDelays(PathEnumedSeq &paths,
ArcDelay arc_delay = search_->deratedDelay(edge->from(graph_),
arc, edge, false, path_ap);
Arrival arrival = prev_arrival + arc_delay;
debugPrint3(debug_, "path_enum", 3, "update arrival %s %s -> %s",
path->name(this),
delayAsString(path->arrival(this), this),
delayAsString(arrival, this));
debugPrint(debug_, "path_enum", 3, "update arrival %s %s -> %s",
path->name(this),
delayAsString(path->arrival(this), this),
delayAsString(arrival, this));
path->setArrival(arrival, this);
prev_arrival = arrival;
if (sdc_->crprActive()) {

20
search/PathGroup.cc
View File

@ -686,11 +686,11 @@ MakePathEndsAll::vertexEnd(Vertex *)
// Only save the worst path end for each crpr tag.
// PathEnum will peel the others.
if (!unique_ends.hasKey(path_end)) {
debugPrint4(debug, "path_enum", 5, "insert %s %s %s %d",
path_end->vertex(sta_)->name(network),
path_end->typeName(),
path_end->transition(sta_)->asString(),
path_end->path()->tag(sta_)->index());
debugPrint(debug, "path_enum", 5, "insert %s %s %s %d",
path_end->vertex(sta_)->name(network),
path_end->typeName(),
path_end->transition(sta_)->asString(),
path_end->path()->tag(sta_)->index());
// Give the group a copy of the path end because
// it may delete it during pruning.
if (group->savable(path_end)) {
@ -700,11 +700,11 @@ MakePathEndsAll::vertexEnd(Vertex *)
}
}
else
debugPrint4(debug, "path_enum", 5, "prune %s %s %s %d",
path_end->vertex(sta_)->name(network),
path_end->typeName(),
path_end->transition(sta_)->asString(),
path_end->path()->tag(sta_)->index());
debugPrint(debug, "path_enum", 5, "prune %s %s %s %d",
path_end->vertex(sta_)->name(network),
path_end->typeName(),
path_end->transition(sta_)->asString(),
path_end->path()->tag(sta_)->index());
}
// Clear ends for next vertex.
PathEndSeq::Iterator end_iter2(ends);

129
search/Power.cc
View File

@ -344,8 +344,8 @@ void
PropActivityVisitor::visit(Vertex *vertex)
{
Pin *pin = vertex->pin();
debugPrint1(debug_, "power_activity", 3, "visit %s",
vertex->name(network_));
debugPrint(debug_, "power_activity", 3, "visit %s",
vertex->name(network_));
if (power_->hasUserActivity(pin))
power_->setActivity(pin, power_->userActivity(pin));
else {
@ -369,8 +369,8 @@ PropActivityVisitor::visit(Vertex *vertex)
Instance *inst = network_->instance(pin);
auto cell = network_->libertyCell(inst);
if (cell && cell->hasSequentials()) {
debugPrint1(debug_, "power_activity", 3, "pending reg %s",
network_->pathName(inst));
debugPrint(debug_, "power_activity", 3, "pending reg %s",
network_->pathName(inst));
visited_regs_->insert(inst);
found_reg_without_activity_ = input_without_activity;
}
@ -383,10 +383,10 @@ PropActivityVisitor::visit(Vertex *vertex)
Instance *inst = network_->instance(pin);
PwrActivity activity = power_->evalActivity(func, inst);
power_->setActivity(pin, activity);
debugPrint3(debug_, "power_activity", 3, "set %s %.2e %.2f",
vertex->name(network_),
activity.activity(),
activity.duty());
debugPrint(debug_, "power_activity", 3, "set %s %.2e %.2f",
vertex->name(network_),
activity.activity(),
activity.duty());
}
}
}
@ -530,8 +530,8 @@ Power::seedActivities(BfsFwdIterator &bfs)
// Clock activities are baked in.
if (!sdc_->isLeafPinClock(pin)
&& !network_->direction(pin)->isInternal()) {
debugPrint1(debug_, "power_activity", 3, "seed %s",
vertex->name(network_));
debugPrint(debug_, "power_activity", 3, "seed %s",
vertex->name(network_));
if (hasUserActivity(pin))
setActivity(pin, userActivity(pin));
else
@ -564,8 +564,8 @@ Power::seedRegOutputActivities(const Instance *inst,
Vertex *vertex = graph_->pinDrvrVertex(pin);
if (func->port() == seq->output()
|| func->port() == seq->outputInv()) {
debugPrint1(debug_, "power_activity", 3, "enqueue reg output %s",
vertex->name(network_));
debugPrint(debug_, "power_activity", 3, "enqueue reg output %s",
vertex->name(network_));
bfs.enqueue(vertex);
}
}
@ -652,16 +652,16 @@ Power::findInputInternalPower(const Pin *pin,
const LibertyPort *corner_port = port->cornerPort(lib_ap_index);
auto internal_pwrs = corner_cell->internalPowers(corner_port);
if (!internal_pwrs->empty()) {
debugPrint3(debug_, "power", 2, "internal input %s/%s (%s)",
network_->pathName(inst),
port->name(),
corner_cell->name());
debugPrint(debug_, "power", 2, "internal input %s/%s (%s)",
network_->pathName(inst),
port->name(),
corner_cell->name());
const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(MinMax::max());
const Pvt *pvt = dcalc_ap->operatingConditions();
Vertex *vertex = graph_->pinLoadVertex(pin);
debugPrint1(debug_, "power", 2, " cap = %s",
units_->capacitanceUnit()->asString(load_cap));
debugPrint0(debug_, "power", 2, " whena act/ns duty energy power");
debugPrint(debug_, "power", 2, " cap = %s",
units_->capacitanceUnit()->asString(load_cap));
debugPrint(debug_, "power", 2, " whena act/ns duty energy power");
float internal = 0.0;
for (InternalPower *pwr : *internal_pwrs) {
const char *related_pg_pin = pwr->relatedPgPin();
@ -694,14 +694,14 @@ Power::findInputInternalPower(const Pin *pin,
duty = evalActivity(when, inst).duty();
}
float port_internal = energy * duty * activity.activity();
debugPrint7(debug_, "power", 2, " %3s %6s %.2f %.2f %9.2e %9.2e %s",
port->name(),
when ? when->asString() : "",
activity.activity() * 1e-9,
duty,
energy,
port_internal,
related_pg_pin ? related_pg_pin : "no pg_pin");
debugPrint(debug_, "power", 2, " %3s %6s %.2f %.2f %9.2e %9.2e %s",
port->name(),
when ? when->asString() : "",
activity.activity() * 1e-9,
duty,
energy,
port_internal,
related_pg_pin ? related_pg_pin : "no pg_pin");
internal += port_internal;
}
result.internal() += internal;
@ -768,17 +768,17 @@ Power::findOutputInternalPower(const Pin *to_pin,
// Return values.
PowerResult &result)
{
debugPrint3(debug_, "power", 2, "internal output %s/%s (%s)",
network_->pathName(inst),
to_port->name(),
cell->name());
debugPrint(debug_, "power", 2, "internal output %s/%s (%s)",
network_->pathName(inst),
to_port->name(),
cell->name());
const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(MinMax::max());
const Pvt *pvt = dcalc_ap->operatingConditions();
int lib_ap_index = corner->libertyIndex(MinMax::max());
LibertyCell *corner_cell = cell->cornerCell(lib_ap_index);
const LibertyPort *to_corner_port = to_port->cornerPort(lib_ap_index);
debugPrint1(debug_, "power", 2, " cap = %s",
units_->capacitanceUnit()->asString(load_cap));
debugPrint(debug_, "power", 2, " cap = %s",
units_->capacitanceUnit()->asString(load_cap));
FuncExpr *func = to_port->function();
map<const char*, float, StringLessIf> pg_duty_sum;
@ -806,7 +806,8 @@ Power::findOutputInternalPower(const Pin *to_pin,
}
float energy = 0.0;
int tr_count = 0;
debugPrint0(debug_, "power", 2, " when act/ns duty wgt energy power");
debugPrint(debug_, "power", 2,
" when act/ns duty wgt energy power");
for (auto to_rf : RiseFall::range()) {
// Use unateness to find from_rf.
RiseFall *from_rf = positive_unate ? to_rf : to_rf->opposite();
@ -830,16 +831,16 @@ Power::findOutputInternalPower(const Pin *to_pin,
weight = duty / duty_sum;
}
float port_internal = weight * energy * to_activity.activity();
debugPrint9(debug_, "power", 2, "%3s -> %-3s %6s %.2f %.2f %.2f %9.2e %9.2e %s",
from_corner_port->name(),
to_port->name(),
when ? when->asString() : "",
to_activity.activity() * 1e-9,
duty,
weight,
energy,
port_internal,
related_pg_pin ? related_pg_pin : "no pg_pin");
debugPrint(debug_, "power", 2, "%3s -> %-3s %6s %.2f %.2f %.2f %9.2e %9.2e %s",
from_corner_port->name(),
to_port->name(),
when ? when->asString() : "",
to_activity.activity() * 1e-9,
duty,
weight,
energy,
port_internal,
related_pg_pin ? related_pg_pin : "no pg_pin");
internal += port_internal;
}
result.internal() += internal;
@ -942,18 +943,18 @@ Power::findLeakagePower(const Instance *,
if (port->direction()->isAnyInput())
duty *= port->isClock() ? 0.25 : 0.5;
}
debugPrint4(debug_, "power", 2, "leakage %s %s %.3e * %.2f",
cell->name(),
when->asString(),
leak->power(),
duty);
debugPrint(debug_, "power", 2, "leakage %s %s %.3e * %.2f",
cell->name(),
when->asString(),
leak->power(),
duty);
cond_leakage += leak->power() * duty;
found_cond = true;
}
else {
debugPrint2(debug_, "power", 2, "leakage default %s %.3e",
cell->name(),
leak->power());
debugPrint(debug_, "power", 2, "leakage default %s %.3e",
cell->name(),
leak->power());
default_leakage += leak->power();
found_default = true;
}
@ -963,9 +964,9 @@ Power::findLeakagePower(const Instance *,
bool cell_leakage_exists;
cell->leakagePower(cell_leakage, cell_leakage_exists);
if (cell_leakage_exists)
debugPrint2(debug_, "power", 2, "leakage cell %s %.3e",
cell->name(),
cell_leakage);
debugPrint(debug_, "power", 2, "leakage cell %s %.3e",
cell->name(),
cell_leakage);
// Ignore default leakages unless there are no conditional leakage groups.
if (found_cond)
leakage = cond_leakage;
@ -973,9 +974,9 @@ Power::findLeakagePower(const Instance *,
leakage = default_leakage;
else if (cell_leakage_exists)
leakage = cell_leakage;
debugPrint2(debug_, "power", 2, "leakage cell %s %.3e",
cell->name(),
leakage);
debugPrint(debug_, "power", 2, "leakage cell %s %.3e",
cell->name(),
leakage);
result.leakage() += leakage;
}
@ -994,12 +995,12 @@ Power::findSwitchingPower(LibertyCell *cell,
LibertyCell *corner_cell = cell->cornerCell(lib_ap_index);
float volt = portVoltage(corner_cell, to_port, dcalc_ap);
float switching = .5 * load_cap * volt * volt * activity.activity();
debugPrint5(debug_, "power", 2, "switching %s/%s activity = %.2e volt = %.2f %.3e",
cell->name(),
to_port->name(),
activity.activity(),
volt,
switching);
debugPrint(debug_, "power", 2, "switching %s/%s activity = %.2e volt = %.2f %.3e",
cell->name(),
to_port->name(),
activity.activity(),
volt,
switching);
result.switching() += switching;
}

218
search/Search.cc
View File

@ -392,7 +392,7 @@ Search::copyState(const StaState *sta)
void
Search::deletePaths()
{
debugPrint0(debug_, "search", 1, "delete paths");
debugPrint(debug_, "search", 1, "delete paths");
if (arrivals_exist_) {
VertexIterator vertex_iter(graph_);
while (vertex_iter.hasNext()) {
@ -565,10 +565,10 @@ Search::findFilteredArrivals()
// Iterate until data arrivals at all latches stop changing.
for (int pass = 1; pass <= 2 || havePendingLatchOutputs() ; pass++) {
enqueuePendingLatchOutputs();
debugPrint1(debug_, "search", 1, "find arrivals pass %d", pass);
debugPrint(debug_, "search", 1, "find arrivals pass %d", pass);
int arrival_count = arrival_iter_->visitParallel(max_level,
arrival_visitor_);
debugPrint1(debug_, "search", 1, "found %d arrivals", arrival_count);
debugPrint(debug_, "search", 1, "found %d arrivals", arrival_count);
}
arrivals_exist_ = true;
}
@ -655,7 +655,7 @@ void
Search::arrivalsInvalid()
{
if (arrivals_exist_) {
debugPrint0(debug_, "search", 1, "arrivals invalid");
debugPrint(debug_, "search", 1, "arrivals invalid");
// Delete paths to make sure no state is left over.
// For example, set_disable_timing strands a vertex, which means
// the search won't revisit it to clear the previous arrival.
@ -682,7 +682,7 @@ Search::arrivalsInvalid()
void
Search::requiredsInvalid()
{
debugPrint0(debug_, "search", 1, "requireds invalid");
debugPrint(debug_, "search", 1, "requireds invalid");
requireds_exist_ = false;
requireds_seeded_ = false;
invalid_requireds_.clear();
@ -695,8 +695,8 @@ void
Search::arrivalInvalid(Vertex *vertex)
{
if (arrivals_exist_) {
debugPrint1(debug_, "search", 2, "arrival invalid %s",
vertex->name(sdc_network_));
debugPrint(debug_, "search", 2, "arrival invalid %s",
vertex->name(sdc_network_));
if (!arrival_iter_->inQueue(vertex)) {
// Lock for StaDelayCalcObserver called by delay calc threads.
UniqueLock lock(invalid_arrivals_lock_);
@ -765,8 +765,8 @@ void
Search::requiredInvalid(Vertex *vertex)
{
if (requireds_exist_) {
debugPrint1(debug_, "search", 2, "required invalid %s",
vertex->name(sdc_network_));
debugPrint(debug_, "search", 2, "required invalid %s",
vertex->name(sdc_network_));
if (!required_iter_->inQueue(vertex)) {
// Lock for StaDelayCalcObserver called by delay calc threads.
UniqueLock lock(invalid_arrivals_lock_);
@ -784,7 +784,7 @@ Search::findClkArrivals()
if (!clk_arrivals_valid_) {
genclks_->ensureInsertionDelays();
Stats stats(debug_, report_);
debugPrint0(debug_, "search", 1, "find clk arrivals");
debugPrint(debug_, "search", 1, "find clk arrivals");
arrival_iter_->clear();
seedClkVertexArrivals();
ClkArrivalSearchPred search_clk(this);
@ -916,7 +916,7 @@ Search::findAllArrivals(VertexVisitor *arrival_visitor)
// Iterate until data arrivals at all latches stop changing.
for (int pass = 1; pass == 1 || havePendingLatchOutputs(); pass++) {
enqueuePendingLatchOutputs();
debugPrint1(debug_, "search", 1, "find arrivals pass %d", pass);
debugPrint(debug_, "search", 1, "find arrivals pass %d", pass);
findArrivals(levelize_->maxLevel(), arrival_visitor);
}
}
@ -958,7 +958,7 @@ void
Search::findArrivals(Level level,
VertexVisitor *arrival_visitor)
{
debugPrint1(debug_, "search", 1, "find arrivals to level %d", level);
debugPrint(debug_, "search", 1, "find arrivals to level %d", level);
findArrivals1();
Stats stats(debug_, report_);
int arrival_count = arrival_iter_->visitParallel(level, arrival_visitor);
@ -969,7 +969,7 @@ Search::findArrivals(Level level,
arrivals_at_endpoints_exist_ = true;
}
arrivals_exist_ = true;
debugPrint1(debug_, "search", 1, "found %u arrivals", arrival_count);
debugPrint(debug_, "search", 1, "found %u arrivals", arrival_count);
}
void
@ -1061,8 +1061,8 @@ ArrivalVisitor::visit(Vertex *vertex)
const Graph *graph = sta_->graph();
const Sdc *sdc = sta_->sdc();
Search *search = sta_->search();
debugPrint1(debug, "search", 2, "find arrivals %s",
vertex->name(sdc_network));
debugPrint(debug, "search", 2, "find arrivals %s",
vertex->name(sdc_network));
Pin *pin = vertex->pin();
// Don't clobber clock sources.
if (!sdc->isLeafPinClock(pin)
@ -1101,8 +1101,8 @@ ArrivalVisitor::visit(Vertex *vertex)
// For example, "set_max_delay -to" from an unclocked source register.
bool is_clk = tag_bldr_->hasClkTag();
if (vertex->isRegClk() && !is_clk) {
debugPrint1(debug, "search", 2, "arrival seed unclked reg clk %s",
network->pathName(pin));
debugPrint(debug, "search", 2, "arrival seed unclked reg clk %s",
network->pathName(pin));
search->makeUnclkedPaths(vertex, true, tag_bldr_);
}
@ -1122,7 +1122,7 @@ ArrivalVisitor::visit(Vertex *vertex)
|| !sdc->isPathDelayInternalEndpoint(pin)))
search->arrivalIterator()->enqueueAdjacentVertices(vertex, adj_pred_);
if (arrivals_changed) {
debugPrint0(debug, "search", 4, "arrival changed");
debugPrint(debug, "search", 4, "arrival changed");
// Only update arrivals when delays change by more than
// fuzzyEqual can distinguish.
search->setVertexArrivals(vertex, tag_bldr_);
@ -1221,16 +1221,16 @@ ArrivalVisitor::visitFromToPath(const Pin *,
{
const Debug *debug = sta_->debug();
const Network *sdc_network = sta_->sdcNetwork();
debugPrint1(debug, "search", 3, " %s",
from_vertex->name(sdc_network));
debugPrint3(debug, "search", 3, " %s -> %s %s",
from_rf->asString(),
to_rf->asString(),
min_max->asString());
debugPrint1(debug, "search", 3, " from tag: %s",
from_tag->asString(sta_));
debugPrint1(debug, "search", 3, " to tag : %s",
to_tag->asString(sta_));
debugPrint(debug, "search", 3, " %s",
from_vertex->name(sdc_network));
debugPrint(debug, "search", 3, " %s -> %s %s",
from_rf->asString(),
to_rf->asString(),
min_max->asString());
debugPrint(debug, "search", 3, " from tag: %s",
from_tag->asString(sta_));
debugPrint(debug, "search", 3, " to tag : %s",
to_tag->asString(sta_));
ClkInfo *to_clk_info = to_tag->clkInfo();
bool to_is_clk = to_tag->isClock();
Arrival arrival;
@ -1239,12 +1239,12 @@ ArrivalVisitor::visitFromToPath(const Pin *,
tag_bldr_->tagMatchArrival(to_tag, tag_match, arrival, arrival_index);
if (tag_match == nullptr
|| delayGreater(to_arrival, arrival, min_max, sta_)) {
debugPrint5(debug, "search", 3, " %s + %s = %s %s %s",
delayAsString(from_path->arrival(sta_), sta_),
delayAsString(arc_delay, sta_),
delayAsString(to_arrival, sta_),
min_max == MinMax::max() ? ">" : "<",
tag_match ? delayAsString(arrival, sta_) : "MIA");
debugPrint(debug, "search", 3, " %s + %s = %s %s %s",
delayAsString(from_path->arrival(sta_), sta_),
delayAsString(arc_delay, sta_),
delayAsString(to_arrival, sta_),
min_max == MinMax::max() ? ">" : "<",
tag_match ? delayAsString(arrival, sta_) : "MIA");
PathVertexRep prev_path;
if (to_tag->isClock() || to_tag->isGenClkSrcPath())
prev_path.init(from_path, sta_);
@ -1294,15 +1294,15 @@ ArrivalVisitor::pruneCrprArrivals()
Arrival max_arrival_max_crpr = (min_max == MinMax::max())
? max_arrival - max_crpr
: max_arrival + max_crpr;
debugPrint4(debug, "search", 4, " cmp %s %s - %s = %s",
tag->asString(sta_),
delayAsString(max_arrival, sta_),
delayAsString(max_crpr, sta_),
delayAsString(max_arrival_max_crpr, sta_));
debugPrint(debug, "search", 4, " cmp %s %s - %s = %s",
tag->asString(sta_),
delayAsString(max_arrival, sta_),
delayAsString(max_crpr, sta_),
delayAsString(max_arrival_max_crpr, sta_));
Arrival arrival = tag_bldr_->arrival(arrival_index);
if (delayGreater(max_arrival_max_crpr, arrival, min_max, sta_)) {
debugPrint1(debug, "search", 3, " pruned %s",
tag->asString(sta_));
debugPrint(debug, "search", 3, " pruned %s",
tag->asString(sta_));
tag_bldr_->deleteArrival(tag);
}
}
@ -1423,8 +1423,8 @@ Search::seedArrival(Vertex *vertex)
// Internal roots isolated by disabled pins are seeded with no clock.
|| (unconstrained_paths_
&& !network_->isTopLevelPort(pin))) {
debugPrint1(debug_, "search", 2, "arrival seed unclked root %s",
network_->pathName(pin));
debugPrint(debug_, "search", 2, "arrival seed unclked root %s",
network_->pathName(pin));
TagGroupBldr tag_bldr(true, this);
tag_bldr.init(vertex);
if (makeUnclkedPaths(vertex, is_reg_clk, &tag_bldr))
@ -1439,8 +1439,8 @@ Search::seedArrival(Vertex *vertex)
}
}
else {
debugPrint1(debug_, "search", 2, "arrival enqueue %s",
network_->pathName(pin));
debugPrint(debug_, "search", 2, "arrival enqueue %s",
network_->pathName(pin));
arrival_iter_->enqueue(vertex);
}
}
@ -1462,8 +1462,8 @@ Search::seedClkArrivals(const Pin *pin,
TagGroupBldr *tag_bldr)
{
for (Clock *clk : *sdc_->findLeafPinClocks(pin)) {
debugPrint2(debug_, "search", 2, "arrival seed clk %s pin %s",
clk->name(), network_->pathName(pin));
debugPrint(debug_, "search", 2, "arrival seed clk %s pin %s",
clk->name(), network_->pathName(pin));
for (PathAnalysisPt *path_ap : corners_->pathAnalysisPts()) {
const MinMax *min_max = path_ap->pathMinMax();
for (RiseFall *rf : RiseFall::range()) {
@ -1737,11 +1737,11 @@ Search::seedInputDelayArrival(const Pin *pin,
bool is_segment_start,
TagGroupBldr *tag_bldr)
{
debugPrint1(debug_, "search", 2,
input_delay
? "arrival seed input arrival %s"
: "arrival seed input %s",
vertex->name(sdc_network_));
debugPrint(debug_, "search", 2,
input_delay
? "arrival seed input arrival %s"
: "arrival seed input %s",
vertex->name(sdc_network_));
ClockEdge *clk_edge = nullptr;
const Pin *ref_pin = nullptr;
if (input_delay) {
@ -1989,8 +1989,8 @@ PathVisitor::visitFanoutPaths(Vertex *from_vertex)
const Pin *to_pin = to_vertex->pin();
if (pred_->searchTo(to_vertex)
&& pred_->searchThru(edge)) {
debugPrint1(sta_->debug(), "search", 3,
" %s", to_vertex->name(sta_->network()));
debugPrint(sta_->debug(), "search", 3,
" %s", to_vertex->name(sta_->network()));
if (!visitEdge(from_pin, from_vertex, edge, to_pin, to_vertex))
break;
}
@ -3071,14 +3071,14 @@ void
Search::findRequireds(Level level)
{
Stats stats(debug_, report_);
debugPrint1(debug_, "search", 1, "find requireds to level %d", level);
debugPrint(debug_, "search", 1, "find requireds to level %d", level);
RequiredVisitor req_visitor(this);
if (!requireds_seeded_)
seedRequireds();
seedInvalidRequireds();
int required_count = required_iter_->visitParallel(level, &req_visitor);
requireds_exist_ = true;
debugPrint1(debug_, "search", 1, "found %d requireds", required_count);
debugPrint(debug_, "search", 1, "found %d requireds", required_count);
stats.report("Find requireds");
}
@ -3102,8 +3102,8 @@ Search::endpoints()
while (vertex_iter.hasNext()) {
Vertex *vertex = vertex_iter.next();
if (isEndpoint(vertex)) {
debugPrint1(debug_, "endpoint", 2, "insert %s",
vertex->name(sdc_network_));
debugPrint(debug_, "endpoint", 2, "insert %s",
vertex->name(sdc_network_));
endpoints_->insert(vertex);
}
}
@ -3111,8 +3111,8 @@ Search::endpoints()
if (invalid_endpoints_) {
for (Vertex *vertex : *invalid_endpoints_) {
if (isEndpoint(vertex)) {
debugPrint1(debug_, "endpoint", 2, "insert %s",
vertex->name(sdc_network_));
debugPrint(debug_, "endpoint", 2, "insert %s",
vertex->name(sdc_network_));
endpoints_->insert(vertex);
}
else {
@ -3132,8 +3132,8 @@ void
Search::endpointInvalid(Vertex *vertex)
{
if (invalid_endpoints_) {
debugPrint1(debug_, "endpoint", 2, "invalid %s",
vertex->name(sdc_network_));
debugPrint(debug_, "endpoint", 2, "invalid %s",
vertex->name(sdc_network_));
invalid_endpoints_->insert(vertex);
}
}
@ -3254,8 +3254,8 @@ FindEndRequiredVisitor::visit(PathEnd *path_end)
void
Search::seedRequired(Vertex *vertex)
{
debugPrint1(debug_, "search", 2, "required seed %s",
vertex->name(sdc_network_));
debugPrint(debug_, "search", 2, "required seed %s",
vertex->name(sdc_network_));
RequiredCmp required_cmp;
FindEndRequiredVisitor seeder(&required_cmp, this);
required_cmp.requiredsInit(vertex, this);
@ -3341,16 +3341,16 @@ RequiredCmp::requiredsSave(Vertex *vertex,
if (prev_reqs) {
Required prev_req = path->required(sta);
if (!delayEqual(prev_req, req)) {
debugPrint2(debug, "search", 3, "required save %s -> %s",
delayAsString(prev_req, sta),
delayAsString(req, sta));
debugPrint(debug, "search", 3, "required save %s -> %s",
delayAsString(prev_req, sta),
delayAsString(req, sta));
path->setRequired(req, sta);
requireds_changed = true;
}
}
else {
debugPrint1(debug, "search", 3, "required save MIA -> %s",
delayAsString(req, sta));
debugPrint(debug, "search", 3, "required save MIA -> %s",
delayAsString(req, sta));
path->setRequired(req, sta);
}
}
@ -3394,8 +3394,8 @@ RequiredVisitor::visit(Vertex *vertex)
{
Search *search = sta_->search();
const Debug *debug = sta_->debug();
debugPrint1(debug, "search", 2, "find required %s",
vertex->name(sta_->network()));
debugPrint(debug, "search", 2, "find required %s",
vertex->name(sta_->network()));
required_cmp_->requiredsInit(vertex, sta_);
vertex->setRequiredsPruned(false);
// Back propagate requireds from fanout.
@ -3431,13 +3431,13 @@ RequiredVisitor::visitFromToPath(const Pin *,
// Don't propagate required times through latch D->Q edges.
if (edge->role() != TimingRole::latchDtoQ()) {
const Debug *debug = sta_->debug();
debugPrint3(debug, "search", 3, " %s -> %s %s",
from_rf->asString(),
to_rf->asString(),
min_max->asString());
debugPrint2(debug, "search", 3, " from tag %2u: %s",
from_tag->index(),
from_tag->asString(sta_));
debugPrint(debug, "search", 3, " %s -> %s %s",
from_rf->asString(),
to_rf->asString(),
min_max->asString());
debugPrint(debug, "search", 3, " from tag %2u: %s",
from_tag->index(),
from_tag->asString(sta_));
int arrival_index;
bool arrival_exists;
from_path->arrivalIndex(arrival_index, arrival_exists);
@ -3448,15 +3448,15 @@ RequiredVisitor::visitFromToPath(const Pin *,
PathVertex to_path(to_vertex, to_tag, sta_);
Required to_required = to_path.required(sta_);
Required from_required = to_required - arc_delay;
debugPrint2(debug, "search", 3, " to tag %2u: %s",
to_tag->index(),
to_tag->asString(sta_));
debugPrint5(debug, "search", 3, " %s - %s = %s %s %s",
delayAsString(to_required, sta_),
delayAsString(arc_delay, sta_),
delayAsString(from_required, sta_),
min_max == MinMax::max() ? "<" : ">",
delayAsString(required_cmp_->required(arrival_index), sta_));
debugPrint(debug, "search", 3, " to tag %2u: %s",
to_tag->index(),
to_tag->asString(sta_));
debugPrint(debug, "search", 3, " %s - %s = %s %s %s",
delayAsString(to_required, sta_),
delayAsString(arc_delay, sta_),
delayAsString(from_required, sta_),
min_max == MinMax::max() ? "<" : ">",
delayAsString(required_cmp_->required(arrival_index), sta_));
required_cmp_->requiredSet(arrival_index, from_required, req_min, sta_);
}
else {
@ -3471,16 +3471,16 @@ RequiredVisitor::visitFromToPath(const Pin *,
if (tagMatchNoCrpr(to_path_tag, to_tag)) {
Required to_required = to_path->required(sta_);
Required from_required = to_required - arc_delay;
debugPrint2(debug, "search", 3, " to tag %2u: %s",
to_path_tag->index(),
to_path_tag->asString(sta_));
debugPrint5(debug, "search", 3, " %s - %s = %s %s %s",
delayAsString(to_required, sta_),
delayAsString(arc_delay, sta_),
delayAsString(from_required, sta_),
min_max == MinMax::max() ? "<" : ">",
delayAsString(required_cmp_->required(arrival_index),
sta_));
debugPrint(debug, "search", 3, " to tag %2u: %s",
to_path_tag->index(),
to_path_tag->asString(sta_));
debugPrint(debug, "search", 3, " %s - %s = %s %s %s",
delayAsString(to_required, sta_),
delayAsString(arc_delay, sta_),
delayAsString(from_required, sta_),
min_max == MinMax::max() ? "<" : ">",
delayAsString(required_cmp_->required(arrival_index),
sta_));
required_cmp_->requiredSet(arrival_index, from_required, req_min, sta_);
break;
}
@ -3669,8 +3669,8 @@ Search::tnsInvalid(Vertex *vertex)
{
if ((tns_exists_ || worst_slacks_)
&& isEndpoint(vertex)) {
debugPrint1(debug_, "tns", 2, "tns invalid %s",
vertex->name(sdc_network_));
debugPrint(debug_, "tns", 2, "tns invalid %s",
vertex->name(sdc_network_));
UniqueLock lock(tns_lock_);
invalid_tns_.insert(vertex);
}
@ -3683,8 +3683,8 @@ Search::updateInvalidTns()
for (Vertex *vertex : invalid_tns_) {
// Network edits can change endpointedness since tnsInvalid was called.
if (isEndpoint(vertex)) {
debugPrint1(debug_, "tns", 2, "update tns %s",
vertex->name(sdc_network_));
debugPrint(debug_, "tns", 2, "update tns %s",
vertex->name(sdc_network_));
SlackSeq slacks(path_ap_count);
wnsSlacks(vertex, slacks);
@ -3732,9 +3732,9 @@ Search::tnsIncr(Vertex *vertex,
PathAPIndex path_ap_index)
{
if (delayLess(slack, 0.0, this)) {
debugPrint2(debug_, "tns", 3, "tns+ %s %s",
delayAsString(slack, this),
vertex->name(sdc_network_));
debugPrint(debug_, "tns", 3, "tns+ %s %s",
delayAsString(slack, this),
vertex->name(sdc_network_));
tns_[path_ap_index] += slack;
if (tns_slacks_[path_ap_index].hasKey(vertex))
report_->critical(263, "tns incr existing vertex");
@ -3751,9 +3751,9 @@ Search::tnsDecr(Vertex *vertex,
tns_slacks_[path_ap_index].findKey(vertex, slack, found);
if (found
&& delayLess(slack, 0.0, this)) {
debugPrint2(debug_, "tns", 3, "tns- %s %s",
delayAsString(slack, this),
vertex->name(sdc_network_));
debugPrint(debug_, "tns", 3, "tns- %s %s",
delayAsString(slack, this),
vertex->name(sdc_network_));
tns_[path_ap_index] -= slack;
tns_slacks_[path_ap_index].erase(vertex);
}
@ -3812,8 +3812,8 @@ Search::wnsTnsPreamble()
// Required times are only needed at endpoints.
if (requireds_seeded_) {
for (Vertex *vertex : invalid_requireds_) {
debugPrint1(debug_, "search", 2, "tns update required %s",
vertex->name(sdc_network_));
debugPrint(debug_, "search", 2, "tns update required %s",
vertex->name(sdc_network_));
if (isEndpoint(vertex)) {
seedRequired(vertex);
// If the endpoint has fanout it's required time

72
search/Sim.cc
View File

@ -755,9 +755,9 @@ Sim::setConstraintConstPins(LogicValueMap *value_map,
LogicValue value;
const Pin *pin;
value_iter.next(pin, value);
debugPrint2(debug_, "sim", 2, "case pin %s = %c",
network_->pathName(pin),
logicValueString(value));
debugPrint(debug_, "sim", 2, "case pin %s = %c",
network_->pathName(pin),
logicValueString(value));
if (network_->isHierarchical(pin)) {
// Set the logic value on pins inside the instance of a hierarchical pin.
bool pin_is_output = network_->direction(pin)->isAnyOutput();
@ -789,13 +789,13 @@ Sim::setConstFuncPins(bool propagate)
if (port) {
FuncExpr *expr = port->function();
if (expr->op() == FuncExpr::op_zero) {
debugPrint1(debug_, "sim", 2, "func pin %s = 0",
network_->pathName(pin));
debugPrint(debug_, "sim", 2, "func pin %s = 0",
network_->pathName(pin));
setPinValue(pin, LogicValue::zero, propagate);
}
else if (expr->op() == FuncExpr::op_one) {
debugPrint1(debug_, "sim", 2, "func pin %s = 1",
network_->pathName(pin));
debugPrint(debug_, "sim", 2, "func pin %s = 1",
network_->pathName(pin));
setPinValue(pin, LogicValue::one, propagate);
}
}
@ -810,9 +810,9 @@ Sim::enqueueConstantPinInputs(bool propagate)
LogicValue value;
Pin *pin;
const_iter->next(pin, value);
debugPrint2(debug_, "sim", 2, "network constant pin %s = %c",
network_->pathName(pin),
logicValueString(value));
debugPrint(debug_, "sim", 2, "network constant pin %s = %c",
network_->pathName(pin),
logicValueString(value));
setPinValue(pin, value, propagate);
}
delete const_iter;
@ -832,8 +832,8 @@ Sim::removePropagatedValue(const Pin *pin)
if (!exists) {
sdc_->logicValue(pin, constraint_value, exists);
if (!exists) {
debugPrint1(debug_, "sim", 2, "pin %s remove prop constant",
network_->pathName(pin));
debugPrint(debug_, "sim", 2, "pin %s remove prop constant",
network_->pathName(pin));
Vertex *vertex, *bidirect_drvr_vertex;
graph_->pinVertices(pin, vertex, bidirect_drvr_vertex);
if (vertex)
@ -864,9 +864,9 @@ Sim::setPinValue(const Pin *pin,
sdc_network_->pathName(pin));
}
else {
debugPrint2(debug_, "sim", 3, "pin %s = %c",
network_->pathName(pin),
logicValueString(value));
debugPrint(debug_, "sim", 3, "pin %s = %c",
network_->pathName(pin),
logicValueString(value));
Vertex *vertex, *bidirect_drvr_vertex;
graph_->pinVertices(pin, vertex, bidirect_drvr_vertex);
// Set vertex constant flags.
@ -903,7 +903,7 @@ Sim::setPinValue(const Pin *pin,
void
Sim::evalInstance(const Instance *inst)
{
debugPrint1(debug_, "sim", 2, "eval %s", network_->pathName(inst));
debugPrint(debug_, "sim", 2, "eval %s", network_->pathName(inst));
InstancePinIterator *pin_iter = network_->pinIterator(inst);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
@ -918,33 +918,33 @@ Sim::evalInstance(const Instance *inst)
if (tri_en_expr) {
if (evalExpr(tri_en_expr, inst) == LogicValue::one) {
value = evalExpr(expr, inst);
debugPrint3(debug_, "sim", 2, " %s tri_en=1 %s = %c",
port->name(),
expr->asString(),
logicValueString(value));
debugPrint(debug_, "sim", 2, " %s tri_en=1 %s = %c",
port->name(),
expr->asString(),
logicValueString(value));
}
}
else {
value = evalExpr(expr, inst);
debugPrint3(debug_, "sim", 2, " %s %s = %c",
port->name(),
expr->asString(),
logicValueString(value));
debugPrint(debug_, "sim", 2, " %s %s = %c",
port->name(),
expr->asString(),
logicValueString(value));
}
}
else if (port->isClockGateOutPin()) {
value = clockGateOutValue(inst);
debugPrint2(debug_, "sim", 2, " %s gated_clk = %c",
port->name(),
logicValueString(value));
debugPrint(debug_, "sim", 2, " %s gated_clk = %c",
port->name(),
logicValueString(value));
}
FuncExpr *tri_en_expr = port->tristateEnable();
if (tri_en_expr == nullptr
|| evalExpr(tri_en_expr, inst) == LogicValue::one) {
debugPrint3(debug_, "sim", 2, " %s %s = %c",
port->name(),
expr ? expr->asString() : "gated_clk",
logicValueString(value));
debugPrint(debug_, "sim", 2, " %s %s = %c",
port->name(),
expr ? expr->asString() : "gated_clk",
logicValueString(value));
if (value != logicValue(pin))
setPinValue(pin, value, true);
}
@ -1093,8 +1093,8 @@ Sim::clearSimValues()
void
Sim::clearInstSimValues(const Instance *inst)
{
debugPrint1(debug_, "sim", 4, "clear %s",
network_->pathName(inst));
debugPrint(debug_, "sim", 4, "clear %s",
network_->pathName(inst));
InstancePinIterator *pin_iter = network_->pinIterator(inst);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
@ -1123,9 +1123,9 @@ void
Sim::annotateVertexEdges(const Instance *inst,
bool annotate)
{
debugPrint2(debug_, "sim", 4, "annotate %s %s",
network_->pathName(inst),
annotate ? "true" : "false");
debugPrint(debug_, "sim", 4, "annotate %s %s",
network_->pathName(inst),
annotate ? "true" : "false");
InstancePinIterator *pin_iter = network_->pinIterator(inst);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();

14
search/Sta.cc
View File

@ -3006,9 +3006,9 @@ Sta::findRequired(Vertex *vertex)
// path pruning on fanout vertices with DFS.
int fanout = 0;
disableFanoutCrprPruning(vertex, fanout);
debugPrint2(debug_, "search", 1, "resurrect pruned required %s fanout %d",
vertex->name(sdc_network_),
fanout);
debugPrint(debug_, "search", 1, "resurrect pruned required %s fanout %d",
vertex->name(sdc_network_),
fanout);
// Find fanout arrivals and requireds with pruning disabled.
search_->findArrivals();
search_->findRequireds(vertex->level());
@ -4613,8 +4613,8 @@ Sta::findFaninPins(Vertex *to,
int inst_level,
int pin_level)
{
debugPrint1(debug_, "fanin", 1, "%s",
to->name(sdc_network_));
debugPrint(debug_, "fanin", 1, "%s",
to->name(sdc_network_));
if (!visited.hasKey(to)) {
visited.insert(to);
Pin *to_pin = to->pin();
@ -4723,8 +4723,8 @@ Sta::findFanoutPins(Vertex *from,
int inst_level,
int pin_level)
{
debugPrint1(debug_, "fanout", 1, "%s",
from->name(sdc_network_));
debugPrint(debug_, "fanout", 1, "%s",
from->name(sdc_network_));
if (!visited.hasKey(from)) {
visited.insert(from);
if (!search_->isEndpoint(from, pred)

4
search/VisitPathEnds.cc
View File

@ -56,8 +56,8 @@ VisitPathEnds::visitPathEnds(Vertex *vertex,
// Ignore slack on bidirect driver vertex. The load vertex gets the slack.
if (!vertex->isBidirectDriver()) {
const Pin *pin = vertex->pin();
debugPrint1(debug_, "search", 2, "find end slack %s",
vertex->name(sdc_network_));
debugPrint(debug_, "search", 2, "find end slack %s",
vertex->name(sdc_network_));
visitor->vertexBegin(vertex);
bool is_constrained = false;
visitClkedPathEnds(pin, vertex, corner, min_max, filtered, visitor,

26
search/VisitPathGroupVertices.cc
View File

@ -247,8 +247,8 @@ PathGroupPathVisitor::visit(Vertex *vertex)
visitFanoutPaths(vertex);
if (vertex_matches_) {
const Debug *debug = sta_->debug();
debugPrint1(debug, "visit_path_group", 1, "visit %s",
vertex->name(sta_->network()));
debugPrint(debug, "visit_path_group", 1, "visit %s",
vertex->name(sta_->network()));
visitor_->visit(vertex);
bkwd_iter_->enqueueAdjacentVertices(vertex);
}
@ -279,11 +279,11 @@ PathGroupPathVisitor::visitFromToPath(const Pin *,
if (!to_path.isNull()) {
if (matching_paths->hasKey(&to_path)) {
const Debug *debug = sta_->debug();
debugPrint4(debug, "visit_path_group", 2, "match %s %s -> %s %s",
from_vertex->name(sta_->network()),
from_tag->asString(sta_),
to_vertex->name(sta_->network()),
to_tag->asString(sta_));
debugPrint(debug, "visit_path_group", 2, "match %s %s -> %s %s",
from_vertex->name(sta_->network()),
from_tag->asString(sta_),
to_vertex->name(sta_->network()),
to_tag->asString(sta_));
fromMatches(from_vertex, from_tag, arrival_index);
}
}
@ -294,12 +294,12 @@ PathGroupPathVisitor::visitFromToPath(const Pin *,
if (tagMatchNoCrpr(to_path->tag(sta_), to_tag)
&& matching_paths->hasKey(to_path)) {
const Debug *debug = sta_->debug();
debugPrint4(debug, "visit_path_group", 2,
"match crpr %s %s -> %s %s",
from_vertex->name(sta_->network()),
from_tag->asString(sta_),
to_vertex->name(sta_->network()),
to_tag->asString(sta_));
debugPrint(debug, "visit_path_group", 2,
"match crpr %s %s -> %s %s",
from_vertex->name(sta_->network()),
from_tag->asString(sta_),
to_vertex->name(sta_->network()),
to_tag->asString(sta_));
fromMatches(from_vertex, from_tag, arrival_index);
}
}

32
search/WorstSlack.cc
View File

@ -149,7 +149,7 @@ WorstSlack::initQueue(PathAPIndex path_ap_index,
{
Search *search = sta->search();
const Debug *debug = sta->debug();
debugPrint0(debug, "wns", 3, "init queue");
debugPrint(debug, "wns", 3, "init queue");
queue_.clear();
worst_vertex_ = nullptr;
@ -169,8 +169,8 @@ WorstSlack::initQueue(PathAPIndex path_ap_index,
sortQueue(path_ap_index, sta);
}
}
debugPrint1(debug, "wns", 3, "threshold %s",
delayAsString(slack_threshold_, sta));
debugPrint(debug, "wns", 3, "threshold %s",
delayAsString(slack_threshold_, sta));
// checkQueue();
}
@ -181,7 +181,7 @@ WorstSlack::sortQueue(PathAPIndex path_ap_index,
if (queue_.size() > 0) {
Search *search = sta->search();
const Debug *debug = sta->debug();
debugPrint0(debug, "wns", 3, "sort queue");
debugPrint(debug, "wns", 3, "sort queue");
VertexSeq vertices;
vertices.reserve(queue_.size());
@ -197,8 +197,8 @@ WorstSlack::sortQueue(PathAPIndex path_ap_index,
int threshold_index = min(min_queue_size_, vertex_count - 1);
Vertex *threshold_vertex = vertices[threshold_index];
slack_threshold_ = search->wnsSlack(threshold_vertex, path_ap_index);
debugPrint1(debug, "wns", 3, "threshold %s",
delayAsString(slack_threshold_, sta));
debugPrint(debug, "wns", 3, "threshold %s",
delayAsString(slack_threshold_, sta));
// Reinsert vertices with slack < threshold.
queue_.clear();
@ -223,7 +223,7 @@ WorstSlack::findWorstInQueue(PathAPIndex path_ap_index,
{
Search *search = sta->search();
const Debug *debug = sta->debug();
debugPrint0(debug, "wns", 3, "find worst in queue");
debugPrint(debug, "wns", 3, "find worst in queue");
worst_vertex_ = nullptr;
worst_slack_ = slack_init_;
@ -302,15 +302,15 @@ WorstSlack::updateWorstSlack(Vertex *vertex,
if (!delayEqual(slack, slack_init_)
&& delayLessEqual(slack, slack_threshold_, sta)) {
debugPrint2(debug, "wns", 3, "insert %s %s",
vertex->name(network),
delayAsString(slack, sta));
debugPrint(debug, "wns", 3, "insert %s %s",
vertex->name(network),
delayAsString(slack, sta));
queue_.insert(vertex);
}
else {
debugPrint2(debug, "wns", 3, "delete %s %s",
vertex->name(network),
delayAsString(slack, sta));
debugPrint(debug, "wns", 3, "delete %s %s",
vertex->name(network),
delayAsString(slack, sta));
queue_.erase(vertex);
}
// checkQueue();
@ -321,9 +321,9 @@ WorstSlack::setWorstSlack(Vertex *vertex,
Slack slack,
const StaState *sta)
{
debugPrint2(sta->debug(), "wns", 3, "%s %s",
vertex->name(sta->network()),
delayAsString(slack, sta));
debugPrint(sta->debug(), "wns", 3, "%s %s",
vertex->name(sta->network()),
delayAsString(slack, sta));
worst_vertex_ = vertex;
worst_slack_ = slack;
}

10
search/WritePathSpice.cc
View File

@ -859,13 +859,13 @@ WritePathSpice::writeSubcktInstVoltSrcs(Stage stage,
const char *drvr_port_name = drvr_port->name();
const char *inst_name = network_->pathName(inst);
debugPrint1(debug_, "write_spice", 2, "subckt %s", cell->name());
debugPrint(debug_, "write_spice", 2, "subckt %s", cell->name());
for (string subckt_port_sname : *spice_port_names) {
const char *subckt_port_name = subckt_port_sname.c_str();
LibertyPgPort *pg_port = cell->findPgPort(subckt_port_name);
debugPrint2(debug_, "write_spice", 2, " port %s%s",
subckt_port_name,
pg_port ? " pwr/gnd" : "");
debugPrint(debug_, "write_spice", 2, " port %s%s",
subckt_port_name,
pg_port ? " pwr/gnd" : "");
if (pg_port)
writeVoltageSource(inst_name, subckt_port_name,
pgPortVoltage(pg_port), volt_index);
@ -1404,7 +1404,7 @@ WritePathSpice::findPathCellnames(// Return values.
if (arc) {
LibertyCell *cell = arc->set()->libertyCell();
if (cell) {
debugPrint1(debug_, "write_spice", 2, "cell %s", cell->name());
debugPrint(debug_, "write_spice", 2, "cell %s", cell->name());
path_cell_names.insert(cell->name());
}
// Include side receivers.

3
util/ReportTcl.cc
View File

@ -237,7 +237,8 @@ ReportTcl::redirectStringEnd()
static int
encapOutputProc(ClientData instanceData,
CONST84 char *buf,
int toWrite, int *)
int toWrite,
int *)
{
ReportTcl *report = reinterpret_cast<ReportTcl *>(instanceData);
return report->printString(buf, toWrite);