luke
/
OpenSTA
mirror of https://github.com/The-OpenROAD-Project/OpenSTA.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

TransRiseFall -> RiseFall

This commit is contained in:
James Cherry 2019-11-11 15:30:19 -07:00
parent bdab2acb09
commit cc1bd6b5ab
129 changed files with 3258 additions and 3251 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
dcalc/ArcDelayCalc.hh
View File

@ -53,14 +53,14 @@ public:
// Find the parasitic for drvr_pin that is acceptable to the delay
// calculator by probing parasitics_.
virtual Parasitic *findParasitic(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap) = 0;
// Find the wire delays and slews for an input port without a driving cell.
// This call primarily initializes the load delay/slew iterator.
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap) = 0;

28
dcalc/ArnoldiDelayCalc.cc
View File

@ -114,7 +114,7 @@ public:
virtual ~ArnoldiDelayCalc();
virtual ArcDelayCalc *copy();
virtual Parasitic *findParasitic(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap);
virtual void gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
@ -134,7 +134,7 @@ public:
Slew &load_slew);
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void reportGateDelay(const LibertyCell *drvr_cell,
@ -260,7 +260,7 @@ ArnoldiDelayCalc::~ArnoldiDelayCalc()
Parasitic *
ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin,
const TransRiseFall *drvr_tr,
const RiseFall *drvr_rf,
const DcalcAnalysisPt *dcalc_ap)
{
// set_load has precidence over parasitics.
@ -278,7 +278,7 @@ ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin,
if (wireload) {
float pin_cap, wire_cap, fanout;
bool has_wire_cap;
graph_delay_calc_->netCaps(drvr_pin, drvr_tr, dcalc_ap,
graph_delay_calc_->netCaps(drvr_pin, drvr_rf, dcalc_ap,
pin_cap, wire_cap, fanout, has_wire_cap);
parasitic_network = parasitics_->makeWireloadNetwork(drvr_pin, wireload,
fanout, op_cond,
@ -292,7 +292,7 @@ ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin,
reduce_->reduceToArnoldi(parasitic_network,
drvr_pin,
parasitic_ap->couplingCapFactor(),
drvr_tr, op_cond, corner,
drvr_rf, op_cond, corner,
cnst_min_max, parasitic_ap);
if (delete_parasitic_network) {
Net *net = network_->net(drvr_pin);
@ -308,11 +308,11 @@ ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin,
void
ArnoldiDelayCalc::inputPortDelay(const Pin *drvr_pin,
float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap)
{
RCDelayCalc::inputPortDelay(drvr_pin, in_slew, tr, parasitic, dcalc_ap);
RCDelayCalc::inputPortDelay(drvr_pin, in_slew, rf, parasitic, dcalc_ap);
rcmodel_ = nullptr;
_delayV[0] = 0.0;
_slewV[0] = in_slew;
@ -332,9 +332,9 @@ ArnoldiDelayCalc::inputPortDelay(const Pin *drvr_pin,
pin_n_ = rcmodel_->n;
double slew_derate = drvr_library_->slewDerateFromLibrary();
double lo_thresh = drvr_library_->slewLowerThreshold(drvr_tr_);
double hi_thresh = drvr_library_->slewUpperThreshold(drvr_tr_);
bool rising = (drvr_tr_ == TransRiseFall::rise());
double lo_thresh = drvr_library_->slewLowerThreshold(drvr_rf_);
double hi_thresh = drvr_library_->slewUpperThreshold(drvr_rf_);
bool rising = (drvr_rf_ == RiseFall::rise());
delay_work_set_thresholds(delay_work_, lo_thresh, hi_thresh, rising,
slew_derate);
delay_c *c = delay_work_->c;
@ -362,7 +362,7 @@ ArnoldiDelayCalc::gateDelay(const LibertyCell *drvr_cell,
Slew &drvr_slew)
{
input_port_ = false;
drvr_tr_ = arc->toTrans()->asRiseFall();
drvr_rf_ = arc->toTrans()->asRiseFall();
drvr_library_ = drvr_cell->libertyLibrary();
drvr_parasitic_ = drvr_parasitic;
ConcreteParasitic *drvr_cparasitic =
@ -403,9 +403,9 @@ ArnoldiDelayCalc::gateDelaySlew(const LibertyCell *drvr_cell,
pin_n_ = rcmodel_->n;
if (table_model) {
double slew_derate = drvr_library_->slewDerateFromLibrary();
double lo_thresh = drvr_library_->slewLowerThreshold(drvr_tr_);
double hi_thresh = drvr_library_->slewUpperThreshold(drvr_tr_);
bool rising = (drvr_tr_ == TransRiseFall::rise());
double lo_thresh = drvr_library_->slewLowerThreshold(drvr_rf_);
double hi_thresh = drvr_library_->slewUpperThreshold(drvr_rf_);
bool rising = (drvr_rf_ == RiseFall::rise());
delay_work_set_thresholds(delay_work_, lo_thresh, hi_thresh, rising,
slew_derate);
if (rcmodel_->order > 0) {

8
dcalc/ArnoldiReduce.cc
View File

@ -139,7 +139,7 @@ Parasitic *
ArnoldiReduce::reduceToArnoldi(Parasitic *parasitic,
const Pin *drvr_pin,
float coupling_cap_factor,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *cnst_min_max,
@ -148,7 +148,7 @@ ArnoldiReduce::reduceToArnoldi(Parasitic *parasitic,
parasitic_network_ = reinterpret_cast<ConcreteParasiticNetwork*>(parasitic);
drvr_pin_ = drvr_pin;
coupling_cap_factor_ = coupling_cap_factor;
tr_ = tr;
rf_ = rf;
op_cond_ = op_cond;
corner_ = corner;
cnst_min_max_ = cnst_min_max;
@ -449,9 +449,9 @@ ArnoldiReduce::pinCapacitance(ParasiticNode *node)
Port *port = network_->port(pin);
LibertyPort *lib_port = network_->libertyPort(port);
if (lib_port)
pin_cap = sdc_->pinCapacitance(pin,tr_, op_cond_, corner_, cnst_min_max_);
pin_cap = sdc_->pinCapacitance(pin,rf_, op_cond_, corner_, cnst_min_max_);
else if (network_->isTopLevelPort(pin))
pin_cap = sdc_->portExtCap(port, tr_, cnst_min_max_);
pin_cap = sdc_->portExtCap(port, rf_, cnst_min_max_);
}
return pin_cap;
}

4
dcalc/ArnoldiReduce.hh
View File

@ -44,7 +44,7 @@ public:
Parasitic *reduceToArnoldi(Parasitic *parasitic,
const Pin *drvr_pin,
float coupling_cap_factor,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *cnst_min_max,
@ -66,7 +66,7 @@ protected:
ConcreteParasiticNetwork *parasitic_network_;
const Pin *drvr_pin_;
float coupling_cap_factor_;
const TransRiseFall *tr_;
const RiseFall *rf_;
const OperatingConditions *op_cond_;
const Corner *corner_;
const MinMax *cnst_min_max_;

6
dcalc/DelayCalc.tcl
View File

@ -91,10 +91,10 @@ proc report_edge_dcalc { edge corner min_max digits } {
while {[$arc_iter has_next]} {
set arc [$arc_iter next]
set from [get_name [$from_pin port]]
set from_tr [$arc from_trans]
set from_rf [$arc from_trans]
set to [get_name [$to_pin port]]
set to_tr [$arc to_trans]
puts "$from $from_tr -> $to $to_tr"
set to_rf [$arc to_trans]
puts "$from $from_rf -> $to $to_rf"
puts -nonewline [report_delay_calc_cmd $edge $arc $corner $min_max $digits]
if { [$edge delay_annotated $arc $corner $min_max] } {
set delay [$edge arc_delay $arc $corner $min_max]

38
dcalc/DmpCeff.cc
View File

@ -135,7 +135,7 @@ public:
const LibertyCell *drvr_cell,
const Pvt *pvt,
const GateTableModel *gate_model,
const TransRiseFall *tr,
const RiseFall *rf,
double rd,
double in_slew,
float related_out_cap,
@ -166,7 +166,7 @@ protected:
const LibertyCell *drvr_cell,
const Pvt *pvt,
const GateTableModel *gate_model,
const TransRiseFall *tr,
const RiseFall *rf,
double rd,
double in_slew,
float related_out_cap);
@ -302,7 +302,7 @@ DmpAlg::init(const LibertyLibrary *drvr_library,
const LibertyCell *drvr_cell,
const Pvt *pvt,
const GateTableModel *gate_model,
const TransRiseFall *tr,
const RiseFall *rf,
double rd,
double in_slew,
float related_out_cap)
@ -315,9 +315,9 @@ DmpAlg::init(const LibertyLibrary *drvr_library,
in_slew_ = in_slew;
related_out_cap_ = related_out_cap;
driver_valid_ = false;
vth_ = drvr_library->outputThreshold(tr);
vl_ = drvr_library->slewLowerThreshold(tr);
vh_ = drvr_library->slewUpperThreshold(tr);
vth_ = drvr_library->outputThreshold(rf);
vl_ = drvr_library->slewLowerThreshold(rf);
vh_ = drvr_library->slewUpperThreshold(rf);
slew_derate_ = drvr_library->slewDerateFromLibrary();
}
@ -698,7 +698,7 @@ public:
const LibertyCell *drvr_cell,
const Pvt *pvt,
const GateTableModel *gate_model,
const TransRiseFall *tr,
const RiseFall *rf,
double rd,
double in_slew,
float related_out_cap,
@ -731,7 +731,7 @@ DmpCap::init(const LibertyLibrary *drvr_library,
const LibertyCell *drvr_cell,
const Pvt *pvt,
const GateTableModel *gate_model,
const TransRiseFall *tr,
const RiseFall *rf,
double rd,
double in_slew,
float related_out_cap,
@ -740,7 +740,7 @@ DmpCap::init(const LibertyLibrary *drvr_library,
double c1)
{
debugPrint0(debug_, "delay_calc", 3, "Using DMP cap\n");
DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, tr,
DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, rf,
rd, in_slew, related_out_cap);
ceff_ = c1 + c2;
}
@ -813,7 +813,7 @@ public:
const LibertyCell *drvr_cell,
const Pvt *pvt,
const GateTableModel *gate_model,
const TransRiseFall *tr,
const RiseFall *rf,
double rd,
double in_slew,
float related_out_cap,
@ -880,7 +880,7 @@ DmpPi::init(const LibertyLibrary *drvr_library,
const LibertyCell *drvr_cell,
const Pvt *pvt,
const GateTableModel *gate_model,
const TransRiseFall *tr,
const RiseFall *rf,
double rd,
double in_slew,
float related_out_cap,
@ -889,7 +889,7 @@ DmpPi::init(const LibertyLibrary *drvr_library,
double c1)
{
debugPrint0(debug_, "delay_calc", 3, "Using DMP Pi\n");
DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, tr, rd,
DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, rf, rd,
in_slew, related_out_cap);
c1_ = c1;
c2_ = c2;
@ -1143,7 +1143,7 @@ public:
const LibertyCell *drvr_cell,
const Pvt *pvt,
const GateTableModel *gate_model,
const TransRiseFall *tr,
const RiseFall *rf,
double rd,
double in_slew,
float related_out_cap,
@ -1190,7 +1190,7 @@ DmpZeroC2::init(const LibertyLibrary *drvr_library,
const LibertyCell *drvr_cell,
const Pvt *pvt,
const GateTableModel *gate_model,
const TransRiseFall *tr,
const RiseFall *rf,
double rd,
double in_slew,
float related_out_cap,
@ -1199,7 +1199,7 @@ DmpZeroC2::init(const LibertyLibrary *drvr_library,
double c1)
{
debugPrint0(debug_, "delay_calc", 3, "Using DMP C2=0\n");
DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, tr, rd,
DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, rf, rd,
in_slew, related_out_cap);
ceff_ = c1_ = c1;
rpi_ = rpi;
@ -1566,13 +1566,13 @@ DmpCeffDelayCalc::~DmpCeffDelayCalc()
void
DmpCeffDelayCalc::inputPortDelay(const Pin *port_pin,
float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap)
{
dmp_alg_ = nullptr;
input_port_ = true;
RCDelayCalc::inputPortDelay(port_pin, in_slew, tr, parasitic, dcalc_ap);
RCDelayCalc::inputPortDelay(port_pin, in_slew, rf, parasitic, dcalc_ap);
}
void
@ -1589,7 +1589,7 @@ DmpCeffDelayCalc::gateDelay(const LibertyCell *drvr_cell,
Slew &drvr_slew)
{
input_port_ = false;
drvr_tr_ = arc->toTrans()->asRiseFall();
drvr_rf_ = arc->toTrans()->asRiseFall();
drvr_library_ = drvr_cell->libertyLibrary();
drvr_parasitic_ = drvr_parasitic;
GateTimingModel *model = gateModel(arc, dcalc_ap);
@ -1649,7 +1649,7 @@ DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library,
// The full monty.
dmp_alg_ = dmp_pi_;
dmp_alg_->init(drvr_library, drvr_cell, pvt, gate_model,
drvr_tr_, rd, in_slew, related_out_cap, c2, rpi, c1);
drvr_rf_, rd, in_slew, related_out_cap, c2, rpi, c1);
debugPrint6(debug_, "delay_calc", 3,
" DMP in_slew = %s c2 = %s rpi = %s c1 = %s Rd = %s (%s alg)\n",
units_->timeUnit()->asString(in_slew),

2
dcalc/DmpCeff.hh
View File

@ -36,7 +36,7 @@ public:
virtual ~DmpCeffDelayCalc();
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void gateDelay(const LibertyCell *drvr_cell,

28
dcalc/DmpDelayCalc.cc
View File

@ -127,11 +127,11 @@ public:
DmpCeffTwoPoleDelayCalc(StaState *sta);
virtual ArcDelayCalc *copy();
virtual Parasitic *findParasitic(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap);
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void gateDelay(const LibertyCell *drvr_cell,
@ -197,7 +197,7 @@ DmpCeffTwoPoleDelayCalc::copy()
Parasitic *
DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap)
{
// set_load has precidence over parasitics.
@ -206,12 +206,12 @@ DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin,
const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
if (parasitics_->haveParasitics()) {
// Prefer PiPoleResidue.
parasitic = parasitics_->findPiPoleResidue(drvr_pin, tr,
parasitic = parasitics_->findPiPoleResidue(drvr_pin, rf,
parasitic_ap);
if (parasitic)
return parasitic;
parasitic = parasitics_->findPiElmore(drvr_pin, tr, parasitic_ap);
parasitic = parasitics_->findPiElmore(drvr_pin, rf, parasitic_ap);
if (parasitic)
return parasitic;
@ -223,7 +223,7 @@ DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin,
dcalc_ap->corner(),
dcalc_ap->constraintMinMax(),
parasitic_ap);
parasitic = parasitics_->findPiPoleResidue(drvr_pin, tr, parasitic_ap);
parasitic = parasitics_->findPiPoleResidue(drvr_pin, rf, parasitic_ap);
reduced_parasitic_drvrs_.push_back(drvr_pin);
return parasitic;
}
@ -234,9 +234,9 @@ DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin,
if (wireload) {
float pin_cap, wire_cap, fanout;
bool has_wire_cap;
graph_delay_calc_->netCaps(drvr_pin, tr, dcalc_ap,
graph_delay_calc_->netCaps(drvr_pin, rf, dcalc_ap,
pin_cap, wire_cap, fanout, has_wire_cap);
parasitic = parasitics_->estimatePiElmore(drvr_pin, tr, wireload,
parasitic = parasitics_->estimatePiElmore(drvr_pin, rf, wireload,
fanout, pin_cap,
dcalc_ap->operatingConditions(),
dcalc_ap->corner(),
@ -254,12 +254,12 @@ DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin,
void
DmpCeffTwoPoleDelayCalc::inputPortDelay(const Pin *port_pin,
float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap)
{
parasitic_is_pole_residue_ = parasitics_->isPiPoleResidue(parasitic);
DmpCeffDelayCalc::inputPortDelay(port_pin, in_slew, tr, parasitic, dcalc_ap);
DmpCeffDelayCalc::inputPortDelay(port_pin, in_slew, rf, parasitic, dcalc_ap);
}
void
@ -277,10 +277,10 @@ DmpCeffTwoPoleDelayCalc::gateDelay(const LibertyCell *drvr_cell,
{
parasitic_is_pole_residue_ = parasitics_->isPiPoleResidue(drvr_parasitic);
const LibertyLibrary *drvr_library = drvr_cell->libertyLibrary();
const TransRiseFall *tr = arc->toTrans()->asRiseFall();
vth_ = drvr_library->outputThreshold(tr);
vl_ = drvr_library->slewLowerThreshold(tr);
vh_ = drvr_library->slewUpperThreshold(tr);
const RiseFall *rf = arc->toTrans()->asRiseFall();
vth_ = drvr_library->outputThreshold(rf);
vl_ = drvr_library->slewLowerThreshold(rf);
vh_ = drvr_library->slewUpperThreshold(rf);
slew_derate_ = drvr_library->slewDerateFromLibrary();
DmpCeffDelayCalc::gateDelay(drvr_cell, arc, in_slew,
load_cap, drvr_parasitic,

10
dcalc/GraphDelayCalc.cc
View File

@ -61,7 +61,7 @@ GraphDelayCalc::incrementalDelayTolerance()
void
GraphDelayCalc::loadCap(const Pin *,
Parasitic *,
const TransRiseFall *,
const RiseFall *,
const DcalcAnalysisPt *,
// Return values.
float &pin_cap,
@ -72,7 +72,7 @@ GraphDelayCalc::loadCap(const Pin *,
float
GraphDelayCalc::loadCap(const Pin *,
const TransRiseFall *,
const RiseFall *,
const DcalcAnalysisPt *) const
{
return 0.0F;
@ -81,7 +81,7 @@ GraphDelayCalc::loadCap(const Pin *,
float
GraphDelayCalc::loadCap(const Pin *,
Parasitic *,
const TransRiseFall *,
const RiseFall *,
const DcalcAnalysisPt *) const
{
return 0.0F;
@ -96,7 +96,7 @@ GraphDelayCalc::loadCap(const Pin *,
void
GraphDelayCalc::netCaps(const Pin *,
const TransRiseFall *,
const RiseFall *,
const DcalcAnalysisPt *,
// Return values.
float &pin_cap,
@ -118,7 +118,7 @@ GraphDelayCalc::ceff(Edge *,
void
GraphDelayCalc::minPulseWidth(const Pin *pin,
const TransRiseFall *hi_low,
const RiseFall *hi_low,
DcalcAPIndex ap_index,
const MinMax *min_max,
// Return values.

10
dcalc/GraphDelayCalc.hh
View File

@ -74,14 +74,14 @@ public:
// wire_cap = annotated net capacitance + port external wire capacitance.
virtual void loadCap(const Pin *drvr_pin,
Parasitic *drvr_parasitic,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap,
// Return values.
float &pin_cap,
float &wire_cap) const;
// Load pin_cap + wire_cap including parasitic.
virtual float loadCap(const Pin *drvr_pin,
const TransRiseFall *to_tr,
const RiseFall *to_rf,
const DcalcAnalysisPt *dcalc_ap) const;
// Load pin_cap + wire_cap including parasitic min/max for rise/fall.
virtual float loadCap(const Pin *drvr_pin,
@ -89,10 +89,10 @@ public:
// Load pin_cap + wire_cap.
virtual float loadCap(const Pin *drvr_pin,
Parasitic *drvr_parasitic,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap) const;
virtual void netCaps(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap,
// Return values.
float &pin_cap,
@ -107,7 +107,7 @@ public:
// Liberty library
// (ignores set_min_pulse_width constraint)
void minPulseWidth(const Pin *pin,
const TransRiseFall *hi_low,
const RiseFall *hi_low,
DcalcAPIndex ap_index,
const MinMax *min_max,
// Return values.

272
dcalc/GraphDelayCalc1.cc
View File

@ -59,14 +59,14 @@ public:
VertexSet *drvrs() { return drvrs_; }
Vertex *dcalcDrvr() const { return dcalc_drvr_; }
void setDcalcDrvr(Vertex *drvr);
void parallelDelaySlew(const TransRiseFall *drvr_tr,
void parallelDelaySlew(const RiseFall *drvr_rf,
const DcalcAnalysisPt *dcalc_ap,
ArcDelayCalc *arc_delay_calc,
GraphDelayCalc1 *dcalc,
// Return values.
ArcDelay &parallel_delay,
Slew &parallel_slew);
void netCaps(const TransRiseFall *tr,
void netCaps(const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap,
// Return values.
float &pin_cap,
@ -83,11 +83,11 @@ private:
// Driver that triggers delay calculation for all the drivers on the net.
Vertex *dcalc_drvr_;
VertexSet *drvrs_;
// [drvr_tr->index][dcalc_ap->index]
// [drvr_rf->index][dcalc_ap->index]
ArcDelay *parallel_delays_;
// [drvr_tr->index][dcalc_ap->index]
// [drvr_rf->index][dcalc_ap->index]
Slew *parallel_slews_;
// [drvr_tr->index][dcalc_ap->index]
// [drvr_rf->index][dcalc_ap->index]
NetCaps *net_caps_;
bool delays_valid_:1;
};
@ -113,7 +113,7 @@ MultiDrvrNet::~MultiDrvrNet()
}
void
MultiDrvrNet::parallelDelaySlew(const TransRiseFall *drvr_tr,
MultiDrvrNet::parallelDelaySlew(const RiseFall *drvr_rf,
const DcalcAnalysisPt *dcalc_ap,
ArcDelayCalc *arc_delay_calc,
GraphDelayCalc1 *dcalc,
@ -126,8 +126,8 @@ MultiDrvrNet::parallelDelaySlew(const TransRiseFall *drvr_tr,
delays_valid_ = true;
}
int index = dcalc_ap->index() * TransRiseFall::index_count
+ drvr_tr->index();
int index = dcalc_ap->index() * RiseFall::index_count
+ drvr_rf->index();
parallel_delay = parallel_delays_[index];
parallel_slew = parallel_slews_[index];
}
@ -137,16 +137,16 @@ MultiDrvrNet::findDelaysSlews(ArcDelayCalc *arc_delay_calc,
GraphDelayCalc1 *dcalc)
{
Corners *corners = dcalc->corners();
int count = TransRiseFall::index_count * corners->dcalcAnalysisPtCount();
int count = RiseFall::index_count * corners->dcalcAnalysisPtCount();
parallel_delays_ = new ArcDelay[count];
parallel_slews_ = new Slew[count];
for (auto dcalc_ap : corners->dcalcAnalysisPts()) {
DcalcAPIndex ap_index = dcalc_ap->index();
const Pvt *pvt = dcalc_ap->operatingConditions();
for (auto drvr_tr : TransRiseFall::range()) {
int drvr_tr_index = drvr_tr->index();
int index = ap_index*TransRiseFall::index_count+drvr_tr_index;
dcalc->findMultiDrvrGateDelay(this, drvr_tr, pvt, dcalc_ap,
for (auto drvr_rf : RiseFall::range()) {
int drvr_rf_index = drvr_rf->index();
int index = ap_index*RiseFall::index_count+drvr_rf_index;
dcalc->findMultiDrvrGateDelay(this, drvr_rf, pvt, dcalc_ap,
arc_delay_calc,
parallel_delays_[index],
parallel_slews_[index]);
@ -155,7 +155,7 @@ MultiDrvrNet::findDelaysSlews(ArcDelayCalc *arc_delay_calc,
}
void
MultiDrvrNet::netCaps(const TransRiseFall *drvr_tr,
MultiDrvrNet::netCaps(const RiseFall *drvr_rf,
const DcalcAnalysisPt *dcalc_ap,
// Return values.
float &pin_cap,
@ -163,8 +163,8 @@ MultiDrvrNet::netCaps(const TransRiseFall *drvr_tr,
float &fanout,
bool &has_set_load)
{
int index = dcalc_ap->index() * TransRiseFall::index_count
+ drvr_tr->index();
int index = dcalc_ap->index() * RiseFall::index_count
+ drvr_rf->index();
NetCaps &net_caps = net_caps_[index];
pin_cap = net_caps.pinCap();
wire_cap = net_caps.wireCap();
@ -177,7 +177,7 @@ MultiDrvrNet::findCaps(const GraphDelayCalc1 *dcalc,
const Sdc *sdc)
{
Corners *corners = dcalc->corners();
int count = TransRiseFall::index_count * corners->dcalcAnalysisPtCount();
int count = RiseFall::index_count * corners->dcalcAnalysisPtCount();
net_caps_ = new NetCaps[count];
const Pin *drvr_pin = dcalc_drvr_->pin();
for (auto dcalc_ap : corners->dcalcAnalysisPts()) {
@ -185,14 +185,14 @@ MultiDrvrNet::findCaps(const GraphDelayCalc1 *dcalc,
const Corner *corner = dcalc_ap->corner();
const OperatingConditions *op_cond = dcalc_ap->operatingConditions();
const MinMax *min_max = dcalc_ap->constraintMinMax();
for (auto drvr_tr : TransRiseFall::range()) {
int drvr_tr_index = drvr_tr->index();
int index = ap_index * TransRiseFall::index_count + drvr_tr_index;
for (auto drvr_rf : RiseFall::range()) {
int drvr_rf_index = drvr_rf->index();
int index = ap_index * RiseFall::index_count + drvr_rf_index;
NetCaps &net_caps = net_caps_[index];
float pin_cap, wire_cap, fanout;
bool has_set_load;
// Find pin and external pin/wire capacitance.
sdc->connectedCap(drvr_pin, drvr_tr, op_cond, corner, min_max,
sdc->connectedCap(drvr_pin, drvr_rf, op_cond, corner, min_max,
pin_cap, wire_cap, fanout, has_set_load);
net_caps.init(pin_cap, wire_cap, fanout, has_set_load);
}
@ -602,7 +602,7 @@ GraphDelayCalc1::seedDrvrSlew(Vertex *drvr_vertex,
Port *port = network_->port(drvr_pin);
drive = sdc_->findInputDrive(port);
}
for (auto tr : TransRiseFall::range()) {
for (auto tr : RiseFall::range()) {
for (auto dcalc_ap : corners_->dcalcAnalysisPts()) {
if (drive) {
const MinMax *cnst_min_max = dcalc_ap->constraintMinMax();
@ -630,7 +630,7 @@ GraphDelayCalc1::seedDrvrSlew(Vertex *drvr_vertex,
void
GraphDelayCalc1::seedNoDrvrCellSlew(Vertex *drvr_vertex,
const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
InputDrive *drive,
DcalcAnalysisPt *dcalc_ap,
ArcDelayCalc *arc_delay_calc)
@ -640,7 +640,7 @@ GraphDelayCalc1::seedNoDrvrCellSlew(Vertex *drvr_vertex,
Slew slew = default_slew;
float drive_slew;
bool exists;
drive->slew(tr, cnst_min_max, drive_slew, exists);
drive->slew(rf, cnst_min_max, drive_slew, exists);
if (exists)
slew = drive_slew;
else {
@ -648,31 +648,31 @@ GraphDelayCalc1::seedNoDrvrCellSlew(Vertex *drvr_vertex,
// bidirect instance paths are disabled.
if (sdc_->bidirectDrvrSlewFromLoad(drvr_pin)) {
Vertex *load_vertex = graph_->pinLoadVertex(drvr_pin);
slew = graph_->slew(load_vertex, tr, ap_index);
slew = graph_->slew(load_vertex, rf, ap_index);
}
}
Delay drive_delay = delay_zero;
float drive_res;
drive->driveResistance(tr, cnst_min_max, drive_res, exists);
Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, tr, dcalc_ap);
drive->driveResistance(rf, cnst_min_max, drive_res, exists);
Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, rf, dcalc_ap);
if (exists) {
float cap = loadCap(drvr_pin, parasitic, tr, dcalc_ap);
float cap = loadCap(drvr_pin, parasitic, rf, dcalc_ap);
drive_delay = cap * drive_res;
slew = cap * drive_res;
}
const MinMax *slew_min_max = dcalc_ap->slewMinMax();
if (!drvr_vertex->slewAnnotated(tr, slew_min_max))
graph_->setSlew(drvr_vertex, tr, ap_index, slew);
arc_delay_calc->inputPortDelay(drvr_pin, delayAsFloat(slew), tr,
if (!drvr_vertex->slewAnnotated(rf, slew_min_max))
graph_->setSlew(drvr_vertex, rf, ap_index, slew);
arc_delay_calc->inputPortDelay(drvr_pin, delayAsFloat(slew), rf,
parasitic, dcalc_ap);
annotateLoadDelays(drvr_vertex, tr, drive_delay, false, dcalc_ap,
annotateLoadDelays(drvr_vertex, rf, drive_delay, false, dcalc_ap,
arc_delay_calc);
}
void
GraphDelayCalc1::seedNoDrvrSlew(Vertex *drvr_vertex,
const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAnalysisPt *dcalc_ap,
ArcDelayCalc *arc_delay_calc)
{
@ -683,14 +683,14 @@ GraphDelayCalc1::seedNoDrvrSlew(Vertex *drvr_vertex,
// bidirect instance paths are disabled.
if (sdc_->bidirectDrvrSlewFromLoad(drvr_pin)) {
Vertex *load_vertex = graph_->pinLoadVertex(drvr_pin);
slew = graph_->slew(load_vertex, tr, ap_index);
slew = graph_->slew(load_vertex, rf, ap_index);
}
if (!drvr_vertex->slewAnnotated(tr, slew_min_max))
graph_->setSlew(drvr_vertex, tr, ap_index, slew);
Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, tr, dcalc_ap);
arc_delay_calc->inputPortDelay(drvr_pin, delayAsFloat(slew), tr,
if (!drvr_vertex->slewAnnotated(rf, slew_min_max))
graph_->setSlew(drvr_vertex, rf, ap_index, slew);
Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, rf, dcalc_ap);
arc_delay_calc->inputPortDelay(drvr_pin, delayAsFloat(slew), rf,
parasitic, dcalc_ap);
annotateLoadDelays(drvr_vertex, tr, delay_zero, false, dcalc_ap,
annotateLoadDelays(drvr_vertex, rf, delay_zero, false, dcalc_ap,
arc_delay_calc);
}
@ -702,7 +702,7 @@ GraphDelayCalc1::seedLoadSlew(Vertex *vertex)
vertex->name(sdc_network_));
ClockSet *clks = sdc_->findLeafPinClocks(pin);
initSlew(vertex);
for (auto tr : TransRiseFall::range()) {
for (auto tr : RiseFall::range()) {
for (auto dcalc_ap : corners_->dcalcAnalysisPts()) {
const MinMax *slew_min_max = dcalc_ap->slewMinMax();
if (!vertex->slewAnnotated(tr, slew_min_max)) {
@ -770,7 +770,7 @@ void
GraphDelayCalc1::findInputDriverDelay(LibertyCell *drvr_cell,
const Pin *drvr_pin,
Vertex *drvr_vertex,
const TransRiseFall *tr,
const RiseFall *rf,
LibertyPort *from_port,
float *from_slews,
LibertyPort *to_port,
@ -778,7 +778,7 @@ GraphDelayCalc1::findInputDriverDelay(LibertyCell *drvr_cell,
{
debugPrint2(debug_, "delay_calc", 2, " driver cell %s %s\n",
drvr_cell->name(),
tr->asString());
rf->asString());
LibertyCellTimingArcSetIterator set_iter(drvr_cell);
while (set_iter.hasNext()) {
TimingArcSet *arc_set = set_iter.next();
@ -787,7 +787,7 @@ GraphDelayCalc1::findInputDriverDelay(LibertyCell *drvr_cell,
TimingArcSetArcIterator arc_iter(arc_set);
while (arc_iter.hasNext()) {
TimingArc *arc = arc_iter.next();
if (arc->toTrans()->asRiseFall() == tr) {
if (arc->toTrans()->asRiseFall() == rf) {
float from_slew = from_slews[arc->fromTrans()->index()];
findInputArcDelay(drvr_cell, drvr_pin, drvr_vertex,
arc, from_slew, dcalc_ap);
@ -814,13 +814,13 @@ GraphDelayCalc1::findInputArcDelay(LibertyCell *drvr_cell,
arc->to()->name(),
arc->toTrans()->asString(),
arc->role()->asString());
TransRiseFall *drvr_tr = arc->toTrans()->asRiseFall();
if (drvr_tr) {
RiseFall *drvr_rf = arc->toTrans()->asRiseFall();
if (drvr_rf) {
DcalcAPIndex ap_index = dcalc_ap->index();
const Pvt *pvt = dcalc_ap->operatingConditions();
Parasitic *drvr_parasitic = arc_delay_calc_->findParasitic(drvr_pin, drvr_tr,
Parasitic *drvr_parasitic = arc_delay_calc_->findParasitic(drvr_pin, drvr_rf,
dcalc_ap);
float load_cap = loadCap(drvr_pin, drvr_parasitic, drvr_tr, dcalc_ap);
float load_cap = loadCap(drvr_pin, drvr_parasitic, drvr_rf, dcalc_ap);
ArcDelay intrinsic_delay;
Slew intrinsic_slew;
@ -841,8 +841,8 @@ GraphDelayCalc1::findInputArcDelay(LibertyCell *drvr_cell,
delayAsString(gate_delay, this),
delayAsString(intrinsic_delay, this),
delayAsString(gate_slew, this));
graph_->setSlew(drvr_vertex, drvr_tr, ap_index, gate_slew);
annotateLoadDelays(drvr_vertex, drvr_tr, load_delay, false, dcalc_ap,
graph_->setSlew(drvr_vertex, drvr_rf, ap_index, gate_slew);
annotateLoadDelays(drvr_vertex, drvr_rf, load_delay, false, dcalc_ap,
arc_delay_calc_);
}
}
@ -960,7 +960,7 @@ GraphDelayCalc1::initRootSlews(Vertex *vertex)
for (auto dcalc_ap : corners_->dcalcAnalysisPts()) {
const MinMax *slew_min_max = dcalc_ap->slewMinMax();
DcalcAPIndex ap_index = dcalc_ap->index();
for (auto tr : TransRiseFall::range()) {
for (auto tr : RiseFall::range()) {
if (!vertex->slewAnnotated(tr, slew_min_max))
graph_->setSlew(vertex, tr, ap_index, default_slew);
}
@ -990,16 +990,16 @@ GraphDelayCalc1::findDriverEdgeDelays(LibertyCell *drvr_cell,
TimingArcSetArcIterator arc_iter(arc_set);
while (arc_iter.hasNext()) {
TimingArc *arc = arc_iter.next();
const TransRiseFall *tr = arc->toTrans()->asRiseFall();
Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, tr,
const RiseFall *rf = arc->toTrans()->asRiseFall();
Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, rf,
dcalc_ap);
float related_out_cap = 0.0;
if (related_out_pin) {
Parasitic *related_out_parasitic =
arc_delay_calc->findParasitic(related_out_pin, tr, dcalc_ap);
arc_delay_calc->findParasitic(related_out_pin, rf, dcalc_ap);
related_out_cap = loadCap(related_out_pin,
related_out_parasitic,
tr, dcalc_ap);
rf, dcalc_ap);
}
delay_changed |= findArcDelay(drvr_cell, drvr_pin, drvr_vertex,
multi_drvr, arc, parasitic,
@ -1022,10 +1022,10 @@ GraphDelayCalc1::loadCap(const Pin *drvr_pin,
{
const MinMax *min_max = dcalc_ap->constraintMinMax();
float load_cap = 0.0;
for (auto drvr_tr : TransRiseFall::range()) {
Parasitic *drvr_parasitic = arc_delay_calc_->findParasitic(drvr_pin, drvr_tr,
for (auto drvr_rf : RiseFall::range()) {
Parasitic *drvr_parasitic = arc_delay_calc_->findParasitic(drvr_pin, drvr_rf,
dcalc_ap);
float cap = loadCap(drvr_pin, nullptr, drvr_parasitic, drvr_tr, dcalc_ap);
float cap = loadCap(drvr_pin, nullptr, drvr_parasitic, drvr_rf, dcalc_ap);
if (min_max->compare(cap, load_cap))
load_cap = cap;
}
@ -1034,39 +1034,39 @@ GraphDelayCalc1::loadCap(const Pin *drvr_pin,
float
GraphDelayCalc1::loadCap(const Pin *drvr_pin,
const TransRiseFall *drvr_tr,
const RiseFall *drvr_rf,
const DcalcAnalysisPt *dcalc_ap) const
{
Parasitic *drvr_parasitic = arc_delay_calc_->findParasitic(drvr_pin, drvr_tr,
Parasitic *drvr_parasitic = arc_delay_calc_->findParasitic(drvr_pin, drvr_rf,
dcalc_ap);
float cap = loadCap(drvr_pin, nullptr, drvr_parasitic, drvr_tr, dcalc_ap);
float cap = loadCap(drvr_pin, nullptr, drvr_parasitic, drvr_rf, dcalc_ap);
return cap;
}
float
GraphDelayCalc1::loadCap(const Pin *drvr_pin,
Parasitic *drvr_parasitic,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap) const
{
return loadCap(drvr_pin, nullptr, drvr_parasitic, tr, dcalc_ap);
return loadCap(drvr_pin, nullptr, drvr_parasitic, rf, dcalc_ap);
}
float
GraphDelayCalc1::loadCap(const Pin *drvr_pin,
MultiDrvrNet *multi_drvr,
Parasitic *drvr_parasitic,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap) const
{
float pin_cap, wire_cap;
bool has_set_load;
float fanout;
if (multi_drvr)
multi_drvr->netCaps(tr, dcalc_ap,
multi_drvr->netCaps(rf, dcalc_ap,
pin_cap, wire_cap, fanout, has_set_load);
else
netCaps(drvr_pin, tr, dcalc_ap,
netCaps(drvr_pin, rf, dcalc_ap,
pin_cap, wire_cap, fanout, has_set_load);
loadCap(drvr_parasitic, has_set_load, pin_cap, wire_cap);
return wire_cap + pin_cap;
@ -1075,7 +1075,7 @@ GraphDelayCalc1::loadCap(const Pin *drvr_pin,
void
GraphDelayCalc1::loadCap(const Pin *drvr_pin,
Parasitic *drvr_parasitic,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap,
// Return values.
float &pin_cap,
@ -1084,7 +1084,7 @@ GraphDelayCalc1::loadCap(const Pin *drvr_pin,
bool has_set_load;
float fanout;
// Find pin and external pin/wire capacitance.
netCaps(drvr_pin, tr, dcalc_ap,
netCaps(drvr_pin, rf, dcalc_ap,
pin_cap, wire_cap, fanout, has_set_load);
loadCap(drvr_parasitic, has_set_load, pin_cap, wire_cap);
}
@ -1115,7 +1115,7 @@ GraphDelayCalc1::loadCap(Parasitic *drvr_parasitic,
void
GraphDelayCalc1::netCaps(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap,
// Return values.
float &pin_cap,
@ -1129,14 +1129,14 @@ GraphDelayCalc1::netCaps(const Pin *drvr_pin,
multi_drvr = multiDrvrNet(drvr_vertex);
}
if (multi_drvr)
multi_drvr->netCaps(tr, dcalc_ap,
multi_drvr->netCaps(rf, dcalc_ap,
pin_cap, wire_cap, fanout, has_set_load);
else {
const OperatingConditions *op_cond = dcalc_ap->operatingConditions();
const Corner *corner = dcalc_ap->corner();
const MinMax *min_max = dcalc_ap->constraintMinMax();
// Find pin and external pin/wire capacitance.
sdc_->connectedCap(drvr_pin, tr, op_cond, corner, min_max,
sdc_->connectedCap(drvr_pin, rf, op_cond, corner, min_max,
pin_cap, wire_cap, fanout, has_set_load);
}
}
@ -1144,7 +1144,7 @@ GraphDelayCalc1::netCaps(const Pin *drvr_pin,
void
GraphDelayCalc1::initSlew(Vertex *vertex)
{
for (auto tr : TransRiseFall::range()) {
for (auto tr : RiseFall::range()) {
for (auto dcalc_ap : corners_->dcalcAnalysisPts()) {
const MinMax *slew_min_max = dcalc_ap->slewMinMax();
if (!vertex->slewAnnotated(tr, slew_min_max)) {
@ -1171,7 +1171,7 @@ GraphDelayCalc1::initWireDelays(Vertex *drvr_vertex,
Delay delay_init_value(delay_min_max->initValue());
Slew slew_init_value(slew_min_max->initValue());
DcalcAPIndex ap_index = dcalc_ap->index();
for (auto tr : TransRiseFall::range()) {
for (auto tr : RiseFall::range()) {
if (!graph_->wireDelayAnnotated(wire_edge, tr, ap_index))
graph_->setWireArcDelay(wire_edge, tr, ap_index, delay_init_value);
// Init load vertex slew.
@ -1203,9 +1203,9 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell,
ArcDelayCalc *arc_delay_calc)
{
bool delay_changed = false;
TransRiseFall *from_tr = arc->fromTrans()->asRiseFall();
TransRiseFall *drvr_tr = arc->toTrans()->asRiseFall();
if (from_tr && drvr_tr) {
RiseFall *from_rf = arc->fromTrans()->asRiseFall();
RiseFall *drvr_rf = arc->toTrans()->asRiseFall();
if (from_rf && drvr_rf) {
DcalcAPIndex ap_index = dcalc_ap->index();
debugPrint6(debug_, "delay_calc", 3,
" %s %s -> %s %s (%s) %s\n",
@ -1217,7 +1217,7 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell,
dcalc_ap->corner()->name());
// Delay calculation is done even when the gate delays/slews are
// annotated because the wire delays may not be annotated.
const Slew from_slew = edgeFromSlew(from_vertex, from_tr, edge, dcalc_ap);
const Slew from_slew = edgeFromSlew(from_vertex, from_rf, edge, dcalc_ap);
ArcDelay gate_delay;
Slew gate_slew;
if (multi_drvr
@ -1229,7 +1229,7 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell,
gate_delay, gate_slew);
else {
float load_cap = loadCap(drvr_pin, multi_drvr, drvr_parasitic,
drvr_tr, dcalc_ap);
drvr_rf, dcalc_ap);
arc_delay_calc->gateDelay(drvr_cell, arc,
from_slew, load_cap, drvr_parasitic,
related_out_cap, pvt, dcalc_ap,
@ -1240,11 +1240,11 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell,
delayAsString(gate_delay, this),
delayAsString(gate_slew, this));
// Merge slews.
const Slew &drvr_slew = graph_->slew(drvr_vertex, drvr_tr, ap_index);
const Slew &drvr_slew = graph_->slew(drvr_vertex, drvr_rf, ap_index);
const MinMax *slew_min_max = dcalc_ap->slewMinMax();
if (fuzzyGreater(gate_slew, drvr_slew, dcalc_ap->slewMinMax())
&& !drvr_vertex->slewAnnotated(drvr_tr, slew_min_max))
graph_->setSlew(drvr_vertex, drvr_tr, ap_index, gate_slew);
&& !drvr_vertex->slewAnnotated(drvr_rf, slew_min_max))
graph_->setSlew(drvr_vertex, drvr_rf, ap_index, gate_slew);
if (!graph_->arcDelayAnnotated(edge, arc, ap_index)) {
const ArcDelay &prev_gate_delay = graph_->arcDelay(edge,arc,ap_index);
float gate_delay1 = delayAsFloat(gate_delay);
@ -1255,7 +1255,7 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell,
delay_changed = true;
graph_->setArcDelay(edge, arc, ap_index, gate_delay);
}
annotateLoadDelays(drvr_vertex, drvr_tr, delay_zero, true, dcalc_ap,
annotateLoadDelays(drvr_vertex, drvr_rf, delay_zero, true, dcalc_ap,
arc_delay_calc);
}
return delay_changed;
@ -1283,15 +1283,15 @@ GraphDelayCalc1::multiDrvrGateDelay(MultiDrvrNet *multi_drvr,
intrinsic_delay, intrinsic_slew);
ArcDelay parallel_delay;
Slew parallel_slew;
const TransRiseFall *drvr_tr = arc->toTrans()->asRiseFall();
multi_drvr->parallelDelaySlew(drvr_tr, dcalc_ap, arc_delay_calc, this,
const RiseFall *drvr_rf = arc->toTrans()->asRiseFall();
multi_drvr->parallelDelaySlew(drvr_rf, dcalc_ap, arc_delay_calc, this,
parallel_delay, parallel_slew);
gate_delay = parallel_delay + intrinsic_delay;
gate_slew = parallel_slew;
float load_cap = loadCap(drvr_pin, multi_drvr, drvr_parasitic,
drvr_tr, dcalc_ap);
drvr_rf, dcalc_ap);
Delay gate_delay1;
Slew gate_slew1;
arc_delay_calc->gateDelay(drvr_cell, arc,
@ -1304,7 +1304,7 @@ GraphDelayCalc1::multiDrvrGateDelay(MultiDrvrNet *multi_drvr,
void
GraphDelayCalc1::findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr,
const TransRiseFall *drvr_tr,
const RiseFall *drvr_rf,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
ArcDelayCalc *arc_delay_calc,
@ -1329,18 +1329,18 @@ GraphDelayCalc1::findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr,
TimingArcSetArcIterator arc_iter(arc_set1);
while (arc_iter.hasNext()) {
TimingArc *arc1 = arc_iter.next();
TransRiseFall *drvr_tr1 = arc1->toTrans()->asRiseFall();
if (drvr_tr1 == drvr_tr) {
RiseFall *drvr_rf1 = arc1->toTrans()->asRiseFall();
if (drvr_rf1 == drvr_rf) {
Vertex *from_vertex1 = edge1->from(graph_);
TransRiseFall *from_tr1 = arc1->fromTrans()->asRiseFall();
Slew from_slew1 = edgeFromSlew(from_vertex1, from_tr1, edge1, dcalc_ap);
RiseFall *from_rf1 = arc1->fromTrans()->asRiseFall();
Slew from_slew1 = edgeFromSlew(from_vertex1, from_rf1, edge1, dcalc_ap);
ArcDelay intrinsic_delay1;
Slew intrinsic_slew1;
arc_delay_calc->gateDelay(drvr_cell1, arc1, from_slew1,
0.0, 0, 0.0, pvt, dcalc_ap,
intrinsic_delay1, intrinsic_slew1);
Parasitic *parasitic1 =
arc_delay_calc->findParasitic(drvr_pin1, drvr_tr1, dcalc_ap);
arc_delay_calc->findParasitic(drvr_pin1, drvr_rf1, dcalc_ap);
const Pin *related_out_pin1 = 0;
float related_out_cap1 = 0.0;
if (related_out_port) {
@ -1348,15 +1348,15 @@ GraphDelayCalc1::findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr,
related_out_pin1 = network_->findPin(inst1, related_out_port);
if (related_out_pin1) {
Parasitic *related_out_parasitic1 =
arc_delay_calc->findParasitic(related_out_pin1, drvr_tr,
arc_delay_calc->findParasitic(related_out_pin1, drvr_rf,
dcalc_ap);
related_out_cap1 = loadCap(related_out_pin1,
related_out_parasitic1,
drvr_tr, dcalc_ap);
drvr_rf, dcalc_ap);
}
}
float load_cap1 = loadCap(drvr_pin1, parasitic1,
drvr_tr, dcalc_ap);
drvr_rf, dcalc_ap);
ArcDelay gate_delay1;
Slew gate_slew1;
arc_delay_calc->gateDelay(drvr_cell1, arc1,
@ -1377,21 +1377,21 @@ GraphDelayCalc1::findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr,
// Use clock slew for register/latch clk->q edges.
Slew
GraphDelayCalc1::edgeFromSlew(const Vertex *from_vertex,
const TransRiseFall *from_tr,
const RiseFall *from_rf,
const Edge *edge,
const DcalcAnalysisPt *dcalc_ap)
{
const TimingRole *role = edge->role();
if (role->genericRole() == TimingRole::regClkToQ()
&& isIdealClk(from_vertex))
return idealClkSlew(from_vertex, from_tr, dcalc_ap->slewMinMax());
return idealClkSlew(from_vertex, from_rf, dcalc_ap->slewMinMax());
else
return graph_->slew(from_vertex, from_tr, dcalc_ap->index());
return graph_->slew(from_vertex, from_rf, dcalc_ap->index());
}
Slew
GraphDelayCalc1::idealClkSlew(const Vertex *vertex,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max)
{
float slew = min_max->initValue();
@ -1399,7 +1399,7 @@ GraphDelayCalc1::idealClkSlew(const Vertex *vertex,
ClockSet::ConstIterator clk_iter(clks);
while (clk_iter.hasNext()) {
Clock *clk = clk_iter.next();
float clk_slew = clk->slew(tr, min_max);
float clk_slew = clk->slew(rf, min_max);
if (min_max->compare(clk_slew, slew))
slew = clk_slew;
}
@ -1411,7 +1411,7 @@ GraphDelayCalc1::idealClkSlew(const Vertex *vertex,
// by the delay calculator.
void
GraphDelayCalc1::annotateLoadDelays(Vertex *drvr_vertex,
const TransRiseFall *drvr_tr,
const RiseFall *drvr_rf,
const ArcDelay &extra_delay,
bool merge,
const DcalcAnalysisPt *dcalc_ap,
@ -1433,30 +1433,30 @@ GraphDelayCalc1::annotateLoadDelays(Vertex *drvr_vertex,
load_vertex->name(sdc_network_),
delayAsString(wire_delay, this),
delayAsString(load_slew, this));
if (!load_vertex->slewAnnotated(drvr_tr, slew_min_max)) {
if (drvr_vertex->slewAnnotated(drvr_tr, slew_min_max)) {
if (!load_vertex->slewAnnotated(drvr_rf, slew_min_max)) {
if (drvr_vertex->slewAnnotated(drvr_rf, slew_min_max)) {
// Copy the driver slew to the load if it is annotated.
const Slew &drvr_slew = graph_->slew(drvr_vertex,drvr_tr,ap_index);
graph_->setSlew(load_vertex, drvr_tr, ap_index, drvr_slew);
const Slew &drvr_slew = graph_->slew(drvr_vertex,drvr_rf,ap_index);
graph_->setSlew(load_vertex, drvr_rf, ap_index, drvr_slew);
}
else {
const Slew &slew = graph_->slew(load_vertex, drvr_tr, ap_index);
const Slew &slew = graph_->slew(load_vertex, drvr_rf, ap_index);
if (!merge
|| fuzzyGreater(load_slew, slew, slew_min_max))
graph_->setSlew(load_vertex, drvr_tr, ap_index, load_slew);
graph_->setSlew(load_vertex, drvr_rf, ap_index, load_slew);
}
}
if (!graph_->wireDelayAnnotated(wire_edge, drvr_tr, ap_index)) {
if (!graph_->wireDelayAnnotated(wire_edge, drvr_rf, ap_index)) {
// Multiple timing arcs with the same output transition
// annotate the same wire edges so they must be combined
// rather than set.
const ArcDelay &delay = graph_->wireArcDelay(wire_edge, drvr_tr,
const ArcDelay &delay = graph_->wireArcDelay(wire_edge, drvr_rf,
ap_index);
Delay wire_delay_extra = extra_delay + wire_delay;
const MinMax *delay_min_max = dcalc_ap->delayMinMax();
if (!merge
|| fuzzyGreater(wire_delay_extra, delay, delay_min_max)) {
graph_->setWireArcDelay(wire_edge, drvr_tr, ap_index,
graph_->setWireArcDelay(wire_edge, drvr_rf, ap_index,
wire_delay_extra);
if (observer_)
observer_->delayChangedTo(load_vertex);
@ -1519,9 +1519,9 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge,
TimingArcSetArcIterator arc_iter(arc_set);
while (arc_iter.hasNext()) {
TimingArc *arc = arc_iter.next();
TransRiseFall *from_tr = arc->fromTrans()->asRiseFall();
TransRiseFall *to_tr = arc->toTrans()->asRiseFall();
if (from_tr && to_tr) {
RiseFall *from_rf = arc->fromTrans()->asRiseFall();
RiseFall *to_rf = arc->toTrans()->asRiseFall();
if (from_rf && to_rf) {
const LibertyPort *related_out_port = arc_set->relatedOut();
const Pin *related_out_pin = 0;
if (related_out_port)
@ -1532,10 +1532,10 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge,
const Pvt *pvt = sdc_->pvt(inst,dcalc_ap->constraintMinMax());
if (pvt == nullptr)
pvt = dcalc_ap->operatingConditions();
const Slew &from_slew = checkEdgeClkSlew(from_vertex, from_tr,
const Slew &from_slew = checkEdgeClkSlew(from_vertex, from_rf,
dcalc_ap);
int slew_index = dcalc_ap->checkDataSlewIndex();
const Slew &to_slew = graph_->slew(to_vertex, to_tr, slew_index);
const Slew &to_slew = graph_->slew(to_vertex, to_rf, slew_index);
debugPrint5(debug_, "delay_calc", 3,
" %s %s -> %s %s (%s)\n",
arc_set->from()->name(),
@ -1550,10 +1550,10 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge,
float related_out_cap = 0.0;
if (related_out_pin) {
Parasitic *related_out_parasitic =
arc_delay_calc->findParasitic(related_out_pin, to_tr, dcalc_ap);
arc_delay_calc->findParasitic(related_out_pin, to_rf, dcalc_ap);
related_out_cap = loadCap(related_out_pin,
related_out_parasitic,
to_tr, dcalc_ap);
to_rf, dcalc_ap);
}
ArcDelay check_delay;
arc_delay_calc->checkDelay(cell, arc,
@ -1578,13 +1578,13 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge,
// Use clock slew for timing check clock edges.
Slew
GraphDelayCalc1::checkEdgeClkSlew(const Vertex *from_vertex,
const TransRiseFall *from_tr,
const RiseFall *from_rf,
const DcalcAnalysisPt *dcalc_ap)
{
if (isIdealClk(from_vertex))
return idealClkSlew(from_vertex, from_tr, dcalc_ap->checkClkSlewMinMax());
return idealClkSlew(from_vertex, from_rf, dcalc_ap->checkClkSlewMinMax());
else
return graph_->slew(from_vertex, from_tr, dcalc_ap->checkClkSlewIndex());
return graph_->slew(from_vertex, from_rf, dcalc_ap->checkClkSlewIndex());
}
////////////////////////////////////////////////////////////////
@ -1696,9 +1696,9 @@ GraphDelayCalc1::ceff(Edge *edge,
const Pvt *pvt = sdc_->pvt(inst, dcalc_ap->constraintMinMax());
if (pvt == nullptr)
pvt = dcalc_ap->operatingConditions();
TransRiseFall *from_tr = arc->fromTrans()->asRiseFall();
TransRiseFall *to_tr = arc->toTrans()->asRiseFall();
if (from_tr && to_tr) {
RiseFall *from_rf = arc->fromTrans()->asRiseFall();
RiseFall *to_rf = arc->toTrans()->asRiseFall();
if (from_rf && to_rf) {
const LibertyPort *related_out_port = arc_set->relatedOut();
const Pin *related_out_pin = 0;
if (related_out_port)
@ -1706,14 +1706,14 @@ GraphDelayCalc1::ceff(Edge *edge,
float related_out_cap = 0.0;
if (related_out_pin) {
Parasitic *related_out_parasitic =
arc_delay_calc_->findParasitic(related_out_pin, to_tr, dcalc_ap);
arc_delay_calc_->findParasitic(related_out_pin, to_rf, dcalc_ap);
related_out_cap = loadCap(related_out_pin, related_out_parasitic,
to_tr, dcalc_ap);
to_rf, dcalc_ap);
}
Parasitic *to_parasitic = arc_delay_calc_->findParasitic(to_pin, to_tr,
Parasitic *to_parasitic = arc_delay_calc_->findParasitic(to_pin, to_rf,
dcalc_ap);
const Slew &from_slew = edgeFromSlew(from_vertex, from_tr, edge, dcalc_ap);
float load_cap = loadCap(to_pin, to_parasitic, to_tr, dcalc_ap);
const Slew &from_slew = edgeFromSlew(from_vertex, from_rf, edge, dcalc_ap);
float load_cap = loadCap(to_pin, to_parasitic, to_rf, dcalc_ap);
ceff = arc_delay_calc_->ceff(cell, arc,
from_slew, load_cap, to_parasitic,
related_out_cap, pvt, dcalc_ap);
@ -1743,9 +1743,9 @@ GraphDelayCalc1::reportDelayCalc(Edge *edge,
const Pvt *pvt = sdc_->pvt(inst, dcalc_ap->constraintMinMax());
if (pvt == nullptr)
pvt = dcalc_ap->operatingConditions();
TransRiseFall *from_tr = arc->fromTrans()->asRiseFall();
TransRiseFall *to_tr = arc->toTrans()->asRiseFall();
if (from_tr && to_tr) {
RiseFall *from_rf = arc->fromTrans()->asRiseFall();
RiseFall *to_rf = arc->toTrans()->asRiseFall();
if (from_rf && to_rf) {
const LibertyPort *related_out_port = arc_set->relatedOut();
const Pin *related_out_pin = 0;
if (related_out_port)
@ -1753,14 +1753,14 @@ GraphDelayCalc1::reportDelayCalc(Edge *edge,
float related_out_cap = 0.0;
if (related_out_pin) {
Parasitic *related_out_parasitic =
arc_delay_calc_->findParasitic(related_out_pin, to_tr, dcalc_ap);
arc_delay_calc_->findParasitic(related_out_pin, to_rf, dcalc_ap);
related_out_cap = loadCap(related_out_pin, related_out_parasitic,
to_tr, dcalc_ap);
to_rf, dcalc_ap);
}
if (role->isTimingCheck()) {
const Slew &from_slew = checkEdgeClkSlew(from_vertex, from_tr, dcalc_ap);
const Slew &from_slew = checkEdgeClkSlew(from_vertex, from_rf, dcalc_ap);
int slew_index = dcalc_ap->checkDataSlewIndex();
const Slew &to_slew = graph_->slew(to_vertex, to_tr, slew_index);
const Slew &to_slew = graph_->slew(to_vertex, to_rf, slew_index);
bool from_ideal_clk = isIdealClk(from_vertex);
const char *from_slew_annotation = from_ideal_clk ? " (ideal clock)" : nullptr;
arc_delay_calc_->reportCheckDelay(cell, arc, from_slew, from_slew_annotation,
@ -1769,9 +1769,9 @@ GraphDelayCalc1::reportDelayCalc(Edge *edge,
}
else {
Parasitic *to_parasitic =
arc_delay_calc_->findParasitic(to_pin, to_tr, dcalc_ap);
const Slew &from_slew = edgeFromSlew(from_vertex, from_tr, edge, dcalc_ap);
float load_cap = loadCap(to_pin, to_parasitic, to_tr, dcalc_ap);
arc_delay_calc_->findParasitic(to_pin, to_rf, dcalc_ap);
const Slew &from_slew = edgeFromSlew(from_vertex, from_rf, edge, dcalc_ap);
float load_cap = loadCap(to_pin, to_parasitic, to_rf, dcalc_ap);
arc_delay_calc_->reportGateDelay(cell, arc,
from_slew, load_cap, to_parasitic,
related_out_cap, pvt, dcalc_ap,

26
dcalc/GraphDelayCalc1.hh
View File

@ -53,23 +53,23 @@ public:
virtual void setObserver(DelayCalcObserver *observer);
// Load pin_cap + wire_cap.
virtual float loadCap(const Pin *drvr_pin,
const TransRiseFall *drvr_tr,
const RiseFall *drvr_rf,
const DcalcAnalysisPt *dcalc_ap) const;
virtual float loadCap(const Pin *drvr_pin,
const DcalcAnalysisPt *dcalc_ap) const;
virtual void loadCap(const Pin *drvr_pin,
Parasitic *drvr_parasitic,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap,
// Return values.
float &pin_cap,
float &wire_cap) const;
virtual float loadCap(const Pin *drvr_pin,
Parasitic *drvr_parasitic,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap) const;
virtual void netCaps(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap,
// Return values.
float &pin_cap,
@ -92,12 +92,12 @@ protected:
ArcDelayCalc *arc_delay_calc);
void seedNoDrvrSlew(Vertex *drvr_vertex,
const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAnalysisPt *dcalc_ap,
ArcDelayCalc *arc_delay_calc);
void seedNoDrvrCellSlew(Vertex *drvr_vertex,
const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
InputDrive *drive,
DcalcAnalysisPt *dcalc_ap,
ArcDelayCalc *arc_delay_calc);
@ -106,7 +106,7 @@ protected:
void findInputDriverDelay(LibertyCell *drvr_cell,
const Pin *drvr_pin,
Vertex *drvr_vertex,
const TransRiseFall *tr,
const RiseFall *rf,
LibertyPort *from_port,
float *from_slews,
LibertyPort *to_port,
@ -155,7 +155,7 @@ protected:
const DcalcAnalysisPt *dcalc_ap,
ArcDelayCalc *arc_delay_calc);
void annotateLoadDelays(Vertex *drvr_vertex,
const TransRiseFall *drvr_tr,
const RiseFall *drvr_rf,
const ArcDelay &extra_delay,
bool merge,
const DcalcAnalysisPt *dcalc_ap,
@ -165,7 +165,7 @@ protected:
void findCheckEdgeDelays(Edge *edge,
ArcDelayCalc *arc_delay_calc);
void findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr,
const TransRiseFall *drvr_tr,
const RiseFall *drvr_rf,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
ArcDelayCalc *arc_delay_calc,
@ -187,11 +187,11 @@ protected:
Slew &gate_slew);
void deleteMultiDrvrNets();
Slew edgeFromSlew(const Vertex *from_vertex,
const TransRiseFall *from_tr,
const RiseFall *from_rf,
const Edge *edge,
const DcalcAnalysisPt *dcalc_ap);
Slew checkEdgeClkSlew(const Vertex *from_vertex,
const TransRiseFall *from_tr,
const RiseFall *from_rf,
const DcalcAnalysisPt *dcalc_ap);
bool bidirectDrvrSlewFromLoad(const Vertex *vertex) const;
void clearIdealClkMap();
@ -200,7 +200,7 @@ protected:
ClockSet *idealClks(const Vertex *vertex);
bool isIdealClk(const Vertex *vertex);
Slew idealClkSlew(const Vertex *vertex,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max);
MultiDrvrNet *multiDrvrNet(const Vertex *drvr_vertex) const;
void loadCap(Parasitic *drvr_parasitic,
@ -211,7 +211,7 @@ protected:
float loadCap(const Pin *drvr_pin,
MultiDrvrNet *multi_drvr,
Parasitic *drvr_parasitic,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap) const;
void mergeIdealClks();

30
dcalc/LumpedCapDelayCalc.cc
View File

@ -48,7 +48,7 @@ LumpedCapDelayCalc::copy()
Parasitic *
LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap)
{
// set_load has precidence over parasitics.
@ -57,7 +57,7 @@ LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin,
const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
if (parasitics_->haveParasitics()) {
// Prefer PiElmore.
parasitic = parasitics_->findPiElmore(drvr_pin, tr,parasitic_ap);
parasitic = parasitics_->findPiElmore(drvr_pin, rf, parasitic_ap);
if (parasitic)
return parasitic;
@ -69,7 +69,7 @@ LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin,
dcalc_ap->corner(),
dcalc_ap->constraintMinMax(),
parasitic_ap);
parasitic = parasitics_->findPiElmore(drvr_pin, tr,parasitic_ap);
parasitic = parasitics_->findPiElmore(drvr_pin, rf, parasitic_ap);
reduced_parasitic_drvrs_.push_back(drvr_pin);
return parasitic;
}
@ -80,9 +80,9 @@ LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin,
if (wireload) {
float pin_cap, wire_cap, fanout;
bool has_wire_cap;
graph_delay_calc_->netCaps(drvr_pin, tr, dcalc_ap,
graph_delay_calc_->netCaps(drvr_pin, rf, dcalc_ap,
pin_cap, wire_cap, fanout, has_wire_cap);
parasitic = parasitics_->estimatePiElmore(drvr_pin, tr, wireload,
parasitic = parasitics_->estimatePiElmore(drvr_pin, rf, wireload,
fanout, pin_cap,
dcalc_ap->operatingConditions(),
dcalc_ap->corner(),
@ -110,12 +110,12 @@ LumpedCapDelayCalc::finishDrvrPin()
void
LumpedCapDelayCalc::inputPortDelay(const Pin *, float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *,
const DcalcAnalysisPt *)
{
drvr_slew_ = in_slew;
drvr_tr_ = tr;
drvr_rf_ = rf;
drvr_library_ = network_->defaultLibertyLibrary();
multi_drvr_slew_factor_ = 1.0F;
}
@ -167,7 +167,7 @@ LumpedCapDelayCalc::gateDelay(const LibertyCell *drvr_cell,
drvr_slew = delay_zero;
drvr_slew_ = 0.0;
}
drvr_tr_ = arc->toTrans()->asRiseFall();
drvr_rf_ = arc->toTrans()->asRiseFall();
drvr_library_ = drvr_cell->libertyLibrary();
multi_drvr_slew_factor_ = 1.0F;
}
@ -193,17 +193,17 @@ LumpedCapDelayCalc::thresholdAdjust(const Pin *load_pin,
if (load_library
&& drvr_library_
&& load_library != drvr_library_) {
float drvr_vth = drvr_library_->outputThreshold(drvr_tr_);
float load_vth = load_library->inputThreshold(drvr_tr_);
float drvr_slew_delta = drvr_library_->slewUpperThreshold(drvr_tr_)
- drvr_library_->slewLowerThreshold(drvr_tr_);
float drvr_vth = drvr_library_->outputThreshold(drvr_rf_);
float load_vth = load_library->inputThreshold(drvr_rf_);
float drvr_slew_delta = drvr_library_->slewUpperThreshold(drvr_rf_)
- drvr_library_->slewLowerThreshold(drvr_rf_);
float load_delay_delta =
delayAsFloat(load_slew) * ((load_vth - drvr_vth) / drvr_slew_delta);
load_delay += (drvr_tr_ == TransRiseFall::rise())
load_delay += (drvr_rf_ == RiseFall::rise())
? load_delay_delta
: -load_delay_delta;
float load_slew_delta = load_library->slewUpperThreshold(drvr_tr_)
- load_library->slewLowerThreshold(drvr_tr_);
float load_slew_delta = load_library->slewUpperThreshold(drvr_rf_)
- load_library->slewLowerThreshold(drvr_rf_);
float drvr_slew_derate = drvr_library_->slewDerateFromLibrary();
float load_slew_derate = load_library->slewDerateFromLibrary();
load_slew = load_slew * ((load_slew_delta / load_slew_derate)

6
dcalc/LumpedCapDelayCalc.hh
View File

@ -29,11 +29,11 @@ public:
LumpedCapDelayCalc(StaState *sta);
virtual ArcDelayCalc *copy();
virtual Parasitic *findParasitic(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap);
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void gateDelay(const LibertyCell *drvr_cell,
@ -102,7 +102,7 @@ protected:
Slew drvr_slew_;
float multi_drvr_slew_factor_;
const LibertyLibrary *drvr_library_;
const TransRiseFall *drvr_tr_;
const RiseFall *drvr_rf_;
// Parasitics returned by findParasitic that are reduced or estimated
// that can be deleted after delay calculation for the driver pin
// is finished.

10
dcalc/RCDelayCalc.cc
View File

@ -38,13 +38,13 @@ RCDelayCalc::copy()
void
RCDelayCalc::inputPortDelay(const Pin *,
float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *parasitic,
const DcalcAnalysisPt *)
{
drvr_parasitic_ = parasitic;
drvr_slew_ = in_slew;
drvr_tr_ = tr;
drvr_rf_ = rf;
drvr_cell_ = nullptr;
drvr_library_ = network_->defaultLibertyLibrary();
multi_drvr_slew_factor_ = 1.0F;
@ -66,9 +66,9 @@ RCDelayCalc::dspfWireDelaySlew(const Pin *,
float vh = .8;
float slew_derate = 1.0;
if (drvr_library_) {
vth = drvr_library_->inputThreshold(drvr_tr_);
vl = drvr_library_->slewLowerThreshold(drvr_tr_);
vh = drvr_library_->slewUpperThreshold(drvr_tr_);
vth = drvr_library_->inputThreshold(drvr_rf_);
vl = drvr_library_->slewLowerThreshold(drvr_rf_);
vh = drvr_library_->slewUpperThreshold(drvr_rf_);
slew_derate = drvr_library_->slewDerateFromLibrary();
}
wire_delay = static_cast<float>(-elmore * log(1.0 - vth));

2
dcalc/RCDelayCalc.hh
View File

@ -29,7 +29,7 @@ public:
virtual ArcDelayCalc *copy();
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);

10
dcalc/SimpleRCDelayCalc.cc
View File

@ -45,12 +45,12 @@ SimpleRCDelayCalc::copy()
void
SimpleRCDelayCalc::inputPortDelay(const Pin *port_pin,
float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap)
{
pvt_ = dcalc_ap->operatingConditions();
RCDelayCalc::inputPortDelay(port_pin, in_slew, tr, parasitic, dcalc_ap);
RCDelayCalc::inputPortDelay(port_pin, in_slew, rf, parasitic, dcalc_ap);
}
void
@ -67,7 +67,7 @@ SimpleRCDelayCalc::gateDelay(const LibertyCell *drvr_cell,
Slew &drvr_slew)
{
drvr_parasitic_ = drvr_parasitic;
drvr_tr_ = arc->toTrans()->asRiseFall();
drvr_rf_ = arc->toTrans()->asRiseFall();
drvr_cell_ = drvr_cell;
drvr_library_ = drvr_cell->libertyLibrary();
pvt_ = pvt;
@ -89,9 +89,9 @@ SimpleRCDelayCalc::loadDelay(const Pin *load_pin,
if (drvr_parasitic_)
parasitics_->findElmore(drvr_parasitic_, load_pin, elmore, elmore_exists);
if (elmore_exists) {
if (drvr_library_ && drvr_library_->wireSlewDegradationTable(drvr_tr_)) {
if (drvr_library_ && drvr_library_->wireSlewDegradationTable(drvr_rf_)) {
wire_delay1 = elmore;
load_slew1 = drvr_library_->degradeWireSlew(drvr_cell_, drvr_tr_,
load_slew1 = drvr_library_->degradeWireSlew(drvr_cell_, drvr_rf_,
pvt_,
delayAsFloat(drvr_slew_),
delayAsFloat(wire_delay1));

2
dcalc/SimpleRCDelayCalc.hh
View File

@ -33,7 +33,7 @@ public:
virtual ArcDelayCalc *copy();
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void gateDelay(const LibertyCell *drvr_cell,

4
dcalc/UnitDelayCalc.cc
View File

@ -39,7 +39,7 @@ UnitDelayCalc::copy()
Parasitic *
UnitDelayCalc::findParasitic(const Pin *,
const TransRiseFall *,
const RiseFall *,
const DcalcAnalysisPt *)
{
return nullptr;
@ -48,7 +48,7 @@ UnitDelayCalc::findParasitic(const Pin *,
void
UnitDelayCalc::inputPortDelay(const Pin *,
float,
const TransRiseFall *,
const RiseFall *,
Parasitic *,
const DcalcAnalysisPt *)
{

4
dcalc/UnitDelayCalc.hh
View File

@ -28,7 +28,7 @@ public:
UnitDelayCalc(StaState *sta);
virtual ArcDelayCalc *copy();
virtual Parasitic *findParasitic(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap);
virtual void gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
@ -56,7 +56,7 @@ public:
const DcalcAnalysisPt *dcalc_ap);
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const TransRiseFall *tr,
const RiseFall *rf,
Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void checkDelay(const LibertyCell *cell,

3
doc/ApiChanges.txt
View File

@ -22,6 +22,9 @@ Release 2.0.17 2019/11/11
Network::setVertexIndex renamed to setVertexId
Network::vertexIndex renamed to vertexId
TransRiseFall renamed to RiseFall
TransRiseFallBoth renamed to RiseFallBoth
Release 2.0.0 2018/06/11
-------------------------

54
graph/Graph.cc
View File

@ -38,14 +38,14 @@ namespace sta {
////////////////////////////////////////////////////////////////
Graph::Graph(StaState *sta,
int slew_tr_count,
int slew_rf_count,
bool have_arc_delays,
DcalcAPIndex ap_count) :
StaState(sta),
vertices_(nullptr),
edges_(nullptr),
arc_count_(0),
slew_tr_count_(slew_tr_count),
slew_rf_count_(slew_rf_count),
have_arc_delays_(have_arc_delays),
ap_count_(ap_count),
width_check_annotations_(nullptr),
@ -553,12 +553,12 @@ Graph::clearPrevPaths()
const Slew &
Graph::slew(const Vertex *vertex,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index)
{
if (slew_tr_count_) {
if (slew_rf_count_) {
int table_index =
(slew_tr_count_ == 1) ? ap_index : ap_index*slew_tr_count_+tr->index();
(slew_rf_count_ == 1) ? ap_index : ap_index*slew_rf_count_+rf->index();
DelayTable *table = slew_tables_[table_index];
VertexId vertex_id = id(vertex);
return table->ref(vertex_id);
@ -571,13 +571,13 @@ Graph::slew(const Vertex *vertex,
void
Graph::setSlew(Vertex *vertex,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index,
const Slew &slew)
{
if (slew_tr_count_) {
if (slew_rf_count_) {
int table_index =
(slew_tr_count_ == 1) ? ap_index : ap_index*slew_tr_count_+tr->index();
(slew_rf_count_ == 1) ? ap_index : ap_index*slew_rf_count_+rf->index();
DelayTable *table = slew_tables_[table_index];
VertexId vertex_id = id(vertex);
Slew &vertex_slew = table->ref(vertex_id);
@ -707,13 +707,13 @@ Graph::setArcDelay(Edge *edge,
const ArcDelay &
Graph::wireArcDelay(const Edge *edge,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index)
{
if (have_arc_delays_) {
DelayTable *table = arc_delays_[ap_index];
ArcDelay *arc_delays = table->pointer(edge->arcDelays());
return arc_delays[tr->index()];
return arc_delays[rf->index()];
}
else
return delay_zero;
@ -721,14 +721,14 @@ Graph::wireArcDelay(const Edge *edge,
void
Graph::setWireArcDelay(Edge *edge,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index,
const ArcDelay &delay)
{
if (have_arc_delays_) {
DelayTable *table = arc_delays_[ap_index];
ArcDelay *arc_delays = table->pointer(edge->arcDelays());
arc_delays[tr->index()] = delay;
arc_delays[rf->index()] = delay;
}
}
@ -761,10 +761,10 @@ Graph::setArcDelayAnnotated(Edge *edge,
bool
Graph::wireDelayAnnotated(Edge *edge,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index) const
{
size_t index = (edge->arcDelays() + TimingArcSet::wireArcIndex(tr)) * ap_count_
size_t index = (edge->arcDelays() + TimingArcSet::wireArcIndex(rf)) * ap_count_
+ ap_index;
if (index >= arc_delay_annotated_.size())
internalError("arc_delay_annotated array bounds exceeded");
@ -773,11 +773,11 @@ Graph::wireDelayAnnotated(Edge *edge,
void
Graph::setWireDelayAnnotated(Edge *edge,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index,
bool annotated)
{
size_t index = (edge->arcDelays() + TimingArcSet::wireArcIndex(tr)) * ap_count_
size_t index = (edge->arcDelays() + TimingArcSet::wireArcIndex(rf)) * ap_count_
+ ap_index;
if (index >= arc_delay_annotated_.size())
internalError("arc_delay_annotated array bounds exceeded");
@ -850,7 +850,7 @@ Graph::delayAnnotated(Edge *edge)
void
Graph::makeSlewTables(DcalcAPIndex ap_count)
{
DcalcAPIndex tr_ap_count = slew_tr_count_ * ap_count;
DcalcAPIndex tr_ap_count = slew_rf_count_ * ap_count;
slew_tables_.resize(tr_ap_count);
for (DcalcAPIndex i = 0; i < tr_ap_count; i++) {
DelayTable *table = new DelayTable;
@ -867,7 +867,7 @@ Graph::deleteSlewTables()
void
Graph::makeVertexSlews(Vertex *vertex)
{
DcalcAPIndex tr_ap_count = slew_tr_count_ * ap_count_;
DcalcAPIndex tr_ap_count = slew_rf_count_ * ap_count_;
for (DcalcAPIndex i = 0; i < tr_ap_count; i++) {
DelayTable *table = slew_tables_[i];
// Slews are 1:1 with vertices and use the same object id.
@ -880,7 +880,7 @@ Graph::makeVertexSlews(Vertex *vertex)
void
Graph::widthCheckAnnotation(const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index,
// Return values.
float &width,
@ -890,7 +890,7 @@ Graph::widthCheckAnnotation(const Pin *pin,
if (width_check_annotations_) {
float *widths = width_check_annotations_->findKey(pin);
if (widths) {
int index = ap_index * TransRiseFall::index_count + tr->index();
int index = ap_index * RiseFall::index_count + rf->index();
width = widths[index];
if (width >= 0.0)
exists = true;
@ -900,7 +900,7 @@ Graph::widthCheckAnnotation(const Pin *pin,
void
Graph::setWidthCheckAnnotation(const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index,
float width)
{
@ -908,14 +908,14 @@ Graph::setWidthCheckAnnotation(const Pin *pin,
width_check_annotations_ = new WidthCheckAnnotations;
float *widths = width_check_annotations_->findKey(pin);
if (widths == nullptr) {
int width_count = TransRiseFall::index_count * ap_count_;
int width_count = RiseFall::index_count * ap_count_;
widths = new float[width_count];
// Use negative (illegal) width values to indicate unannotated checks.
for (int i = 0; i < width_count; i++)
widths[i] = -1;
(*width_check_annotations_)[pin] = widths;
}
int index = ap_index * TransRiseFall::index_count + tr->index();
int index = ap_index * RiseFall::index_count + rf->index();
widths[index] = width;
}
@ -1091,10 +1091,10 @@ Vertex::setColor(LevelColor color)
}
bool
Vertex::slewAnnotated(const TransRiseFall *tr,
Vertex::slewAnnotated(const RiseFall *rf,
const MinMax *min_max) const
{
int index = min_max->index() * transitionCount() + tr->index();
int index = min_max->index() * transitionCount() + rf->index();
return ((1 << index) & slew_annotated_) != 0;
}
@ -1106,14 +1106,14 @@ Vertex::slewAnnotated() const
void
Vertex::setSlewAnnotated(bool annotated,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index)
{
// Track rise/fall/min/max annotations separately, but after that
// only rise/fall.
if (ap_index > 1)
ap_index = 0;
int index = ap_index * transitionCount() + tr->index();
int index = ap_index * transitionCount() + rf->index();
if (annotated)
slew_annotated_ |= (1 << index);
else

26
graph/Graph.hh
View File

@ -64,13 +64,13 @@ static constexpr ObjectIdx prev_path_null = object_id_null;
class Graph : public StaState
{
public:
// slew_tr_count is
// slew_rf_count is
// 0 no slews
// 1 one slew for rise/fall
// 2 rise/fall slews
// ap_count is the dcalc analysis point count.
Graph(StaState *sta,
int slew_tr_count,
int slew_rf_count,
bool have_arc_delays,
DcalcAPIndex ap_count);
void makeGraph();
@ -112,10 +112,10 @@ public:
// reported_slews = measured_slews / slew_derate_from_library
// Measured slews are between slew_lower_threshold and slew_upper_threshold.
virtual const Slew &slew(const Vertex *vertex,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index);
virtual void setSlew(Vertex *vertex,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index,
const Slew &slew);
@ -142,10 +142,10 @@ public:
ArcDelay delay);
// Alias for arcDelays using library wire arcs.
virtual const ArcDelay &wireArcDelay(const Edge *edge,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index);
virtual void setWireArcDelay(Edge *edge,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index,
const ArcDelay &delay);
// Is timing arc delay annotated.
@ -157,10 +157,10 @@ public:
DcalcAPIndex ap_index,
bool annotated);
bool wireDelayAnnotated(Edge *edge,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index) const;
void setWireDelayAnnotated(Edge *edge,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index,
bool annotated);
// True if any edge arc is annotated.
@ -170,13 +170,13 @@ public:
// Sdf width check annotation.
void widthCheckAnnotation(const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index,
// Return values.
float &width,
bool &exists);
void setWidthCheckAnnotation(const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index,
float width);
@ -237,7 +237,7 @@ protected:
PrevPathsTable prev_paths_;
std::mutex prev_paths_lock_;
Vector<bool> arc_delay_annotated_;
int slew_tr_count_;
int slew_rf_count_;
bool have_arc_delays_;
DcalcAPIndex ap_count_;
DelayTableSeq slew_tables_; // [ap_index][tr_index][vertex_id]
@ -285,12 +285,12 @@ public:
TagGroupIndex tagGroupIndex() const;
void setTagGroupIndex(TagGroupIndex tag_index);
// Slew is annotated by sdc set_annotated_transition cmd.
bool slewAnnotated(const TransRiseFall *tr,
bool slewAnnotated(const RiseFall *rf,
const MinMax *min_max) const;
// True if any rise/fall analysis pt slew is annotated.
bool slewAnnotated() const;
void setSlewAnnotated(bool annotated,
const TransRiseFall *tr,
const RiseFall *rf,
DcalcAPIndex ap_index);
void removeSlewAnnotated();
// Constant zero/one from simulation.

2
graph/GraphClass.hh
View File

@ -49,7 +49,7 @@ typedef Vector<GraphLoop*> GraphLoopSeq;
// 16,777,215 tags
static const int tag_group_index_bits = 24;
static const TagGroupIndex tag_group_index_max = (1<<tag_group_index_bits)-1;
static const int slew_annotated_bits = MinMax::index_count * TransRiseFall::index_count;
static const int slew_annotated_bits = MinMax::index_count * RiseFall::index_count;
// Bit shifts used to mark vertices in a Bfs queue.
enum class BfsIndex { dcalc, arrival, required, other, bits };

16
liberty/InternalPower.cc
View File

@ -36,7 +36,7 @@ InternalPowerAttrs::~InternalPowerAttrs()
void
InternalPowerAttrs::deleteContents()
{
for (auto tr_index : TransRiseFall::rangeIndex()) {
for (auto tr_index : RiseFall::rangeIndex()) {
InternalPowerModel *model = models_[tr_index];
if (model)
delete model;
@ -47,16 +47,16 @@ InternalPowerAttrs::deleteContents()
}
InternalPowerModel *
InternalPowerAttrs::model(TransRiseFall *tr) const
InternalPowerAttrs::model(RiseFall *rf) const
{
return models_[tr->index()];
return models_[rf->index()];
}
void
InternalPowerAttrs::setModel(TransRiseFall *tr,
InternalPowerAttrs::setModel(RiseFall *rf,
InternalPowerModel *model)
{
models_[tr->index()] = model;
models_[rf->index()] = model;
}
void
@ -77,7 +77,7 @@ InternalPower::InternalPower(LibertyCell *cell,
when_(attrs->when()),
related_pg_pin_(attrs->relatedPgPin())
{
for (auto tr : TransRiseFall::range()) {
for (auto tr : RiseFall::range()) {
int tr_index = tr->index();
models_[tr_index] = attrs->model(tr);
}
@ -96,12 +96,12 @@ InternalPower::libertyCell() const
}
float
InternalPower::power(TransRiseFall *tr,
InternalPower::power(RiseFall *rf,
const Pvt *pvt,
float in_slew,
float load_cap)
{
InternalPowerModel *model = models_[tr->index()];
InternalPowerModel *model = models_[rf->index()];
if (model)
return model->power(libertyCell(), pvt, in_slew, load_cap);
else

10
liberty/InternalPower.hh
View File

@ -34,15 +34,15 @@ public:
void deleteContents();
FuncExpr *when() const { return when_; }
FuncExpr *&whenRef() { return when_; }
void setModel(TransRiseFall *tr,
void setModel(RiseFall *rf,
InternalPowerModel *model);
InternalPowerModel *model(TransRiseFall *tr) const;
InternalPowerModel *model(RiseFall *rf) const;
const char *relatedPgPin() const { return related_pg_pin_; }
void setRelatedPgPin(const char *related_pg_pin);
protected:
FuncExpr *when_;
InternalPowerModel *models_[TransRiseFall::index_count];
InternalPowerModel *models_[RiseFall::index_count];
const char *related_pg_pin_;
private:
@ -62,7 +62,7 @@ public:
LibertyPort *relatedPort() const { return related_port_; }
FuncExpr *when() const { return when_; }
const char *relatedPgPin() const { return related_pg_pin_; }
float power(TransRiseFall *tr,
float power(RiseFall *rf,
const Pvt *pvt,
float in_slew,
float load_cap);
@ -72,7 +72,7 @@ protected:
LibertyPort *related_port_;
FuncExpr *when_;
const char *related_pg_pin_;
InternalPowerModel *models_[TransRiseFall::index_count];
InternalPowerModel *models_[RiseFall::index_count];
private:
DISALLOW_COPY_AND_ASSIGN(InternalPower);

190
liberty/Liberty.cc
View File

@ -94,7 +94,7 @@ LibertyLibrary::LibertyLibrary(const char *name,
addTableTemplate(scalar_template, type);
}
for (auto tr_index : TransRiseFall::rangeIndex()) {
for (auto tr_index : RiseFall::rangeIndex()) {
wire_slew_degradation_tbls_[tr_index] = nullptr;
input_threshold_[tr_index] = input_threshold_default_;
output_threshold_[tr_index] = output_threshold_default_;
@ -111,7 +111,7 @@ LibertyLibrary::~LibertyLibrary()
scale_factors_map_.deleteContents();
delete scale_factors_;
for (auto tr_index : TransRiseFall::rangeIndex()) {
for (auto tr_index : RiseFall::rangeIndex()) {
TableModel *model = wire_slew_degradation_tbls_[tr_index];
delete model;
}
@ -278,28 +278,28 @@ LibertyLibrary::scaleFactor(ScaleFactorType type,
void
LibertyLibrary::setWireSlewDegradationTable(TableModel *model,
TransRiseFall *tr)
RiseFall *rf)
{
int tr_index = tr->index();
int tr_index = rf->index();
if (wire_slew_degradation_tbls_[tr_index])
delete wire_slew_degradation_tbls_[tr_index];
wire_slew_degradation_tbls_[tr_index] = model;
}
TableModel *
LibertyLibrary::wireSlewDegradationTable(const TransRiseFall *tr) const
LibertyLibrary::wireSlewDegradationTable(const RiseFall *rf) const
{
return wire_slew_degradation_tbls_[tr->index()];
return wire_slew_degradation_tbls_[rf->index()];
}
float
LibertyLibrary::degradeWireSlew(const LibertyCell *cell,
const TransRiseFall *tr,
const RiseFall *rf,
const Pvt *pvt,
float in_slew,
float wire_delay) const
{
const TableModel *model = wireSlewDegradationTable(tr);
const TableModel *model = wireSlewDegradationTable(rf);
if (model)
return degradeWireSlew(cell, pvt, model, in_slew, wire_delay);
else
@ -450,64 +450,64 @@ LibertyLibrary::setDefaultOutputPinCap(float cap)
}
void
LibertyLibrary::defaultIntrinsic(const TransRiseFall *tr,
LibertyLibrary::defaultIntrinsic(const RiseFall *rf,
// Return values.
float &intrinsic,
bool &exists) const
{
default_intrinsic_.value(tr, intrinsic, exists);
default_intrinsic_.value(rf, intrinsic, exists);
}
void
LibertyLibrary::setDefaultIntrinsic(const TransRiseFall *tr,
LibertyLibrary::setDefaultIntrinsic(const RiseFall *rf,
float value)
{
default_intrinsic_.setValue(tr, value);
default_intrinsic_.setValue(rf, value);
}
void
LibertyLibrary::defaultPinResistance(const TransRiseFall *tr,
LibertyLibrary::defaultPinResistance(const RiseFall *rf,
const PortDirection *dir,
// Return values.
float &res,
bool &exists) const
{
if (dir->isAnyTristate())
defaultBidirectPinRes(tr, res, exists);
defaultBidirectPinRes(rf, res, exists);
else
defaultOutputPinRes(tr, res, exists);
defaultOutputPinRes(rf, res, exists);
}
void
LibertyLibrary::defaultBidirectPinRes(const TransRiseFall *tr,
LibertyLibrary::defaultBidirectPinRes(const RiseFall *rf,
// Return values.
float &res,
bool &exists) const
{
return default_inout_pin_res_.value(tr, res, exists);
return default_inout_pin_res_.value(rf, res, exists);
}
void
LibertyLibrary::setDefaultBidirectPinRes(const TransRiseFall *tr,
LibertyLibrary::setDefaultBidirectPinRes(const RiseFall *rf,
float value)
{
default_inout_pin_res_.setValue(tr, value);
default_inout_pin_res_.setValue(rf, value);
}
void
LibertyLibrary::defaultOutputPinRes(const TransRiseFall *tr,
LibertyLibrary::defaultOutputPinRes(const RiseFall *rf,
// Return values.
float &res,
bool &exists) const
{
default_output_pin_res_.value(tr, res, exists);
default_output_pin_res_.value(rf, res, exists);
}
void
LibertyLibrary::setDefaultOutputPinRes(const TransRiseFall *tr,
LibertyLibrary::setDefaultOutputPinRes(const RiseFall *rf,
float value)
{
default_output_pin_res_.setValue(tr, value);
default_output_pin_res_.setValue(rf, value);
}
void
@ -595,55 +595,55 @@ LibertyLibrary::setDefaultOperatingConditions(OperatingConditions *op_cond)
}
float
LibertyLibrary::inputThreshold(const TransRiseFall *tr) const
LibertyLibrary::inputThreshold(const RiseFall *rf) const
{
return input_threshold_[tr->index()];
return input_threshold_[rf->index()];
}
void
LibertyLibrary::setInputThreshold(const TransRiseFall *tr,
LibertyLibrary::setInputThreshold(const RiseFall *rf,
float th)
{
input_threshold_[tr->index()] = th;
input_threshold_[rf->index()] = th;
}
float
LibertyLibrary::outputThreshold(const TransRiseFall *tr) const
LibertyLibrary::outputThreshold(const RiseFall *rf) const
{
return output_threshold_[tr->index()];
return output_threshold_[rf->index()];
}
void
LibertyLibrary::setOutputThreshold(const TransRiseFall *tr,
LibertyLibrary::setOutputThreshold(const RiseFall *rf,
float th)
{
output_threshold_[tr->index()] = th;
output_threshold_[rf->index()] = th;
}
float
LibertyLibrary::slewLowerThreshold(const TransRiseFall *tr) const
LibertyLibrary::slewLowerThreshold(const RiseFall *rf) const
{
return slew_lower_threshold_[tr->index()];
return slew_lower_threshold_[rf->index()];
}
void
LibertyLibrary::setSlewLowerThreshold(const TransRiseFall *tr,
LibertyLibrary::setSlewLowerThreshold(const RiseFall *rf,
float th)
{
slew_lower_threshold_[tr->index()] = th;
slew_lower_threshold_[rf->index()] = th;
}
float
LibertyLibrary::slewUpperThreshold(const TransRiseFall *tr) const
LibertyLibrary::slewUpperThreshold(const RiseFall *rf) const
{
return slew_upper_threshold_[tr->index()];
return slew_upper_threshold_[rf->index()];
}
void
LibertyLibrary::setSlewUpperThreshold(const TransRiseFall *tr,
LibertyLibrary::setSlewUpperThreshold(const RiseFall *rf,
float th)
{
slew_upper_threshold_[tr->index()] = th;
slew_upper_threshold_[rf->index()] = th;
}
float
@ -1507,7 +1507,7 @@ class LatchEnable
public:
LatchEnable(LibertyPort *data,
LibertyPort *enable,
TransRiseFall *enable_tr,
RiseFall *enable_rf,
FuncExpr *enable_func,
LibertyPort *output,
TimingArcSet *d_to_q,
@ -1517,7 +1517,7 @@ public:
LibertyPort *output() const { return output_; }
LibertyPort *enable() const { return enable_; }
FuncExpr *enableFunc() const { return enable_func_; }
TransRiseFall *enableTransition() const { return enable_tr_; }
RiseFall *enableTransition() const { return enable_rf_; }
TimingArcSet *dToQ() const { return d_to_q_; }
TimingArcSet *enToQ() const { return en_to_q_; }
TimingArcSet *setupCheck() const { return setup_check_; }
@ -1527,7 +1527,7 @@ private:
LibertyPort *data_;
LibertyPort *enable_;
TransRiseFall *enable_tr_;
RiseFall *enable_rf_;
FuncExpr *enable_func_;
LibertyPort *output_;
TimingArcSet *d_to_q_;
@ -1537,7 +1537,7 @@ private:
LatchEnable::LatchEnable(LibertyPort *data,
LibertyPort *enable,
TransRiseFall *enable_tr,
RiseFall *enable_rf,
FuncExpr *enable_func,
LibertyPort *output,
TimingArcSet *d_to_q,
@ -1545,7 +1545,7 @@ LatchEnable::LatchEnable(LibertyPort *data,
TimingArcSet *setup_check) :
data_(data),
enable_(enable),
enable_tr_(enable_tr),
enable_rf_(enable_rf),
enable_func_(enable_func),
output_(output),
d_to_q_(d_to_q),
@ -1583,38 +1583,38 @@ LibertyCell::makeLatchEnables(Report *report,
TimingArcSetArcIterator check_arc_iter(setup_check);
if (check_arc_iter.hasNext()) {
TimingArc *check_arc = check_arc_iter.next();
TransRiseFall *en_tr = latch_enable->enableTransition();
TransRiseFall *check_tr = check_arc->fromTrans()->asRiseFall();
if (check_tr == en_tr) {
RiseFall *en_rf = latch_enable->enableTransition();
RiseFall *check_rf = check_arc->fromTrans()->asRiseFall();
if (check_rf == en_rf) {
report->warn("cell %s/%s %s -> %s latch enable %s_edge timing arc is inconsistent with %s -> %s setup_%s check.\n",
library_->name(),
name_,
en->name(),
q->name(),
en_tr == TransRiseFall::rise()?"rising":"falling",
en_rf == RiseFall::rise()?"rising":"falling",
en->name(),
d->name(),
check_tr==TransRiseFall::rise()?"rising":"falling");
check_rf==RiseFall::rise()?"rising":"falling");
}
FuncExpr *en_func = latch_enable->enableFunc();
if (en_func) {
TimingSense en_sense = en_func->portTimingSense(en);
if (en_sense == TimingSense::positive_unate
&& en_tr != TransRiseFall::rise())
&& en_rf != RiseFall::rise())
report->warn("cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function positive sense.\n",
library_->name(),
name_,
en->name(),
q->name(),
en_tr == TransRiseFall::rise()?"rising":"falling");
en_rf == RiseFall::rise()?"rising":"falling");
else if (en_sense == TimingSense::negative_unate
&& en_tr != TransRiseFall::fall())
&& en_rf != RiseFall::fall())
report->warn("cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function negative sense.\n",
library_->name(),
name_,
en->name(),
q->name(),
en_tr == TransRiseFall::rise()?"rising":"falling");
en_rf == RiseFall::rise()?"rising":"falling");
}
break;
}
@ -1651,9 +1651,9 @@ LibertyCell::makeLatchEnable(LibertyPort *d,
TimingArcSet *setup_check,
Debug *debug)
{
TransRiseFall *en_tr = en_to_q->isRisingFallingEdge();
RiseFall *en_rf = en_to_q->isRisingFallingEdge();
FuncExpr *en_func = findLatchEnableFunc(d, en);
LatchEnable *latch_enable = new LatchEnable(d, en, en_tr, en_func, q,
LatchEnable *latch_enable = new LatchEnable(d, en, en_rf, en_func, q,
d_to_q, en_to_q, setup_check);
// Multiple enables for D->Q pairs are not supported.
if (latch_d_to_q_map_[d_to_q])
@ -1720,18 +1720,18 @@ LibertyCell::latchEnable(TimingArcSet *d_to_q_set,
// Return values.
LibertyPort *&enable_port,
FuncExpr *&enable_func,
TransRiseFall *&enable_tr) const
RiseFall *&enable_rf) const
{
enable_port = nullptr;
LatchEnable *latch_enable = latch_d_to_q_map_.findKey(d_to_q_set);
if (latch_enable) {
enable_port = latch_enable->enable();
enable_func = latch_enable->enableFunc();
enable_tr = latch_enable->enableTransition();
enable_rf = latch_enable->enableTransition();
}
}
TransRiseFall *
RiseFall *
LibertyCell::latchCheckEnableTrans(TimingArcSet *check_set)
{
LatchEnable *latch_enable = latch_check_map_.findKey(check_set);
@ -1817,8 +1817,8 @@ LibertyPort::LibertyPort(LibertyCell *cell,
is_disabled_constraint_(false)
{
liberty_port_ = this;
min_pulse_width_[TransRiseFall::riseIndex()] = 0.0;
min_pulse_width_[TransRiseFall::fallIndex()] = 0.0;
min_pulse_width_[RiseFall::riseIndex()] = 0.0;
min_pulse_width_[RiseFall::fallIndex()] = 0.0;
}
LibertyPort::~LibertyPort()
@ -1855,34 +1855,34 @@ LibertyPort::findLibertyBusBit(int index) const
void
LibertyPort::setCapacitance(float cap)
{
setCapacitance(TransRiseFall::rise(), MinMax::min(), cap);
setCapacitance(TransRiseFall::fall(), MinMax::min(), cap);
setCapacitance(TransRiseFall::rise(), MinMax::max(), cap);
setCapacitance(TransRiseFall::fall(), MinMax::max(), cap);
setCapacitance(RiseFall::rise(), MinMax::min(), cap);
setCapacitance(RiseFall::fall(), MinMax::min(), cap);
setCapacitance(RiseFall::rise(), MinMax::max(), cap);
setCapacitance(RiseFall::fall(), MinMax::max(), cap);
}
void
LibertyPort::setCapacitance(const TransRiseFall *tr,
LibertyPort::setCapacitance(const RiseFall *rf,
const MinMax *min_max,
float cap)
{
capacitance_.setValue(tr, min_max, cap);
capacitance_.setValue(rf, min_max, cap);
if (hasMembers()) {
LibertyPortMemberIterator member_iter(this);
while (member_iter.hasNext()) {
LibertyPort *port_bit = member_iter.next();
port_bit->setCapacitance(tr, min_max, cap);
port_bit->setCapacitance(rf, min_max, cap);
}
}
}
float
LibertyPort::capacitance(const TransRiseFall *tr,
LibertyPort::capacitance(const RiseFall *rf,
const MinMax *min_max) const
{
float cap;
bool exists;
capacitance_.value(tr, min_max, cap, exists);
capacitance_.value(rf, min_max, cap, exists);
if (exists)
return cap;
else
@ -1890,17 +1890,17 @@ LibertyPort::capacitance(const TransRiseFall *tr,
}
void
LibertyPort::capacitance(const TransRiseFall *tr,
LibertyPort::capacitance(const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &cap,
bool &exists) const
{
capacitance_.value(tr, min_max, cap, exists);
capacitance_.value(rf, min_max, cap, exists);
}
float
LibertyPort::capacitance(const TransRiseFall *tr,
LibertyPort::capacitance(const RiseFall *rf,
const MinMax *min_max,
const OperatingConditions *op_cond,
const Pvt *pvt) const
@ -1910,10 +1910,10 @@ LibertyPort::capacitance(const TransRiseFall *tr,
// Scaled capacitance is not derated because scale factors are wrt
// nominal pvt.
if (scaled_port)
return scaled_port->capacitance(tr, min_max);
return scaled_port->capacitance(rf, min_max);
}
LibertyLibrary *lib = liberty_cell_->libertyLibrary();
float cap = capacitance(tr, min_max);
float cap = capacitance(rf, min_max);
return cap * lib->scaleFactor(ScaleFactorType::pin_cap, liberty_cell_, pvt);
}
@ -1927,7 +1927,7 @@ LibertyPort::capacitanceIsOneValue() const
// Use the min/max "drive" for all the timing arcs in the cell.
float
LibertyPort::driveResistance(const TransRiseFall *tr,
LibertyPort::driveResistance(const RiseFall *rf,
const MinMax *min_max) const
{
float max_drive = min_max->initValue();
@ -1939,8 +1939,8 @@ LibertyPort::driveResistance(const TransRiseFall *tr,
TimingArcSetArcIterator arc_iter(set);
while (arc_iter.hasNext()) {
TimingArc *arc = arc_iter.next();
if (tr == nullptr
|| arc->toTrans()->asRiseFall() == tr) {
if (rf == nullptr
|| arc->toTrans()->asRiseFall() == rf) {
GateTimingModel *model = dynamic_cast<GateTimingModel*>(arc->model());
if (model) {
float drive = model->driveResistance(liberty_cell_, nullptr);
@ -2077,7 +2077,7 @@ LibertyPort::setMinPeriod(float min_period)
}
void
LibertyPort::minPulseWidth(const TransRiseFall *hi_low,
LibertyPort::minPulseWidth(const RiseFall *hi_low,
const OperatingConditions *op_cond,
const Pvt *pvt,
float &min_width,
@ -2099,7 +2099,7 @@ LibertyPort::minPulseWidth(const TransRiseFall *hi_low,
}
void
LibertyPort::minPulseWidth(const TransRiseFall *hi_low,
LibertyPort::minPulseWidth(const RiseFall *hi_low,
float &min_width,
bool &exists) const
{
@ -2109,7 +2109,7 @@ LibertyPort::minPulseWidth(const TransRiseFall *hi_low,
}
void
LibertyPort::setMinPulseWidth(TransRiseFall *hi_low,
LibertyPort::setMinPulseWidth(RiseFall *hi_low,
float min_width)
{
int hi_low_index = hi_low->index();
@ -2202,8 +2202,8 @@ LibertyPort::setIsPllFeedbackPin(bool is_pll_feedback_pin)
}
void
LibertyPort::setPulseClk(TransRiseFall *trigger,
TransRiseFall *sense)
LibertyPort::setPulseClk(RiseFall *trigger,
RiseFall *sense)
{
pulse_clk_trigger_ = trigger;
pulse_clk_sense_ = sense;
@ -2575,7 +2575,7 @@ ScaleFactors::ScaleFactors(const char *name) :
{
for (int type = 0; type < scale_factor_type_count; type++) {
for (int pvt = 0; pvt < int(ScaleFactorPvt::count); pvt++) {
for (auto tr_index : TransRiseFall::rangeIndex()) {
for (auto tr_index : RiseFall::rangeIndex()) {
scales_[type][pvt][tr_index] = 0.0;
}
}
@ -2590,10 +2590,10 @@ ScaleFactors::~ScaleFactors()
void
ScaleFactors::setScale(ScaleFactorType type,
ScaleFactorPvt pvt,
TransRiseFall *tr,
RiseFall *rf,
float scale)
{
scales_[int(type)][int(pvt)][tr->index()] = scale;
scales_[int(type)][int(pvt)][rf->index()] = scale;
}
void
@ -2607,9 +2607,9 @@ ScaleFactors::setScale(ScaleFactorType type,
float
ScaleFactors::scale(ScaleFactorType type,
ScaleFactorPvt pvt,
TransRiseFall *tr)
RiseFall *rf)
{
return scales_[int(type)][int(pvt)][tr->index()];
return scales_[int(type)][int(pvt)][rf->index()];
}
float
@ -2644,8 +2644,8 @@ ScaleFactors::print()
|| scaleFactorTypeRiseFallPrefix(type)
|| scaleFactorTypeLowHighSuffix(type)) {
printf(" %.3f,%.3f",
scales_[type_index][pvt_index][TransRiseFall::riseIndex()],
scales_[type_index][pvt_index][TransRiseFall::fallIndex()]);
scales_[type_index][pvt_index][RiseFall::riseIndex()],
scales_[type_index][pvt_index][RiseFall::fallIndex()]);
}
else {
printf(" %.3f",
@ -2714,7 +2714,7 @@ OcvDerate::OcvDerate(const char *name) :
name_(name)
{
for (auto el_index : EarlyLate::rangeIndex()) {
for (auto tr_index : TransRiseFall::rangeIndex()) {
for (auto tr_index : RiseFall::rangeIndex()) {
derate_[tr_index][el_index][int(PathType::clk)] = nullptr;
derate_[tr_index][el_index][int(PathType::data)] = nullptr;
}
@ -2728,7 +2728,7 @@ OcvDerate::~OcvDerate()
// Collect them in a set to avoid duplicate deletes.
Set<Table*> models;
for (auto el_index : EarlyLate::rangeIndex()) {
for (auto tr_index : TransRiseFall::rangeIndex()) {
for (auto tr_index : RiseFall::rangeIndex()) {
Table *derate;
derate = derate_[tr_index][el_index][int(PathType::clk)];
if (derate)
@ -2746,20 +2746,20 @@ OcvDerate::~OcvDerate()
}
Table *
OcvDerate::derateTable(const TransRiseFall *tr,
OcvDerate::derateTable(const RiseFall *rf,
const EarlyLate *early_late,
PathType path_type)
{
return derate_[tr->index()][early_late->index()][int(path_type)];
return derate_[rf->index()][early_late->index()][int(path_type)];
}
void
OcvDerate::setDerateTable(const TransRiseFall *tr,
OcvDerate::setDerateTable(const RiseFall *rf,
const EarlyLate *early_late,
const PathType path_type,
Table *derate)
{
derate_[tr->index()][early_late->index()][int(path_type)] = derate;
derate_[rf->index()][early_late->index()][int(path_type)] = derate;
}
////////////////////////////////////////////////////////////////

94
liberty/Liberty.hh
View File

@ -150,10 +150,10 @@ public:
const LibertyCell *cell,
const Pvt *pvt) const;
void setWireSlewDegradationTable(TableModel *model,
TransRiseFall *tr);
TableModel *wireSlewDegradationTable(const TransRiseFall *tr) const;
RiseFall *rf);
TableModel *wireSlewDegradationTable(const RiseFall *rf) const;
float degradeWireSlew(const LibertyCell *cell,
const TransRiseFall *tr,
const RiseFall *rf,
const Pvt *pvt,
float in_slew,
float wire_delay) const;
@ -168,29 +168,29 @@ public:
float defaultBidirectPinCap() const { return default_bidirect_pin_cap_; }
void setDefaultBidirectPinCap(float cap);
void defaultIntrinsic(const TransRiseFall *tr,
void defaultIntrinsic(const RiseFall *rf,
// Return values.
float &intrisic,
bool &exists) const;
void setDefaultIntrinsic(const TransRiseFall *tr,
void setDefaultIntrinsic(const RiseFall *rf,
float value);
// Uses defaultOutputPinRes or defaultBidirectPinRes based on dir.
void defaultPinResistance(const TransRiseFall *tr,
void defaultPinResistance(const RiseFall *rf,
const PortDirection *dir,
// Return values.
float &res,
bool &exists) const;
void defaultBidirectPinRes(const TransRiseFall *tr,
void defaultBidirectPinRes(const RiseFall *rf,
// Return values.
float &res,
bool &exists) const;
void setDefaultBidirectPinRes(const TransRiseFall *tr,
void setDefaultBidirectPinRes(const RiseFall *rf,
float value);
void defaultOutputPinRes(const TransRiseFall *tr,
void defaultOutputPinRes(const RiseFall *rf,
// Return values.
float &res,
bool &exists) const;
void setDefaultOutputPinRes(const TransRiseFall *tr,
void setDefaultOutputPinRes(const RiseFall *rf,
float value);
void defaultMaxSlew(float &slew,
@ -206,18 +206,18 @@ public:
void setDefaultFanoutLoad(float load);
// Logic thresholds.
float inputThreshold(const TransRiseFall *tr) const;
void setInputThreshold(const TransRiseFall *tr,
float inputThreshold(const RiseFall *rf) const;
void setInputThreshold(const RiseFall *rf,
float th);
float outputThreshold(const TransRiseFall *tr) const;
void setOutputThreshold(const TransRiseFall *tr,
float outputThreshold(const RiseFall *rf) const;
void setOutputThreshold(const RiseFall *rf,
float th);
// Slew thresholds (measured).
float slewLowerThreshold(const TransRiseFall *tr) const;
void setSlewLowerThreshold(const TransRiseFall *tr,
float slewLowerThreshold(const RiseFall *rf) const;
void setSlewLowerThreshold(const RiseFall *rf,
float th);
float slewUpperThreshold(const TransRiseFall *tr) const;
void setSlewUpperThreshold(const TransRiseFall *tr,
float slewUpperThreshold(const RiseFall *rf) const;
void setSlewUpperThreshold(const RiseFall *rf,
float th);
// The library and delay calculator use the liberty slew upper/lower
// (measured) thresholds for the table axes and value. These slews
@ -299,7 +299,7 @@ protected:
float nominal_temperature_;
ScaleFactors *scale_factors_;
ScaleFactorsMap scale_factors_map_;
TableModel *wire_slew_degradation_tbls_[TransRiseFall::index_count];
TableModel *wire_slew_degradation_tbls_[RiseFall::index_count];
float default_input_pin_cap_;
float default_output_pin_cap_;
float default_bidirect_pin_cap_;
@ -313,10 +313,10 @@ protected:
bool default_max_fanout_exists_;
float default_max_slew_;
bool default_max_slew_exists_;
float input_threshold_[TransRiseFall::index_count];
float output_threshold_[TransRiseFall::index_count];
float slew_lower_threshold_[TransRiseFall::index_count];
float slew_upper_threshold_[TransRiseFall::index_count];
float input_threshold_[RiseFall::index_count];
float output_threshold_[RiseFall::index_count];
float slew_lower_threshold_[RiseFall::index_count];
float slew_upper_threshold_[RiseFall::index_count];
float slew_derate_from_library_;
WireloadMap wireloads_;
Wireload *default_wire_load_;
@ -442,8 +442,8 @@ public:
// Return values.
LibertyPort *&enable_port,
FuncExpr *&enable_func,
TransRiseFall *&enable_tr) const;
TransRiseFall *latchCheckEnableTrans(TimingArcSet *check_set);
RiseFall *&enable_rf) const;
RiseFall *latchCheckEnableTrans(TimingArcSet *check_set);
bool isDisabledConstraint() const { return is_disabled_constraint_; }
LibertyCell *cornerCell(int ap_index);
@ -638,25 +638,25 @@ public:
LibertyCell *libertyCell() const { return liberty_cell_; }
LibertyPort *findLibertyMember(int index) const;
LibertyPort *findLibertyBusBit(int index) const;
float capacitance(const TransRiseFall *tr,
float capacitance(const RiseFall *rf,
const MinMax *min_max) const;
void capacitance(const TransRiseFall *tr,
void capacitance(const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &cap,
bool &exists) const;
// Capacitance at op_cond derated by library/cell scale factors
// using pvt.
float capacitance(const TransRiseFall *tr,
float capacitance(const RiseFall *rf,
const MinMax *min_max,
const OperatingConditions *op_cond,
const Pvt *pvt) const;
bool capacitanceIsOneValue() const;
void setCapacitance(float cap);
void setCapacitance(const TransRiseFall *tr,
void setCapacitance(const RiseFall *rf,
const MinMax *min_max,
float cap);
float driveResistance(const TransRiseFall *tr,
float driveResistance(const RiseFall *rf,
const MinMax *min_max) const;
// Max of rise/fall.
float driveResistance() const;
@ -694,16 +694,16 @@ public:
bool &exists) const;
void setMinPeriod(float min_period);
// high = rise, low = fall
void minPulseWidth(const TransRiseFall *hi_low,
void minPulseWidth(const RiseFall *hi_low,
const OperatingConditions *op_cond,
const Pvt *pvt,
float &min_width,
bool &exists) const;
// Unscaled value.
void minPulseWidth(const TransRiseFall *hi_low,
void minPulseWidth(const RiseFall *hi_low,
float &min_width,
bool &exists) const;
void setMinPulseWidth(TransRiseFall *hi_low,
void setMinPulseWidth(RiseFall *hi_low,
float min_width);
bool isClock() const;
void setIsClock(bool is_clk);
@ -721,11 +721,11 @@ public:
// Is the clock for timing checks.
bool isCheckClk() const { return is_check_clk_; }
void setIsCheckClk(bool is_clk);
TransRiseFall *pulseClkTrigger() const { return pulse_clk_trigger_; }
RiseFall *pulseClkTrigger() const { return pulse_clk_trigger_; }
// Rise for high, fall for low.
TransRiseFall *pulseClkSense() const { return pulse_clk_sense_; }
void setPulseClk(TransRiseFall *trigger,
TransRiseFall *sense);
RiseFall *pulseClkSense() const { return pulse_clk_sense_; }
void setPulseClk(RiseFall *rfigger,
RiseFall *sense);
bool isDisabledConstraint() const { return is_disabled_constraint_; }
void setIsDisabledConstraint(bool is_disabled);
LibertyPort *cornerPort(int ap_index);
@ -765,14 +765,14 @@ protected:
MinMaxFloatValues cap_limit_; // outputs
MinMaxFloatValues fanout_limit_; // outputs
float min_period_;
float min_pulse_width_[TransRiseFall::index_count];
TransRiseFall *pulse_clk_trigger_;
TransRiseFall *pulse_clk_sense_;
float min_pulse_width_[RiseFall::index_count];
RiseFall *pulse_clk_trigger_;
RiseFall *pulse_clk_sense_;
const char *related_ground_pin_;
const char *related_power_pin_;
Vector<LibertyPort*> corner_ports_;
unsigned int min_pulse_width_exists_:TransRiseFall::index_count;
unsigned int min_pulse_width_exists_:RiseFall::index_count;
bool min_period_exists_:1;
bool is_clk_:1;
bool is_reg_clk_:1;
@ -864,7 +864,7 @@ public:
const char *name() const { return name_; }
float scale(ScaleFactorType type,
ScaleFactorPvt pvt,
TransRiseFall *tr);
RiseFall *rf);
float scale(ScaleFactorType type,
ScaleFactorPvt pvt,
int tr_index);
@ -872,7 +872,7 @@ public:
ScaleFactorPvt pvt);
void setScale(ScaleFactorType type,
ScaleFactorPvt pvt,
TransRiseFall *tr,
RiseFall *rf,
float scale);
void setScale(ScaleFactorType type,
ScaleFactorPvt pvt,
@ -881,7 +881,7 @@ public:
protected:
const char *name_;
float scales_[scale_factor_type_count][int(ScaleFactorPvt::count)][TransRiseFall::index_count];
float scales_[scale_factor_type_count][int(ScaleFactorPvt::count)][RiseFall::index_count];
private:
DISALLOW_COPY_AND_ASSIGN(ScaleFactors);
@ -1024,10 +1024,10 @@ public:
OcvDerate(const char *name);
~OcvDerate();
const char *name() const { return name_; }
Table *derateTable(const TransRiseFall *tr,
Table *derateTable(const RiseFall *rf,
const EarlyLate *early_late,
PathType path_type);
void setDerateTable(const TransRiseFall *tr,
void setDerateTable(const RiseFall *rf,
const EarlyLate *early_late,
PathType path_type,
Table *derate);
@ -1035,7 +1035,7 @@ public:
private:
const char *name_;
// [rf_type][derate_type][path_type]
Table *derate_[TransRiseFall::index_count][EarlyLate::index_count][path_type_count];
Table *derate_[RiseFall::index_count][EarlyLate::index_count][path_type_count];
};
// Power/ground port.

204
liberty/LibertyBuilder.cc
View File

@ -143,47 +143,47 @@ LibertyBuilder::makeTimingArcs(LibertyCell *cell,
true, false, attrs);
case TimingType::setup_rising:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::rise(), TimingRole::setup(),
RiseFall::rise(), TimingRole::setup(),
attrs);
case TimingType::setup_falling:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::fall(), TimingRole::setup(),
RiseFall::fall(), TimingRole::setup(),
attrs);
case TimingType::hold_rising:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::rise(), TimingRole::hold(),
RiseFall::rise(), TimingRole::hold(),
attrs);
case TimingType::hold_falling:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::fall(), TimingRole::hold(),
RiseFall::fall(), TimingRole::hold(),
attrs);
case TimingType::rising_edge:
return makeRegLatchArcs(cell, from_port, to_port, related_out,
TransRiseFall::rise(), attrs);
RiseFall::rise(), attrs);
case TimingType::falling_edge:
return makeRegLatchArcs(cell, from_port, to_port, related_out,
TransRiseFall::fall(), attrs);
RiseFall::fall(), attrs);
case TimingType::preset:
return makePresetClrArcs(cell, from_port, to_port, related_out,
TransRiseFall::rise(), attrs);
RiseFall::rise(), attrs);
case TimingType::clear:
return makePresetClrArcs(cell, from_port, to_port, related_out,
TransRiseFall::fall(), attrs);
RiseFall::fall(), attrs);
case TimingType::recovery_rising:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::rise(),TimingRole::recovery(),
RiseFall::rise(),TimingRole::recovery(),
attrs);
case TimingType::recovery_falling:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::fall(),TimingRole::recovery(),
RiseFall::fall(),TimingRole::recovery(),
attrs);
case TimingType::removal_rising:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::rise(), TimingRole::removal(),
RiseFall::rise(), TimingRole::removal(),
attrs);
case TimingType::removal_falling:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::fall(), TimingRole::removal(),
RiseFall::fall(), TimingRole::removal(),
attrs);
case TimingType::three_state_disable:
return makeTristateDisableArcs(cell, from_port, to_port, related_out,
@ -205,28 +205,28 @@ LibertyBuilder::makeTimingArcs(LibertyCell *cell,
true, false, attrs);
case TimingType::skew_falling:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::fall(), TimingRole::skew(),
RiseFall::fall(), TimingRole::skew(),
attrs);
case TimingType::skew_rising:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::rise(), TimingRole::skew(),
RiseFall::rise(), TimingRole::skew(),
attrs);
case TimingType::non_seq_setup_rising:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::rise(),
RiseFall::rise(),
TimingRole::nonSeqSetup(), attrs);
case TimingType::non_seq_setup_falling:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::fall(),
RiseFall::fall(),
TimingRole::nonSeqSetup(), attrs);
case TimingType::non_seq_hold_rising:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::rise(),
RiseFall::rise(),
TimingRole::nonSeqHold(),
attrs);
case TimingType::non_seq_hold_falling:
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
TransRiseFall::fall(),
RiseFall::fall(),
TimingRole::nonSeqHold(),
attrs);
case TimingType::min_pulse_width:
@ -270,34 +270,34 @@ LibertyBuilder::makeCombinationalArcs(LibertyCell *cell,
}
}
TimingModel *model;
TransRiseFall *to_tr;
RiseFall *to_rf;
switch (sense) {
case TimingSense::positive_unate:
if (to_rise) {
to_tr = TransRiseFall::rise();
model = attrs->model(to_tr);
to_rf = RiseFall::rise();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, TransRiseFall::rise(), to_tr, model);
makeTimingArc(arc_set, RiseFall::rise(), to_rf, model);
}
if (to_fall) {
to_tr = TransRiseFall::fall();
model = attrs->model(to_tr);
to_rf = RiseFall::fall();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, TransRiseFall::fall(), to_tr, model);
makeTimingArc(arc_set, RiseFall::fall(), to_rf, model);
}
break;
case TimingSense::negative_unate:
if (to_fall) {
to_tr = TransRiseFall::fall();
model = attrs->model(to_tr);
to_rf = RiseFall::fall();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, TransRiseFall::rise(), to_tr, model);
makeTimingArc(arc_set, RiseFall::rise(), to_rf, model);
}
if (to_rise) {
to_tr = TransRiseFall::rise();
model = attrs->model(to_tr);
to_rf = RiseFall::rise();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, TransRiseFall::fall(), to_tr, model);
makeTimingArc(arc_set, RiseFall::fall(), to_rf, model);
}
break;
case TimingSense::non_unate:
@ -307,19 +307,19 @@ LibertyBuilder::makeCombinationalArcs(LibertyCell *cell,
// as in fpga lut cells.
case TimingSense::none:
if (to_fall) {
to_tr = TransRiseFall::fall();
model = attrs->model(to_tr);
to_rf = RiseFall::fall();
model = attrs->model(to_rf);
if (model) {
makeTimingArc(arc_set, TransRiseFall::fall(), to_tr, model);
makeTimingArc(arc_set, TransRiseFall::rise(), to_tr, model);
makeTimingArc(arc_set, RiseFall::fall(), to_rf, model);
makeTimingArc(arc_set, RiseFall::rise(), to_rf, model);
}
}
if (to_rise) {
to_tr = TransRiseFall::rise();
model = attrs->model(to_tr);
to_rf = RiseFall::rise();
model = attrs->model(to_rf);
if (model) {
makeTimingArc(arc_set, TransRiseFall::rise(), to_tr, model);
makeTimingArc(arc_set, TransRiseFall::fall(), to_tr, model);
makeTimingArc(arc_set, RiseFall::rise(), to_rf, model);
makeTimingArc(arc_set, RiseFall::fall(), to_rf, model);
}
}
break;
@ -338,20 +338,20 @@ LibertyBuilder::makeLatchDtoQArcs(LibertyCell *cell,
related_out,
TimingRole::latchDtoQ(), attrs);
TimingModel *model;
TransRiseFall *to_tr = TransRiseFall::rise();
model = attrs->model(to_tr);
RiseFall *to_rf = RiseFall::rise();
model = attrs->model(to_rf);
TimingSense sense = attrs->timingSense();
if (model) {
TransRiseFall *from_tr = (sense == TimingSense::negative_unate) ?
to_tr->opposite() : to_tr;
makeTimingArc(arc_set, from_tr, to_tr, model);
RiseFall *from_rf = (sense == TimingSense::negative_unate) ?
to_rf->opposite() : to_rf;
makeTimingArc(arc_set, from_rf, to_rf, model);
}
to_tr = TransRiseFall::fall();
model = attrs->model(to_tr);
to_rf = RiseFall::fall();
model = attrs->model(to_rf);
if (model) {
TransRiseFall *from_tr = (sense == TimingSense::negative_unate) ?
to_tr->opposite() : to_tr;
makeTimingArc(arc_set, from_tr, to_tr, model);
RiseFall *from_rf = (sense == TimingSense::negative_unate) ?
to_rf->opposite() : to_rf;
makeTimingArc(arc_set, from_rf, to_rf, model);
}
return arc_set;
}
@ -361,7 +361,7 @@ LibertyBuilder::makeRegLatchArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
LibertyPort *related_out,
TransRiseFall *from_tr,
RiseFall *from_rf,
TimingArcAttrs *attrs)
{
FuncExpr *to_func = to_port->function();
@ -374,23 +374,23 @@ LibertyBuilder::makeRegLatchArcs(LibertyCell *cell,
TimingRole *role = seq->isRegister() ?
TimingRole::regClkToQ() : TimingRole::latchEnToQ();
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
from_tr, role, attrs);
from_rf, role, attrs);
}
else if (seq->isLatch()
&& seq->data()
&& seq->data()->hasPort(from_port))
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
from_tr, TimingRole::latchDtoQ(), attrs);
from_rf, TimingRole::latchDtoQ(), attrs);
else if ((seq->clear() && seq->clear()->hasPort(from_port))
|| (seq->preset() && seq->preset()->hasPort(from_port)))
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
from_tr, TimingRole::regSetClr(), attrs);
from_rf, TimingRole::regSetClr(), attrs);
}
}
// No associated ff/latch - assume register clk->q.
cell->setHasInferedRegTimingArcs(true);
return makeFromTransitionArcs(cell, from_port, to_port, related_out,
from_tr, TimingRole::regClkToQ(), attrs);
from_rf, TimingRole::regClkToQ(), attrs);
}
TimingArcSet *
@ -398,22 +398,22 @@ LibertyBuilder::makeFromTransitionArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
LibertyPort *related_out,
TransRiseFall *from_tr,
RiseFall *from_rf,
TimingRole *role,
TimingArcAttrs *attrs)
{
TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port,
related_out, role, attrs);
TimingModel *model;
TransRiseFall *to_tr;
to_tr = TransRiseFall::rise();
model = attrs->model(to_tr);
RiseFall *to_rf;
to_rf = RiseFall::rise();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, from_tr, to_tr, model);
to_tr = TransRiseFall::fall();
model = attrs->model(to_tr);
makeTimingArc(arc_set, from_rf, to_rf, model);
to_rf = RiseFall::fall();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, from_tr, to_tr, model);
makeTimingArc(arc_set, from_rf, to_rf, model);
return arc_set;
}
@ -422,26 +422,26 @@ LibertyBuilder::makePresetClrArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
LibertyPort *related_out,
TransRiseFall *to_tr,
RiseFall *to_rf,
TimingArcAttrs *attrs)
{
TimingArcSet *arc_set = nullptr;
TimingModel *model = attrs->model(to_tr);
TimingModel *model = attrs->model(to_rf);
if (model) {
arc_set = makeTimingArcSet(cell, from_port, to_port, related_out,
TimingRole::regSetClr(), attrs);
TransRiseFall *opp_tr = to_tr->opposite();
RiseFall *opp_rf = to_rf->opposite();
switch (attrs->timingSense()) {
case TimingSense::positive_unate:
makeTimingArc(arc_set, to_tr, to_tr, model);
makeTimingArc(arc_set, to_rf, to_rf, model);
break;
case TimingSense::negative_unate:
makeTimingArc(arc_set, opp_tr, to_tr, model);
makeTimingArc(arc_set, opp_rf, to_rf, model);
break;
case TimingSense::non_unate:
case TimingSense::unknown:
makeTimingArc(arc_set, to_tr, to_tr, model);
makeTimingArc(arc_set, opp_tr, to_tr, model);
makeTimingArc(arc_set, to_rf, to_rf, model);
makeTimingArc(arc_set, opp_rf, to_rf, model);
break;
case TimingSense::none:
break;
@ -469,32 +469,32 @@ LibertyBuilder::makeTristateEnableArcs(LibertyCell *cell,
if (sense == TimingSense::unknown && tristate_enable)
sense = tristate_enable->portTimingSense(from_port);
TimingModel *model;
TransRiseFall *to_tr;
RiseFall *to_rf;
switch (sense) {
case TimingSense::positive_unate:
if (to_rise) {
to_tr = TransRiseFall::rise();
model = attrs->model(to_tr);
to_rf = RiseFall::rise();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, Transition::rise(), Transition::trZ1(), model);
}
if (to_fall) {
to_tr = TransRiseFall::fall();
model = attrs->model(to_tr);
to_rf = RiseFall::fall();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, Transition::rise(), Transition::trZ0(), model);
}
break;
case TimingSense::negative_unate:
if (to_rise) {
to_tr = TransRiseFall::rise();
model = attrs->model(to_tr);
to_rf = RiseFall::rise();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, Transition::fall(), Transition::trZ1(), model);
}
if (to_fall) {
to_tr = TransRiseFall::fall();
model = attrs->model(to_tr);
to_rf = RiseFall::fall();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, Transition::fall(), Transition::trZ0(), model);
}
@ -502,16 +502,16 @@ LibertyBuilder::makeTristateEnableArcs(LibertyCell *cell,
case TimingSense::non_unate:
case TimingSense::unknown:
if (to_rise) {
to_tr = TransRiseFall::rise();
model = attrs->model(to_tr);
to_rf = RiseFall::rise();
model = attrs->model(to_rf);
if (model) {
makeTimingArc(arc_set, Transition::rise(), Transition::trZ1(), model);
makeTimingArc(arc_set, Transition::fall(), Transition::trZ1(), model);
}
}
if (to_fall) {
to_tr = TransRiseFall::fall();
model = attrs->model(to_tr);
to_rf = RiseFall::fall();
model = attrs->model(to_rf);
if (model) {
makeTimingArc(arc_set, Transition::rise(), Transition::trZ0(), model);
makeTimingArc(arc_set, Transition::fall(), Transition::trZ0(), model);
@ -542,32 +542,32 @@ LibertyBuilder::makeTristateDisableArcs(LibertyCell *cell,
if (sense == TimingSense::unknown && tristate_enable)
sense = timingSenseOpposite(tristate_enable->portTimingSense(from_port));
TimingModel *model;
TransRiseFall *to_tr;
RiseFall *to_rf;
switch (sense) {
case TimingSense::positive_unate:
if (to_rise) {
to_tr = TransRiseFall::rise();
model = attrs->model(to_tr);
to_rf = RiseFall::rise();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, Transition::rise(), Transition::tr0Z(), model);
}
if (to_fall) {
to_tr = TransRiseFall::fall();
model = attrs->model(to_tr);
to_rf = RiseFall::fall();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, Transition::rise(), Transition::tr1Z(), model);
}
break;
case TimingSense::negative_unate:
if (to_rise) {
to_tr = TransRiseFall::rise();
model = attrs->model(to_tr);
to_rf = RiseFall::rise();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, Transition::fall(), Transition::tr0Z(), model);
}
if (to_fall) {
to_tr = TransRiseFall::fall();
model = attrs->model(to_tr);
to_rf = RiseFall::fall();
model = attrs->model(to_rf);
if (model)
makeTimingArc(arc_set, Transition::fall(), Transition::tr1Z(), model);
}
@ -575,16 +575,16 @@ LibertyBuilder::makeTristateDisableArcs(LibertyCell *cell,
case TimingSense::non_unate:
case TimingSense::unknown:
if (to_rise) {
to_tr = TransRiseFall::rise();
model = attrs->model(to_tr);
to_rf = RiseFall::rise();
model = attrs->model(to_rf);
if (model) {
makeTimingArc(arc_set, Transition::fall(), Transition::tr0Z(), model);
makeTimingArc(arc_set, Transition::rise(), Transition::tr0Z(), model);
}
}
if (to_fall) {
to_tr = TransRiseFall::fall();
model = attrs->model(to_tr);
to_rf = RiseFall::fall();
model = attrs->model(to_rf);
if (model) {
makeTimingArc(arc_set, Transition::fall(), Transition::tr1Z(), model);
makeTimingArc(arc_set, Transition::rise(), Transition::tr1Z(), model);
@ -610,21 +610,21 @@ LibertyBuilder::makeTimingArcSet(LibertyCell *cell,
TimingArc *
LibertyBuilder::makeTimingArc(TimingArcSet *set,
TransRiseFall *from_tr,
TransRiseFall *to_tr,
RiseFall *from_rf,
RiseFall *to_rf,
TimingModel *model)
{
return new TimingArc(set, from_tr->asTransition(),
to_tr->asTransition(), model);
return new TimingArc(set, from_rf->asTransition(),
to_rf->asTransition(), model);
}
TimingArc *
LibertyBuilder::makeTimingArc(TimingArcSet *set,
Transition *from_tr,
Transition *to_tr,
Transition *from_rf,
Transition *to_rf,
TimingModel *model)
{
return new TimingArc(set, from_tr, to_tr, model);
return new TimingArc(set, from_rf, to_rf, model);
}
////////////////////////////////////////////////////////////////

14
liberty/LibertyBuilder.hh
View File

@ -83,12 +83,12 @@ protected:
TimingRole *role,
TimingArcAttrs *attrs);
virtual TimingArc *makeTimingArc(TimingArcSet *set,
Transition *from_tr,
Transition *to_tr,
Transition *from_rf,
Transition *to_rf,
TimingModel *model);
TimingArc *makeTimingArc(TimingArcSet *set,
TransRiseFall *from_tr,
TransRiseFall *to_tr,
RiseFall *from_rf,
RiseFall *to_rf,
TimingModel *model);
TimingArcSet *makeCombinationalArcs(LibertyCell *cell,
LibertyPort *from_port,
@ -106,20 +106,20 @@ protected:
LibertyPort *from_port,
LibertyPort *to_port,
LibertyPort *related_out,
TransRiseFall *from_tr,
RiseFall *from_rf,
TimingArcAttrs *attrs);
TimingArcSet *makeFromTransitionArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
LibertyPort *related_out,
TransRiseFall *from_tr,
RiseFall *from_rf,
TimingRole *role,
TimingArcAttrs *attrs);
TimingArcSet *makePresetClrArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
LibertyPort *related_out,
TransRiseFall *to_tr,
RiseFall *to_rf,
TimingArcAttrs *attrs);
TimingArcSet *makeTristateEnableArcs(LibertyCell *cell,
LibertyPort *from_port,

4
liberty/LibertyClass.hh
View File

@ -53,8 +53,8 @@ class FuncExpr;
class TimingModel;
class TimingRole;
class Transition;
class TransRiseFall;
class TransRiseFallBoth;
class RiseFall;
class RiseFallBoth;
class LibertyCellSequentialIterator;
typedef Vector<LibertyLibrary*> LibertyLibrarySeq;

376
liberty/LibertyReader.cc
View File

File diff suppressed because it is too large Load Diff

82
liberty/LibertyReaderPvt.hh
View File

@ -100,15 +100,15 @@ public:
virtual void visitDefaultIntrinsicRise(LibertyAttr *attr);
virtual void visitDefaultIntrinsicFall(LibertyAttr *attr);
virtual void visitDefaultIntrinsic(LibertyAttr *attr,
TransRiseFall *tr);
RiseFall *rf);
virtual void visitDefaultInoutPinRiseRes(LibertyAttr *attr);
virtual void visitDefaultInoutPinFallRes(LibertyAttr *attr);
virtual void visitDefaultInoutPinRes(LibertyAttr *attr,
TransRiseFall *tr);
RiseFall *rf);
virtual void visitDefaultOutputPinRiseRes(LibertyAttr *attr);
virtual void visitDefaultOutputPinFallRes(LibertyAttr *attr);
virtual void visitDefaultOutputPinRes(LibertyAttr *attr,
TransRiseFall *tr);
RiseFall *rf);
virtual void visitDefaultFanoutLoad(LibertyAttr *attr);
virtual void visitDefaultWireLoad(LibertyAttr *attr);
virtual void visitDefaultWireLoadMode(LibertyAttr *attr);
@ -117,19 +117,19 @@ public:
virtual void visitInputThresholdPctFall(LibertyAttr *attr);
virtual void visitInputThresholdPctRise(LibertyAttr *attr);
virtual void visitInputThresholdPct(LibertyAttr *attr,
TransRiseFall *tr);
RiseFall *rf);
virtual void visitOutputThresholdPctFall(LibertyAttr *attr);
virtual void visitOutputThresholdPctRise(LibertyAttr *attr);
virtual void visitOutputThresholdPct(LibertyAttr *attr,
TransRiseFall *tr);
RiseFall *rf);
virtual void visitSlewLowerThresholdPctFall(LibertyAttr *attr);
virtual void visitSlewLowerThresholdPctRise(LibertyAttr *attr);
virtual void visitSlewLowerThresholdPct(LibertyAttr *attr,
TransRiseFall *tr);
RiseFall *rf);
virtual void visitSlewUpperThresholdPctFall(LibertyAttr *attr);
virtual void visitSlewUpperThresholdPctRise(LibertyAttr *attr);
virtual void visitSlewUpperThresholdPct(LibertyAttr *attr,
TransRiseFall *tr);
RiseFall *rf);
virtual void visitSlewDerateFromLibrary(LibertyAttr *attr);
virtual void beginTableTemplateDelay(LibertyGroup *group);
@ -222,7 +222,7 @@ public:
virtual void visitMinPulseWidthLow(LibertyAttr *attr);
virtual void visitMinPulseWidthHigh(LibertyAttr *attr);
virtual void visitMinPulseWidth(LibertyAttr *attr,
TransRiseFall *tr);
RiseFall *rf);
virtual void visitPulseClock(LibertyAttr *attr);
virtual void visitClockGateClockPin(LibertyAttr *attr);
virtual void visitClockGateEnablePin(LibertyAttr *attr);
@ -300,11 +300,11 @@ public:
virtual void visitIntrinsicRise(LibertyAttr *attr);
virtual void visitIntrinsicFall(LibertyAttr *attr);
virtual void visitIntrinsic(LibertyAttr *attr,
TransRiseFall *tr);
RiseFall *rf);
virtual void visitRiseResistance(LibertyAttr *attr);
virtual void visitFallResistance(LibertyAttr *attr);
virtual void visitRiseFallResistance(LibertyAttr *attr,
TransRiseFall *tr);
RiseFall *rf);
virtual void visitValue(LibertyAttr *attr);
virtual void visitValues(LibertyAttr *attr);
virtual void beginCellRise(LibertyGroup *group);
@ -323,12 +323,12 @@ public:
virtual void beginTableModel(LibertyGroup *group,
TableTemplateType type,
TransRiseFall *tr,
RiseFall *rf,
float scale,
ScaleFactorType scale_factor_type);
virtual void endTableModel();
virtual void beginTimingTableModel(LibertyGroup *group,
TransRiseFall *tr,
RiseFall *rf,
ScaleFactorType scale_factor_type);
virtual void beginTable(LibertyGroup *group,
TableTemplateType type,
@ -517,10 +517,10 @@ protected:
const char *default_wireload_selection_;
ScaleFactors *scale_factors_;
ScaleFactors *save_scale_factors_;
bool have_input_threshold_[TransRiseFall::index_count];
bool have_output_threshold_[TransRiseFall::index_count];
bool have_slew_lower_threshold_[TransRiseFall::index_count];
bool have_slew_upper_threshold_[TransRiseFall::index_count];
bool have_input_threshold_[RiseFall::index_count];
bool have_output_threshold_[RiseFall::index_count];
bool have_slew_lower_threshold_[RiseFall::index_count];
bool have_slew_upper_threshold_[RiseFall::index_count];
TableTemplate *tbl_template_;
LibertyCell *cell_;
LibertyCell *save_cell_;
@ -549,9 +549,9 @@ protected:
InternalPowerGroup *internal_power_;
LeakagePowerGroup *leakage_power_;
LeakagePowerGroupSeq leakage_powers_;
TransRiseFall *tr_;
RiseFall *rf_;
OcvDerate *ocv_derate_;
TransRiseFallBoth *rf_type_;
RiseFallBoth *rf_type_;
EarlyLateAll *derate_type_;
EarlyLateAll *sigma_type_;
PathType path_type_;
@ -710,36 +710,36 @@ public:
virtual ~TimingGroup();
const char *relatedOutputPortName()const {return related_output_port_name_;}
void setRelatedOutputPortName(const char *name);
void intrinsic(TransRiseFall *tr,
void intrinsic(RiseFall *rf,
// Return values.
float &value,
bool &exists);
void setIntrinsic(TransRiseFall *tr,
void setIntrinsic(RiseFall *rf,
float value);
void resistance(TransRiseFall *tr,
void resistance(RiseFall *rf,
// Return values.
float &value,
bool &exists);
void setResistance(TransRiseFall *tr,
void setResistance(RiseFall *rf,
float value);
TableModel *cell(TransRiseFall *tr);
void setCell(TransRiseFall *tr,
TableModel *cell(RiseFall *rf);
void setCell(RiseFall *rf,
TableModel *model);
TableModel *constraint(TransRiseFall *tr);
void setConstraint(TransRiseFall *tr,
TableModel *constraint(RiseFall *rf);
void setConstraint(RiseFall *rf,
TableModel *model);
TableModel *transition(TransRiseFall *tr);
void setTransition(TransRiseFall *tr,
TableModel *transition(RiseFall *rf);
void setTransition(RiseFall *rf,
TableModel *model);
void makeTimingModels(LibertyLibrary *library,
LibertyReader *visitor);
void setDelaySigma(TransRiseFall *tr,
void setDelaySigma(RiseFall *rf,
EarlyLate *early_late,
TableModel *model);
void setSlewSigma(TransRiseFall *tr,
void setSlewSigma(RiseFall *rf,
EarlyLate *early_late,
TableModel *model);
void setConstraintSigma(TransRiseFall *tr,
void setConstraintSigma(RiseFall *rf,
EarlyLate *early_late,
TableModel *model);
@ -748,16 +748,16 @@ protected:
void makeTableModels(LibertyReader *visitor);
const char *related_output_port_name_;
float intrinsic_[TransRiseFall::index_count];
bool intrinsic_exists_[TransRiseFall::index_count];
float resistance_[TransRiseFall::index_count];
bool resistance_exists_[TransRiseFall::index_count];
TableModel *cell_[TransRiseFall::index_count];
TableModel *constraint_[TransRiseFall::index_count];
TableModel *constraint_sigma_[TransRiseFall::index_count][EarlyLate::index_count];
TableModel *transition_[TransRiseFall::index_count];
TableModel *delay_sigma_[TransRiseFall::index_count][EarlyLate::index_count];
TableModel *slew_sigma_[TransRiseFall::index_count][EarlyLate::index_count];
float intrinsic_[RiseFall::index_count];
bool intrinsic_exists_[RiseFall::index_count];
float resistance_[RiseFall::index_count];
bool resistance_exists_[RiseFall::index_count];
TableModel *cell_[RiseFall::index_count];
TableModel *constraint_[RiseFall::index_count];
TableModel *constraint_sigma_[RiseFall::index_count][EarlyLate::index_count];
TableModel *transition_[RiseFall::index_count];
TableModel *delay_sigma_[RiseFall::index_count][EarlyLate::index_count];
TableModel *slew_sigma_[RiseFall::index_count][EarlyLate::index_count];
private:
DISALLOW_COPY_AND_ASSIGN(TimingGroup);

4
liberty/TableModel.cc
View File

@ -551,10 +551,10 @@ CheckTableModel::checkAxis(TableAxis *axis)
TableModel::TableModel(Table *table,
ScaleFactorType scale_factor_type,
TransRiseFall *tr) :
RiseFall *rf) :
table_(table),
scale_factor_type_(int(scale_factor_type)),
tr_index_(tr->index()),
tr_index_(rf->index()),
is_scaled_(false)
{
}

4
liberty/TableModel.hh
View File

@ -197,7 +197,7 @@ class TableModel
public:
TableModel(Table *table,
ScaleFactorType scale_factor_type,
TransRiseFall *tr);
RiseFall *rf);
~TableModel();
void setScaleFactorType(ScaleFactorType type);
int order() const;
@ -242,7 +242,7 @@ protected:
Table *table_;
// ScaleFactorType gcc barfs if this is dcl'd.
unsigned scale_factor_type_:scale_factor_bits;
unsigned tr_index_:TransRiseFall::index_bit_count;
unsigned tr_index_:RiseFall::index_bit_count;
bool is_scaled_:1;
private:

78
liberty/TimingArc.cc
View File

@ -64,8 +64,8 @@ TimingArcAttrs::deleteContents()
stringDelete(sdf_cond_end_);
stringDelete(mode_name_);
stringDelete(mode_value_);
delete models_[TransRiseFall::riseIndex()];
delete models_[TransRiseFall::fallIndex()];
delete models_[RiseFall::riseIndex()];
delete models_[RiseFall::fallIndex()];
}
void
@ -116,16 +116,16 @@ TimingArcAttrs::setModeValue(const char *value)
}
TimingModel *
TimingArcAttrs::model(TransRiseFall *tr) const
TimingArcAttrs::model(RiseFall *rf) const
{
return models_[tr->index()];
return models_[rf->index()];
}
void
TimingArcAttrs::setModel(TransRiseFall *tr,
TimingArcAttrs::setModel(RiseFall *rf,
TimingModel *model)
{
models_[tr->index()] = model;
models_[rf->index()] = model;
}
void
@ -188,7 +188,7 @@ TimingArcSet::init(LibertyCell *cell)
if (cell)
index_ = cell->addTimingArcSet(this);
for (auto tr_index : TransRiseFall::rangeIndex()) {
for (auto tr_index : RiseFall::rangeIndex()) {
from_arc1_[tr_index] = nullptr;
from_arc2_[tr_index] = nullptr;
}
@ -223,11 +223,11 @@ TimingArcSet::addTimingArc(TimingArc *arc)
internalError("timing arc max index exceeded\n");
arcs_.push_back(arc);
int from_tr_index = arc->fromTrans()->asRiseFall()->index();
if (from_arc1_[from_tr_index] == nullptr)
from_arc1_[from_tr_index] = arc;
else if (from_arc2_[from_tr_index] == nullptr)
from_arc2_[from_tr_index] = arc;
int from_rf_index = arc->fromTrans()->asRiseFall()->index();
if (from_arc1_[from_rf_index] == nullptr)
from_arc1_[from_rf_index] = arc;
else if (from_arc2_[from_rf_index] == nullptr)
from_arc2_[from_rf_index] = arc;
return arc_index;
}
@ -243,13 +243,13 @@ TimingArcSet::deleteTimingArc(TimingArc *arc)
arcs_[arc->index()] = last_arc;
arcs_.pop_back();
}
int from_tr_index = arc->fromTrans()->asRiseFall()->index();
if (from_arc1_[from_tr_index] == arc) {
from_arc1_[from_tr_index] = from_arc2_[from_tr_index];
from_arc2_[from_tr_index] = nullptr;
int from_rf_index = arc->fromTrans()->asRiseFall()->index();
if (from_arc1_[from_rf_index] == arc) {
from_arc1_[from_rf_index] = from_arc2_[from_rf_index];
from_arc2_[from_rf_index] = nullptr;
}
else if (from_arc2_[from_tr_index] == arc)
from_arc2_[from_tr_index] = nullptr;
else if (from_arc2_[from_rf_index] == arc)
from_arc2_[from_rf_index] = nullptr;
delete arc;
}
@ -272,12 +272,12 @@ TimingArcSet::setIsCondDefault(bool is_default)
}
void
TimingArcSet::arcsFrom(const TransRiseFall *from_tr,
TimingArcSet::arcsFrom(const RiseFall *from_rf,
// Return values.
TimingArc *&arc1,
TimingArc *&arc2)
{
int tr_index = from_tr->index();
int tr_index = from_rf->index();
arc1 = from_arc1_[tr_index];
arc2 = from_arc2_[tr_index];
}
@ -293,15 +293,15 @@ TimingArcSet::sense() const
return TimingSense::non_unate;
}
TransRiseFall *
RiseFall *
TimingArcSet::isRisingFallingEdge() const
{
int arc_count = arcs_.size();
if (arc_count == 2) {
TransRiseFall *from_tr1 = arcs_[0]->fromTrans()->asRiseFall();
TransRiseFall *from_tr2 = arcs_[1]->fromTrans()->asRiseFall();
if (from_tr1 == from_tr2)
return from_tr1;
RiseFall *from_rf1 = arcs_[0]->fromTrans()->asRiseFall();
RiseFall *from_rf2 = arcs_[1]->fromTrans()->asRiseFall();
if (from_rf1 == from_rf2)
return from_rf1;
}
if (arcs_.size() == 1)
return arcs_[0]->fromTrans()->asRiseFall();
@ -463,9 +463,9 @@ timingArcsLess(const TimingArcSet *set1,
////////////////////////////////////////////////////////////////
int
TimingArcSet::wireArcIndex(const TransRiseFall *tr)
TimingArcSet::wireArcIndex(const RiseFall *rf)
{
return tr->index();
return rf->index();
}
void
@ -495,12 +495,12 @@ TimingArcSetArcIterator::TimingArcSetArcIterator(const TimingArcSet *set) :
////////////////////////////////////////////////////////////////
TimingArc::TimingArc(TimingArcSet *set,
Transition *from_tr,
Transition *to_tr,
Transition *from_rf,
Transition *to_rf,
TimingModel *model) :
set_(set),
from_tr_(from_tr),
to_tr_(to_tr),
from_rf_(from_rf),
to_rf_(to_rf),
model_(model),
scaled_models_(nullptr)
{
@ -576,15 +576,15 @@ TimingArc::setCornerArc(TimingArc *corner_arc,
TimingSense
TimingArc::sense() const
{
if ((from_tr_ == Transition::rise()
&& to_tr_ == Transition::rise())
|| (from_tr_ == Transition::fall()
&& to_tr_ == Transition::fall()))
if ((from_rf_ == Transition::rise()
&& to_rf_ == Transition::rise())
|| (from_rf_ == Transition::fall()
&& to_rf_ == Transition::fall()))
return TimingSense::positive_unate;
else if ((from_tr_ == Transition::rise()
&& to_tr_ == Transition::fall())
|| (from_tr_ == Transition::fall()
&& to_tr_ == Transition::rise()))
else if ((from_rf_ == Transition::rise()
&& to_rf_ == Transition::fall())
|| (from_rf_ == Transition::fall()
&& to_rf_ == Transition::rise()))
return TimingSense::negative_unate;
else
return TimingSense::non_unate;

28
liberty/TimingArc.hh
View File

@ -106,8 +106,8 @@ public:
void setModeName(const char *name);
const char *modeValue() const { return mode_value_; }
void setModeValue(const char *value);
TimingModel *model(TransRiseFall *tr) const;
void setModel(TransRiseFall *tr,
TimingModel *model(RiseFall *rf) const;
void setModel(RiseFall *rf,
TimingModel *model);
float ocvArcDepth() const { return ocv_arc_depth_; }
void setOcvArcDepth(float depth);
@ -122,7 +122,7 @@ protected:
const char *mode_name_;
const char *mode_value_;
float ocv_arc_depth_;
TimingModel *models_[TransRiseFall::index_count];
TimingModel *models_[RiseFall::index_count];
private:
DISALLOW_COPY_AND_ASSIGN(TimingArcAttrs);
@ -150,11 +150,11 @@ public:
TimingRole *role() const { return role_; };
TimingSense sense() const;
// Rise/fall if the arc set is rising_edge or falling_edge.
TransRiseFall *isRisingFallingEdge() const;
RiseFall *isRisingFallingEdge() const;
size_t arcCount() const { return arcs_.size(); }
TimingArcSeq &arcs() { return arcs_; }
// Return 1 or 2 arcs matching from transition.
void arcsFrom(const TransRiseFall *from_tr,
void arcsFrom(const RiseFall *from_rf,
// Return values.
TimingArc *&arc1,
TimingArc *&arc2);
@ -194,7 +194,7 @@ public:
// Psuedo definition for wire arcs.
static TimingArcSet *wireTimingArcSet() { return wire_timing_arc_set_; }
static int wireArcIndex(const TransRiseFall *tr);
static int wireArcIndex(const RiseFall *rf);
static int wireArcCount() { return 2; }
protected:
@ -215,8 +215,8 @@ protected:
float ocv_arc_depth_;
unsigned index_;
bool is_disabled_constraint_;
TimingArc *from_arc1_[TransRiseFall::index_count];
TimingArc *from_arc2_[TransRiseFall::index_count];
TimingArc *from_arc1_[RiseFall::index_count];
TimingArc *from_arc2_[RiseFall::index_count];
static TimingArcSet *wire_timing_arc_set_;
@ -239,14 +239,14 @@ class TimingArc
{
public:
TimingArc(TimingArcSet *set,
Transition *from_tr,
Transition *to_tr,
Transition *from_rf,
Transition *to_rf,
TimingModel *model);
~TimingArc();
LibertyPort *from() const { return set_->from(); }
LibertyPort *to() const { return set_->to(); }
Transition *fromTrans() const { return from_tr_; }
Transition *toTrans() const { return to_tr_; }
Transition *fromTrans() const { return from_rf_; }
Transition *toTrans() const { return to_rf_; }
TimingRole *role() const { return set_->role(); }
TimingArcSet *set() const { return set_; }
TimingSense sense() const;
@ -267,8 +267,8 @@ protected:
TimingModel *scaled_model);
TimingArcSet *set_;
Transition *from_tr_;
Transition *to_tr_;
Transition *from_rf_;
Transition *to_rf_;
unsigned index_;
TimingModel *model_;
ScaledTimingModelMap *scaled_models_;

136
liberty/Transition.cc
View File

@ -21,12 +21,12 @@ namespace sta {
using std::max;
TransRiseFall TransRiseFall::rise_("rise", "^", 0);
TransRiseFall TransRiseFall::fall_("fall", "v", 1);
const std::array<TransRiseFall*, 2> TransRiseFall::range_{&rise_, &fall_};
const std::array<int, 2> TransRiseFall::range_index_{rise_.index(), fall_.index()};
RiseFall RiseFall::rise_("rise", "^", 0);
RiseFall RiseFall::fall_("fall", "v", 1);
const std::array<RiseFall*, 2> RiseFall::range_{&rise_, &fall_};
const std::array<int, 2> RiseFall::range_index_{rise_.index(), fall_.index()};
TransRiseFall::TransRiseFall(const char *name,
RiseFall::RiseFall(const char *name,
const char *short_name,
int sdf_triple_index) :
name_(name),
@ -35,20 +35,20 @@ TransRiseFall::TransRiseFall(const char *name,
{
}
TransRiseFall::~TransRiseFall()
RiseFall::~RiseFall()
{
stringDelete(short_name_);
}
void
TransRiseFall::setShortName(const char *short_name)
RiseFall::setShortName(const char *short_name)
{
stringDelete(short_name_);
short_name_ = stringCopy(short_name);
}
TransRiseFall *
TransRiseFall::opposite() const
RiseFall *
RiseFall::opposite() const
{
if (this == &rise_)
return &fall_;
@ -56,8 +56,8 @@ TransRiseFall::opposite() const
return &rise_;
}
TransRiseFall *
TransRiseFall::find(const char *tr_str)
RiseFall *
RiseFall::find(const char *tr_str)
{
if (stringEq(tr_str, rise_.name()))
return &rise_;
@ -67,8 +67,8 @@ TransRiseFall::find(const char *tr_str)
return nullptr;
}
TransRiseFall *
TransRiseFall::find(int index)
RiseFall *
RiseFall::find(int index)
{
if (index == rise_.index())
return &rise_;
@ -76,26 +76,26 @@ TransRiseFall::find(int index)
return &fall_;
}
TransRiseFallBoth *
TransRiseFall::asRiseFallBoth()
RiseFallBoth *
RiseFall::asRiseFallBoth()
{
if (this == &rise_)
return TransRiseFallBoth::rise();
return RiseFallBoth::rise();
else
return TransRiseFallBoth::fall();
return RiseFallBoth::fall();
}
const TransRiseFallBoth *
TransRiseFall::asRiseFallBoth() const
const RiseFallBoth *
RiseFall::asRiseFallBoth() const
{
if (this == &rise_)
return TransRiseFallBoth::rise();
return RiseFallBoth::rise();
else
return TransRiseFallBoth::fall();
return RiseFallBoth::fall();
}
Transition *
TransRiseFall::asTransition() const
RiseFall::asTransition() const
{
if (this == &rise_)
return Transition::rise();
@ -105,26 +105,26 @@ TransRiseFall::asTransition() const
////////////////////////////////////////////////////////////////
TransRiseFallBoth TransRiseFallBoth::rise_("rise", "^", 0,
TransRiseFall::rise(),
{TransRiseFall::rise()},
{TransRiseFall::riseIndex()});
TransRiseFallBoth TransRiseFallBoth::fall_("fall", "v", 1,
TransRiseFall::fall(),
{TransRiseFall::fall()},
{TransRiseFall::fallIndex()});
TransRiseFallBoth TransRiseFallBoth::rise_fall_("rise_fall", "rf", 2,
RiseFallBoth RiseFallBoth::rise_("rise", "^", 0,
RiseFall::rise(),
{RiseFall::rise()},
{RiseFall::riseIndex()});
RiseFallBoth RiseFallBoth::fall_("fall", "v", 1,
RiseFall::fall(),
{RiseFall::fall()},
{RiseFall::fallIndex()});
RiseFallBoth RiseFallBoth::rise_fall_("rise_fall", "rf", 2,
nullptr,
{TransRiseFall::rise(),
TransRiseFall::fall()},
{TransRiseFall::riseIndex(),
TransRiseFall::fallIndex()});
{RiseFall::rise(),
RiseFall::fall()},
{RiseFall::riseIndex(),
RiseFall::fallIndex()});
TransRiseFallBoth::TransRiseFallBoth(const char *name,
RiseFallBoth::RiseFallBoth(const char *name,
const char *short_name,
int sdf_triple_index,
TransRiseFall *as_rise_fall,
std::vector<TransRiseFall*> range,
RiseFall *as_rise_fall,
std::vector<RiseFall*> range,
std::vector<int> range_index) :
name_(name),
short_name_(stringCopy(short_name)),
@ -135,13 +135,13 @@ TransRiseFallBoth::TransRiseFallBoth(const char *name,
{
}
TransRiseFallBoth::~TransRiseFallBoth()
RiseFallBoth::~RiseFallBoth()
{
stringDelete(short_name_);
}
TransRiseFallBoth *
TransRiseFallBoth::find(const char *tr_str)
RiseFallBoth *
RiseFallBoth::find(const char *tr_str)
{
if (stringEq(tr_str, rise_.name()))
return &rise_;
@ -154,14 +154,14 @@ TransRiseFallBoth::find(const char *tr_str)
}
bool
TransRiseFallBoth::matches(const TransRiseFall *tr) const
RiseFallBoth::matches(const RiseFall *rf) const
{
return this == &rise_fall_
|| as_rise_fall_ == tr;
|| as_rise_fall_ == rf;
}
bool
TransRiseFallBoth::matches(const Transition *tr) const
RiseFallBoth::matches(const Transition *tr) const
{
return this == &rise_fall_
|| (this == &rise_
@ -171,7 +171,7 @@ TransRiseFallBoth::matches(const Transition *tr) const
}
void
TransRiseFallBoth::setShortName(const char *short_name)
RiseFallBoth::setShortName(const char *short_name)
{
stringDelete(short_name_);
short_name_ = stringCopy(short_name);
@ -183,23 +183,23 @@ TransitionMap Transition::transition_map_;
int Transition::max_index_ = 0;
// Sdf triple order defined on Sdf 3.0 spec, pg 3-17.
Transition Transition::rise_{ "^", "01", TransRiseFall::rise(), 0};
Transition Transition::fall_ { "v", "10", TransRiseFall::fall(), 1};
Transition Transition::tr_0Z_{"0Z", "0Z", TransRiseFall::rise(), 2};
Transition Transition::tr_Z1_{"Z1", "Z1", TransRiseFall::rise(), 3};
Transition Transition::tr_1Z_{"1Z", "1Z", TransRiseFall::fall(), 4};
Transition Transition::tr_Z0_{"Z0", "Z0", TransRiseFall::fall(), 5};
Transition Transition::tr_0X_{"0X", "0X", TransRiseFall::rise(), 6};
Transition Transition::tr_X1_{"X1", "X1", TransRiseFall::rise(), 7};
Transition Transition::tr_1X_{"1X", "1X", TransRiseFall::fall(), 8};
Transition Transition::tr_X0_{"X0", "X0", TransRiseFall::fall(), 9};
Transition Transition::rise_{ "^", "01", RiseFall::rise(), 0};
Transition Transition::fall_ { "v", "10", RiseFall::fall(), 1};
Transition Transition::tr_0Z_{"0Z", "0Z", RiseFall::rise(), 2};
Transition Transition::tr_Z1_{"Z1", "Z1", RiseFall::rise(), 3};
Transition Transition::tr_1Z_{"1Z", "1Z", RiseFall::fall(), 4};
Transition Transition::tr_Z0_{"Z0", "Z0", RiseFall::fall(), 5};
Transition Transition::tr_0X_{"0X", "0X", RiseFall::rise(), 6};
Transition Transition::tr_X1_{"X1", "X1", RiseFall::rise(), 7};
Transition Transition::tr_1X_{"1X", "1X", RiseFall::fall(), 8};
Transition Transition::tr_X0_{"X0", "X0", RiseFall::fall(), 9};
Transition Transition::tr_XZ_{"XZ", "XZ", nullptr, 10};
Transition Transition::tr_ZX_{"ZX", "ZX", nullptr, 11};
Transition Transition::rise_fall_{"*", "**", nullptr, -1};
Transition::Transition(const char *name,
const char *init_final,
TransRiseFall *as_rise_fall,
RiseFall *as_rise_fall,
int sdf_triple_index) :
name_(stringCopy(name)),
init_final_(init_final),
@ -228,10 +228,10 @@ Transition::find(const char *tr_str)
return transition_map_.findKey(tr_str);
}
const TransRiseFallBoth *
const RiseFallBoth *
Transition::asRiseFallBoth() const
{
return reinterpret_cast<const TransRiseFallBoth*>(as_rise_fall_);
return reinterpret_cast<const RiseFallBoth*>(as_rise_fall_);
}
void
@ -243,35 +243,35 @@ Transition::setName(const char *name)
////////////////////////////////////////////////////////////////
TransRiseFallIterator::TransRiseFallIterator(const TransRiseFallBoth *tr)
RiseFallIterator::RiseFallIterator(const RiseFallBoth *rf)
{
if (tr == TransRiseFallBoth::riseFall()) {
if (rf == RiseFallBoth::riseFall()) {
index_ = 0;
index_max_ = TransRiseFall::index_max;
index_max_ = RiseFall::index_max;
}
else {
index_ = tr->asRiseFall()->index();
index_ = rf->asRiseFall()->index();
index_max_ = index_;
}
}
void
TransRiseFallIterator::init()
RiseFallIterator::init()
{
index_ = 0;
index_max_ = TransRiseFall::index_max;
index_max_ = RiseFall::index_max;
}
bool
TransRiseFallIterator::hasNext()
RiseFallIterator::hasNext()
{
return index_ <= index_max_;
}
TransRiseFall *
TransRiseFallIterator::next()
RiseFall *
RiseFallIterator::next()
{
return (index_++ == 0) ? TransRiseFall::rise() : TransRiseFall::fall();
return (index_++ == 0) ? RiseFall::rise() : RiseFall::fall();
}
} // namespace

94
liberty/Transition.hh
View File

@ -27,18 +27,18 @@
namespace sta {
class Transition;
class TransRiseFall;
class TransRiseFallBoth;
class RiseFall;
class RiseFallBoth;
typedef Map<const char*, Transition*, CharPtrLess> TransitionMap;
// Rise/fall transition.
class TransRiseFall
class RiseFall
{
public:
// Singleton accessors.
static TransRiseFall *rise() { return &rise_; }
static TransRiseFall *fall() { return &fall_; }
static RiseFall *rise() { return &rise_; }
static RiseFall *fall() { return &fall_; }
static int riseIndex() { return rise_.sdf_triple_index_; }
static int fallIndex() { return fall_.sdf_triple_index_; }
const char *asString() const { return short_name_; }
@ -46,63 +46,63 @@ public:
const char *shortName() const { return short_name_; }
void setShortName(const char *short_name);
int index() const { return sdf_triple_index_; }
TransRiseFallBoth *asRiseFallBoth();
const TransRiseFallBoth *asRiseFallBoth() const;
RiseFallBoth *asRiseFallBoth();
const RiseFallBoth *asRiseFallBoth() const;
Transition *asTransition() const;
// Find transition corresponding to tr_str.
static TransRiseFall *find(const char *tr_str);
static RiseFall *find(const char *tr_str);
// Find transition from index.
static TransRiseFall *find(int index);
TransRiseFall *opposite() const;
static RiseFall *find(int index);
RiseFall *opposite() const;
// for range support.
// for (auto tr : TransRiseFall::range()) {}
static const std::array<TransRiseFall*, 2> &range() { return range_; }
// for (auto tr_index : TransRiseFall::rangeIndex()) {}
// for (auto tr : RiseFall::range()) {}
static const std::array<RiseFall*, 2> &range() { return range_; }
// for (auto tr_index : RiseFall::rangeIndex()) {}
static const std::array<int, 2> &rangeIndex() { return range_index_; }
static const int index_count = 2;
static const int index_max = (index_count - 1);
static const int index_bit_count = 1;
protected:
TransRiseFall(const char *name,
RiseFall(const char *name,
const char *short_name,
int sdf_triple_index);
~TransRiseFall();
~RiseFall();
const char *name_;
const char *short_name_;
const int sdf_triple_index_;
static TransRiseFall rise_;
static TransRiseFall fall_;
static const std::array<TransRiseFall*, 2> range_;
static RiseFall rise_;
static RiseFall fall_;
static const std::array<RiseFall*, 2> range_;
static const std::array<int, 2> range_index_;
private:
DISALLOW_COPY_AND_ASSIGN(TransRiseFall);
DISALLOW_COPY_AND_ASSIGN(RiseFall);
};
// Rise/fall/risefall transition.
class TransRiseFallBoth
class RiseFallBoth
{
public:
// Singleton accessors.
static TransRiseFallBoth *rise() { return &rise_; }
static TransRiseFallBoth *fall() { return &fall_; }
static TransRiseFallBoth *riseFall() { return &rise_fall_; }
static RiseFallBoth *rise() { return &rise_; }
static RiseFallBoth *fall() { return &fall_; }
static RiseFallBoth *riseFall() { return &rise_fall_; }
const char *asString() const { return short_name_; }
const char *name() const { return name_; }
const char *shortName() const { return short_name_; }
void setShortName(const char *short_name);
int index() const { return sdf_triple_index_; }
bool matches(const TransRiseFall *tr) const;
bool matches(const RiseFall *rf) const;
bool matches(const Transition *tr) const;
TransRiseFall *asRiseFall() const { return as_rise_fall_; }
RiseFall *asRiseFall() const { return as_rise_fall_; }
// Find transition corresponding to string.
static TransRiseFallBoth *find(const char *tr_str);
static RiseFallBoth *find(const char *tr_str);
// for (auto tr : min_max->range()) {}
const std::vector<TransRiseFall*> &range() const { return range_; }
const std::vector<RiseFall*> &range() const { return range_; }
// for (auto tr_index : min_max->rangeIndex()) {}
const std::vector<int> &rangeIndex() const { return range_index_; }
@ -111,27 +111,27 @@ public:
static const int index_bit_count = 2;
protected:
TransRiseFallBoth(const char *name,
RiseFallBoth(const char *name,
const char *short_name,
int sdf_triple_index,
TransRiseFall *as_rise_fall,
std::vector<TransRiseFall*> range,
RiseFall *as_rise_fall,
std::vector<RiseFall*> range,
std::vector<int> range_index);
~TransRiseFallBoth();
~RiseFallBoth();
const char *name_;
const char *short_name_;
const int sdf_triple_index_;
TransRiseFall *as_rise_fall_;
const std::vector<TransRiseFall*> range_;
RiseFall *as_rise_fall_;
const std::vector<RiseFall*> range_;
const std::vector<int> range_index_;
static TransRiseFallBoth rise_;
static TransRiseFallBoth fall_;
static TransRiseFallBoth rise_fall_;
static RiseFallBoth rise_;
static RiseFallBoth fall_;
static RiseFallBoth rise_fall_;
private:
DISALLOW_COPY_AND_ASSIGN(TransRiseFallBoth);
DISALLOW_COPY_AND_ASSIGN(RiseFallBoth);
};
// General SDF transition.
@ -159,8 +159,8 @@ public:
const char *asInitFinalString() const { return init_final_; }
int sdfTripleIndex() const { return sdf_triple_index_; }
int index() const { return sdf_triple_index_; }
TransRiseFall *asRiseFall() const { return as_rise_fall_; }
const TransRiseFallBoth *asRiseFallBoth() const;
RiseFall *asRiseFall() const { return as_rise_fall_; }
const RiseFallBoth *asRiseFallBoth() const;
bool matches(const Transition *tr) const;
// Find transition corresponding to string.
static Transition *find(const char *tr_str);
@ -169,13 +169,13 @@ public:
private:
Transition(const char *name,
const char *init_final,
TransRiseFall *as_rise_fall,
RiseFall *as_rise_fall,
int sdf_triple_index);
~Transition();
const char *name_;
const char *init_final_;
TransRiseFall *as_rise_fall_;
RiseFall *as_rise_fall_;
const int sdf_triple_index_;
static Transition rise_;
@ -203,18 +203,18 @@ private:
};
// Obsolete. Use range iteration instead.
// for (auto tr : TransRiseFall::range()) {}
class TransRiseFallIterator : public Iterator<TransRiseFall*>
// for (auto tr : RiseFall::range()) {}
class RiseFallIterator : public Iterator<RiseFall*>
{
public:
TransRiseFallIterator() : index_(0), index_max_(TransRiseFall::index_max) {}
explicit TransRiseFallIterator(const TransRiseFallBoth *tr);
RiseFallIterator() : index_(0), index_max_(RiseFall::index_max) {}
explicit RiseFallIterator(const RiseFallBoth *rf);
void init();
virtual bool hasNext();
virtual TransRiseFall *next();
virtual RiseFall *next();
private:
DISALLOW_COPY_AND_ASSIGN(TransRiseFallIterator);
DISALLOW_COPY_AND_ASSIGN(RiseFallIterator);
int index_;
int index_max_;

88
parasitics/ConcreteParasitics.cc
View File

@ -290,7 +290,7 @@ ConcretePiElmoreEstimated::ConcretePiElmoreEstimated(float c2,
float elmore_res,
float elmore_cap,
bool elmore_use_load_cap,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op,
const Corner *corner,
const MinMax *min_max,
@ -299,7 +299,7 @@ ConcretePiElmoreEstimated::ConcretePiElmoreEstimated(float c2,
elmore_res_(elmore_res),
elmore_cap_(elmore_cap),
elmore_use_load_cap_(elmore_use_load_cap),
tr_(tr),
rf_(rf),
op_cond_(op),
corner_(corner),
min_max_(min_max),
@ -328,7 +328,7 @@ ConcretePiElmoreEstimated::findElmore(const Pin *load_pin,
{
float load_cap = 0.0;
if (elmore_use_load_cap_)
load_cap = sdc_->pinCapacitance(load_pin, tr_, op_cond_,
load_cap = sdc_->pinCapacitance(load_pin, rf_, op_cond_,
corner_, min_max_);
elmore = elmore_res_ * (elmore_cap_ + load_cap);
exists = true;
@ -875,20 +875,20 @@ ConcreteParasitics::clear()
int
ConcreteParasitics::parasiticAnalysisPtIndex(const ParasiticAnalysisPt *ap,
const TransRiseFall *tr) const
const RiseFall *rf) const
{
return ap->index() * TransRiseFall::index_count + tr->index();
return ap->index() * RiseFall::index_count + rf->index();
}
void
ConcreteParasitics::deleteParasitics()
{
int ap_count = corners_->parasiticAnalysisPtCount();
int ap_tr_count = ap_count * TransRiseFall::index_count;
int ap_rf_count = ap_count * RiseFall::index_count;
for (auto drvr_parasitics : drvr_parasitic_map_) {
ConcreteParasitic **parasitics = drvr_parasitics.second;
if (parasitics) {
for (int i = 0; i < ap_tr_count; i++)
for (int i = 0; i < ap_rf_count; i++)
delete parasitics[i];
delete [] parasitics;
}
@ -912,10 +912,10 @@ ConcreteParasitics::deleteParasitics(const Pin *drvr_pin,
{
ConcreteParasitic **parasitics = drvr_parasitic_map_[drvr_pin];
if (parasitics) {
for (auto tr : TransRiseFall::range()) {
int ap_tr_index = parasiticAnalysisPtIndex(ap, tr);
delete parasitics[ap_tr_index];
parasitics[ap_tr_index] = nullptr;
for (auto tr : RiseFall::range()) {
int ap_rf_index = parasiticAnalysisPtIndex(ap, tr);
delete parasitics[ap_rf_index];
parasitics[ap_rf_index] = nullptr;
}
}
}
@ -1017,8 +1017,8 @@ ConcreteParasitics::deleteDrvrReducedParasitics(const Pin *drvr_pin)
ConcreteParasitic **parasitics = drvr_parasitic_map_[drvr_pin];
if (parasitics) {
int ap_count = corners_->parasiticAnalysisPtCount();
int ap_tr_count = ap_count * TransRiseFall::index_count;
for (int i = 0; i < ap_tr_count; i++)
int ap_rf_count = ap_count * RiseFall::index_count;
for (int i = 0; i < ap_rf_count; i++)
delete parasitics[i];
delete [] parasitics;
}
@ -1036,18 +1036,18 @@ ConcreteParasitics::isPiElmore(Parasitic *parasitic) const
Parasitic *
ConcreteParasitics::findPiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap) const
{
if (!drvr_parasitic_map_.empty()) {
int ap_tr_index = parasiticAnalysisPtIndex(ap, tr);
int ap_rf_index = parasiticAnalysisPtIndex(ap, rf);
UniqueLock lock(lock_);
ConcreteParasitic **parasitics = drvr_parasitic_map_.findKey(drvr_pin);
if (parasitics) {
ConcreteParasitic *parasitic = parasitics[ap_tr_index];
if (parasitic == nullptr && tr == TransRiseFall::fall()) {
ap_tr_index = parasiticAnalysisPtIndex(ap, TransRiseFall::rise());
parasitic = parasitics[ap_tr_index];
ConcreteParasitic *parasitic = parasitics[ap_rf_index];
if (parasitic == nullptr && rf == RiseFall::fall()) {
ap_rf_index = parasiticAnalysisPtIndex(ap, RiseFall::rise());
parasitic = parasitics[ap_rf_index];
}
if (parasitic && parasitic->isPiElmore())
return parasitic;
@ -1058,7 +1058,7 @@ ConcreteParasitics::findPiElmore(const Pin *drvr_pin,
Parasitic *
ConcreteParasitics::makePiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap,
float c2,
float rpi,
@ -1068,14 +1068,14 @@ ConcreteParasitics::makePiElmore(const Pin *drvr_pin,
ConcreteParasitic **parasitics = drvr_parasitic_map_.findKey(drvr_pin);
if (parasitics == nullptr) {
int ap_count = corners_->parasiticAnalysisPtCount();
int ap_tr_count = ap_count * TransRiseFall::index_count;
parasitics = new ConcreteParasitic*[ap_tr_count];
for (int i = 0; i < ap_tr_count; i++)
int ap_rf_count = ap_count * RiseFall::index_count;
parasitics = new ConcreteParasitic*[ap_rf_count];
for (int i = 0; i < ap_rf_count; i++)
parasitics[i] = nullptr;
drvr_parasitic_map_[drvr_pin] = parasitics;
}
int ap_tr_index = parasiticAnalysisPtIndex(ap, tr);
ConcreteParasitic *parasitic = parasitics[ap_tr_index];
int ap_rf_index = parasiticAnalysisPtIndex(ap, rf);
ConcreteParasitic *parasitic = parasitics[ap_rf_index];
ConcretePiElmore *pi_elmore = nullptr;
if (parasitic) {
if (parasitic->isPiElmore()) {
@ -1085,12 +1085,12 @@ ConcreteParasitics::makePiElmore(const Pin *drvr_pin,
else {
delete parasitic;
pi_elmore = new ConcretePiElmore(c2, rpi, c1);
parasitics[ap_tr_index] = pi_elmore;
parasitics[ap_rf_index] = pi_elmore;
}
}
else {
pi_elmore = new ConcretePiElmore(c2, rpi, c1);
parasitics[ap_tr_index] = pi_elmore;
parasitics[ap_rf_index] = pi_elmore;
}
return pi_elmore;
}
@ -1156,18 +1156,18 @@ ConcreteParasitics::isPiPoleResidue(Parasitic* parasitic) const
Parasitic *
ConcreteParasitics::findPiPoleResidue(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap) const
{
if (!drvr_parasitic_map_.empty()) {
int ap_tr_index = parasiticAnalysisPtIndex(ap, tr);
int ap_rf_index = parasiticAnalysisPtIndex(ap, rf);
UniqueLock lock(lock_);
ConcreteParasitic **parasitics = drvr_parasitic_map_.findKey(drvr_pin);
if (parasitics) {
ConcreteParasitic *parasitic = parasitics[ap_tr_index];
if (parasitic == nullptr && tr == TransRiseFall::fall()) {
ap_tr_index = parasiticAnalysisPtIndex(ap, TransRiseFall::rise());
parasitic = parasitics[ap_tr_index];
ConcreteParasitic *parasitic = parasitics[ap_rf_index];
if (parasitic == nullptr && rf == RiseFall::fall()) {
ap_rf_index = parasiticAnalysisPtIndex(ap, RiseFall::rise());
parasitic = parasitics[ap_rf_index];
}
if (parasitic->isPiPoleResidue())
return parasitic;
@ -1178,7 +1178,7 @@ ConcreteParasitics::findPiPoleResidue(const Pin *drvr_pin,
Parasitic *
ConcreteParasitics::makePiPoleResidue(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap,
float c2,
float rpi,
@ -1188,14 +1188,14 @@ ConcreteParasitics::makePiPoleResidue(const Pin *drvr_pin,
ConcreteParasitic **parasitics = drvr_parasitic_map_.findKey(drvr_pin);
if (parasitics == nullptr) {
int ap_count = corners_->parasiticAnalysisPtCount();
int ap_tr_count = ap_count * TransRiseFall::index_count;
parasitics = new ConcreteParasitic*[ap_tr_count];
for (int i = 0; i < ap_tr_count; i++)
int ap_rf_count = ap_count * RiseFall::index_count;
parasitics = new ConcreteParasitic*[ap_rf_count];
for (int i = 0; i < ap_rf_count; i++)
parasitics[i] = nullptr;
drvr_parasitic_map_[drvr_pin] = parasitics;
}
int ap_tr_index = parasiticAnalysisPtIndex(ap, tr);
ConcreteParasitic *parasitic = parasitics[ap_tr_index];
int ap_rf_index = parasiticAnalysisPtIndex(ap, rf);
ConcreteParasitic *parasitic = parasitics[ap_rf_index];
ConcretePiPoleResidue *pi_pole_residue = nullptr;
if (parasitic) {
if (parasitic->isPiElmore()) {
@ -1205,12 +1205,12 @@ ConcreteParasitics::makePiPoleResidue(const Pin *drvr_pin,
else {
delete parasitic;
pi_pole_residue = new ConcretePiPoleResidue(c2, rpi, c1);
parasitics[ap_tr_index] = pi_pole_residue;
parasitics[ap_rf_index] = pi_pole_residue;
}
}
else {
pi_pole_residue = new ConcretePiPoleResidue(c2, rpi, c1);
parasitics[ap_tr_index] = pi_pole_residue;
parasitics[ap_rf_index] = pi_pole_residue;
}
return pi_pole_residue;
}
@ -1652,7 +1652,7 @@ ConcreteParasitics::reduceToPiPoleResidue2(Parasitic *parasitic,
Parasitic *
ConcreteParasitics::estimatePiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const Wireload *wireload,
float fanout,
float net_pin_cap,
@ -1663,14 +1663,14 @@ ConcreteParasitics::estimatePiElmore(const Pin *drvr_pin,
{
float c2, rpi, c1, elmore_res, elmore_cap;
bool elmore_use_load_cap;
estimatePiElmore(drvr_pin, tr, wireload, fanout, net_pin_cap,
estimatePiElmore(drvr_pin, rf, wireload, fanout, net_pin_cap,
op_cond, corner, min_max, this,
c2, rpi, c1,
elmore_res, elmore_cap, elmore_use_load_cap);
return new ConcretePiElmoreEstimated(c2, rpi, c1, elmore_res, elmore_cap,
elmore_use_load_cap,
tr, op_cond, corner, min_max,
rf, op_cond, corner, min_max,
sdc_);
}

12
parasitics/ConcreteParasitics.hh
View File

@ -61,10 +61,10 @@ public:
virtual bool isPiElmore(Parasitic *parasitic) const;
virtual Parasitic *findPiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap) const;
virtual Parasitic *makePiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap,
float c2, float rpi, float c1);
@ -80,12 +80,12 @@ public:
virtual bool isPiPoleResidue(Parasitic* parasitic) const;
virtual Parasitic *findPiPoleResidue(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap) const;
virtual Parasitic *findPoleResidue(const Parasitic *parasitic,
const Pin *load_pin) const;
virtual Parasitic *makePiPoleResidue(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap,
float c2, float rpi, float c1);
virtual void setPoleResidue(Parasitic *parasitic, const Pin *load_pin,
@ -150,7 +150,7 @@ public:
ParasiticNode *node) const;
virtual Parasitic *estimatePiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const Wireload *wireload,
float fanout,
float net_pin_cap,
@ -196,7 +196,7 @@ public:
protected:
int parasiticAnalysisPtIndex(const ParasiticAnalysisPt *ap,
const TransRiseFall *tr) const;
const RiseFall *rf) const;
Parasitic *ensureRspf(const Pin *drvr_pin);
void makeAnalysisPtAfter();
void deleteReducedParasitics(const Pin *pin);

4
parasitics/ConcreteParasiticsPvt.hh
View File

@ -157,7 +157,7 @@ public:
float elmore_res,
float elmore_cap,
bool elmore_use_load_cap,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *min_max,
@ -174,7 +174,7 @@ private:
float elmore_res_;
float elmore_cap_;
bool elmore_use_load_cap_;
const TransRiseFall *tr_;
const RiseFall *rf_;
const OperatingConditions *op_cond_;
const Corner *corner_;
const MinMax *min_max_;

22
parasitics/EstimateParasitics.cc
View File

@ -28,7 +28,7 @@ namespace sta {
// loads when driven by a different pin.
void
EstimateParasitics::estimatePiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const Wireload *wireload,
float fanout,
float net_pin_cap,
@ -52,7 +52,7 @@ EstimateParasitics::estimatePiElmore(const Pin *drvr_pin,
switch (tree) {
case WireloadTree::worst_case:
estimatePiElmoreWorst(drvr_pin, wireload_cap, wireload_res,
fanout, net_pin_cap, tr, op_cond, corner,
fanout, net_pin_cap, rf, op_cond, corner,
min_max, sta,
c2, rpi, c1, elmore_res,
elmore_cap, elmore_use_load_cap);
@ -60,13 +60,13 @@ EstimateParasitics::estimatePiElmore(const Pin *drvr_pin,
case WireloadTree::balanced:
case WireloadTree::unknown:
estimatePiElmoreBalanced(drvr_pin, wireload_cap, wireload_res,
fanout, net_pin_cap, tr, op_cond,
fanout, net_pin_cap, rf, op_cond,
corner, min_max,sta,
c2, rpi, c1, elmore_res,
elmore_cap, elmore_use_load_cap);
break;
case WireloadTree::best_case:
estimatePiElmoreBest(drvr_pin, wireload_cap, net_pin_cap, tr,
estimatePiElmoreBest(drvr_pin, wireload_cap, net_pin_cap, rf,
op_cond, corner, min_max,
c2, rpi, c1, elmore_res, elmore_cap,
elmore_use_load_cap);
@ -79,7 +79,7 @@ void
EstimateParasitics::estimatePiElmoreBest(const Pin *,
float wireload_cap,
float net_pin_cap,
const TransRiseFall *,
const RiseFall *,
const OperatingConditions *,
const Corner *,
const MinMax *,
@ -106,7 +106,7 @@ EstimateParasitics::estimatePiElmoreWorst(const Pin *drvr_pin,
float wireload_res,
float,
float net_pin_cap,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *min_max,
@ -120,7 +120,7 @@ EstimateParasitics::estimatePiElmoreWorst(const Pin *drvr_pin,
{
Sdc *sdc = sta->sdc();
float drvr_pin_cap = 0.0;
drvr_pin_cap = sdc->pinCapacitance(drvr_pin, tr, op_cond, corner, min_max);
drvr_pin_cap = sdc->pinCapacitance(drvr_pin, rf, op_cond, corner, min_max);
c2 = drvr_pin_cap;
rpi = wireload_res;
c1 = net_pin_cap - drvr_pin_cap + wireload_cap;
@ -138,7 +138,7 @@ EstimateParasitics::estimatePiElmoreBalanced(const Pin *drvr_pin,
float wireload_res,
float fanout,
float net_pin_cap,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *min_max,
@ -168,7 +168,7 @@ EstimateParasitics::estimatePiElmoreBalanced(const Pin *drvr_pin,
double y1 = 0.0;
double y2 = 0.0;
double y3 = 0.0;
y1 = sdc->pinCapacitance(drvr_pin, tr, op_cond, corner, min_max);
y1 = sdc->pinCapacitance(drvr_pin, rf, op_cond, corner, min_max);
PinConnectedPinIterator *load_iter =
network->connectedPinIterator(drvr_pin);
while (load_iter->hasNext()) {
@ -178,10 +178,10 @@ EstimateParasitics::estimatePiElmoreBalanced(const Pin *drvr_pin,
Port *port = network->port(load_pin);
double load_cap = 0.0;
if (network->isLeaf(load_pin))
load_cap = sdc->pinCapacitance(load_pin, tr, op_cond,
load_cap = sdc->pinCapacitance(load_pin, rf, op_cond,
corner, min_max);
else if (network->isTopLevelPort(load_pin))
load_cap = sdc->portExtCap(port, tr, min_max);
load_cap = sdc->portExtCap(port, rf, min_max);
else
internalError("load pin not leaf or top level");
double cap = load_cap + cap_fanout;

8
parasitics/EstimateParasitics.hh
View File

@ -31,7 +31,7 @@ public:
protected:
// Helper function for wireload estimation.
void estimatePiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const Wireload *wireload,
float fanout,
float net_pin_cap,
@ -49,7 +49,7 @@ protected:
void estimatePiElmoreBest(const Pin *drvr_pin,
float net_pin_cap,
float wireload_cap,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *min_max,
@ -65,7 +65,7 @@ protected:
float wireload_res,
float fanout,
float net_pin_cap,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *min_max,
@ -79,7 +79,7 @@ protected:
float wireload_res,
float fanout,
float net_pin_cap,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *min_max,

10
parasitics/NullParasitics.cc
View File

@ -74,7 +74,7 @@ NullParasitics::capacitance(Parasitic *) const
Parasitic *
NullParasitics::findPiElmore(const Pin *,
const TransRiseFall *,
const RiseFall *,
const ParasiticAnalysisPt *) const
{
return nullptr;
@ -82,7 +82,7 @@ NullParasitics::findPiElmore(const Pin *,
Parasitic *
NullParasitics::makePiElmore(const Pin *,
const TransRiseFall *,
const RiseFall *,
const ParasiticAnalysisPt *,
float,
float,
@ -154,7 +154,7 @@ NullParasitics::isPiPoleResidue(Parasitic* ) const
Parasitic *
NullParasitics::findPiPoleResidue(const Pin *,
const TransRiseFall *,
const RiseFall *,
const ParasiticAnalysisPt *) const
{
return nullptr;
@ -162,7 +162,7 @@ NullParasitics::findPiPoleResidue(const Pin *,
Parasitic *
NullParasitics::makePiPoleResidue(const Pin *,
const TransRiseFall *,
const RiseFall *,
const ParasiticAnalysisPt *,
float,
float,
@ -432,7 +432,7 @@ NullParasitics::reduceToPiPoleResidue2(Parasitic *,
Parasitic *
NullParasitics::estimatePiElmore(const Pin *,
const TransRiseFall *,
const RiseFall *,
const Wireload *,
float,
float,

10
parasitics/NullParasitics.hh
View File

@ -42,10 +42,10 @@ public:
virtual Parasitic *
findPiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap) const;
virtual Parasitic *makePiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap,
float c2, float rpi, float c1);
virtual bool isPiElmore(Parasitic *parasitic) const;
@ -66,10 +66,10 @@ public:
virtual bool isPiPoleResidue(Parasitic* parasitic) const;
virtual Parasitic *
findPiPoleResidue(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap) const;
virtual Parasitic *makePiPoleResidue(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap,
float c2, float rpi,
float c1);
@ -173,7 +173,7 @@ public:
const ParasiticAnalysisPt *ap);
virtual Parasitic *
estimatePiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const Wireload *wireload,
float fanout,
float net_pin_cap,

10
parasitics/Parasitics.hh
View File

@ -77,10 +77,10 @@ public:
// capacitor on the driver pin.
virtual bool isPiElmore(Parasitic *parasitic) const = 0;
virtual Parasitic *findPiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap) const = 0;
virtual Parasitic *makePiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap,
float c2,
float rpi,
@ -115,10 +115,10 @@ public:
// Pi model driver load with pole/residue interconnect model to load pins.
virtual bool isPiPoleResidue(Parasitic* parasitic) const = 0;
virtual Parasitic *findPiPoleResidue(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap) const=0;
virtual Parasitic *makePiPoleResidue(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ParasiticAnalysisPt *ap,
float c2,
float rpi,
@ -262,7 +262,7 @@ public:
// Estimate parasitic as pi elmore using wireload model.
virtual Parasitic *estimatePiElmore(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const Wireload *wireload,
float fanout,
float net_pin_cap,

18
parasitics/Parasitics.i
View File

@ -25,7 +25,7 @@ using sta::cmdLinkedNetwork;
using sta::Instance;
using sta::MinMaxAll;
using sta::ReduceParasiticsTo;
using sta::TransRiseFall;
using sta::RiseFall;
using sta::Pin;
using sta::TmpFloatSeq;
@ -56,12 +56,12 @@ read_spef_cmd(const char *filename,
TmpFloatSeq *
find_pi_elmore(Pin *drvr_pin,
TransRiseFall *tr,
RiseFall *rf,
MinMax *min_max)
{
float c2, rpi, c1;
bool exists;
Sta::sta()->findPiElmore(drvr_pin, tr, min_max, c2, rpi, c1, exists);
Sta::sta()->findPiElmore(drvr_pin, rf, min_max, c2, rpi, c1, exists);
TmpFloatSeq *floats = new FloatSeq;
if (exists) {
floats->push_back(c2);
@ -74,34 +74,34 @@ find_pi_elmore(Pin *drvr_pin,
float
find_elmore(Pin *drvr_pin,
Pin *load_pin,
TransRiseFall *tr,
RiseFall *rf,
MinMax *min_max)
{
float elmore = 0.0;
bool exists;
Sta::sta()->findElmore(drvr_pin, load_pin, tr, min_max, elmore, exists);
Sta::sta()->findElmore(drvr_pin, load_pin, rf, min_max, elmore, exists);
return elmore;
}
void
set_pi_model_cmd(Pin *drvr_pin,
TransRiseFall *tr,
RiseFall *rf,
MinMaxAll *min_max,
float c2,
float rpi,
float c1)
{
Sta::sta()->makePiElmore(drvr_pin, tr, min_max, c2, rpi, c1);
Sta::sta()->makePiElmore(drvr_pin, rf, min_max, c2, rpi, c1);
}
void
set_elmore_cmd(Pin *drvr_pin,
Pin *load_pin,
TransRiseFall *tr,
RiseFall *rf,
MinMaxAll *min_max,
float elmore)
{
Sta::sta()->setElmore(drvr_pin, load_pin, tr, min_max, elmore);
Sta::sta()->setElmore(drvr_pin, load_pin, rf, min_max, elmore);
}
%} // inline

38
parasitics/ReduceParasitics.cc
View File

@ -40,7 +40,7 @@ public:
ParasiticNode *drvr_node,
bool includes_pin_caps,
float coupling_cap_factor,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *cnst_min_max,
@ -71,7 +71,7 @@ protected:
bool includes_pin_caps_;
float coupling_cap_multiplier_;
const TransRiseFall *tr_;
const RiseFall *rf_;
const OperatingConditions *op_cond_;
const Corner *corner_;
const MinMax *cnst_min_max_;
@ -84,7 +84,7 @@ protected:
ReduceToPi::ReduceToPi(StaState *sta) :
StaState(sta),
coupling_cap_multiplier_(1.0),
tr_(nullptr),
rf_(nullptr),
op_cond_(nullptr),
corner_(nullptr),
cnst_min_max_(nullptr),
@ -101,7 +101,7 @@ ReduceToPi::reduceToPi(const Pin *drvr_pin,
ParasiticNode *drvr_node,
bool includes_pin_caps,
float coupling_cap_factor,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *cnst_min_max,
@ -112,7 +112,7 @@ ReduceToPi::reduceToPi(const Pin *drvr_pin,
{
includes_pin_caps_ = includes_pin_caps;
coupling_cap_multiplier_ = coupling_cap_factor;
tr_ = tr;
rf_ = rf;
op_cond_ = op_cond;
corner_ = corner;
cnst_min_max_ = cnst_min_max;
@ -212,13 +212,13 @@ ReduceToPi::pinCapacitance(ParasiticNode *node)
LibertyPort *lib_port = network_->libertyPort(port);
if (lib_port) {
if (!includes_pin_caps_) {
pin_cap = sdc_->pinCapacitance(pin, tr_, op_cond_, corner_,
pin_cap = sdc_->pinCapacitance(pin, rf_, op_cond_, corner_,
cnst_min_max_);
pin_caps_one_value_ &= lib_port->capacitanceIsOneValue();
}
}
else if (network_->isTopLevelPort(pin))
pin_cap = sdc_->portExtCap(port, tr_, cnst_min_max_);
pin_cap = sdc_->portExtCap(port, rf_, cnst_min_max_);
}
return pin_cap;
}
@ -276,7 +276,7 @@ public:
const Pin *drvr_pin,
ParasiticNode *drvr_node,
float coupling_cap_factor,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *cnst_min_max,
@ -308,11 +308,11 @@ reduceToPiElmore(Parasitic *parasitic_network,
sta->network()->pathName(drvr_pin));
ReduceToPiElmore reducer(sta);
reducer.makePiElmore(parasitic_network, drvr_pin, drvr_node,
coupling_cap_factor, TransRiseFall::rise(),
coupling_cap_factor, RiseFall::rise(),
op_cond, corner, cnst_min_max, ap);
if (!reducer.pinCapsOneValue())
reducer.makePiElmore(parasitic_network, drvr_pin, drvr_node,
coupling_cap_factor, TransRiseFall::fall(),
coupling_cap_factor, RiseFall::fall(),
op_cond, corner, cnst_min_max, ap);
}
}
@ -327,7 +327,7 @@ ReduceToPiElmore::makePiElmore(Parasitic *parasitic_network,
const Pin *drvr_pin,
ParasiticNode *drvr_node,
float coupling_cap_factor,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *cnst_min_max,
@ -337,9 +337,9 @@ ReduceToPiElmore::makePiElmore(Parasitic *parasitic_network,
reduceToPi(drvr_pin, drvr_node,
parasitics_->includesPinCaps(parasitic_network),
coupling_cap_factor,
tr, op_cond, corner, cnst_min_max, ap,
rf, op_cond, corner, cnst_min_max, ap,
c2, rpi, c1);
Parasitic *pi_elmore = parasitics_->makePiElmore(drvr_pin, tr, ap,
Parasitic *pi_elmore = parasitics_->makePiElmore(drvr_pin, rf, ap,
c2, rpi, c1);
parasitics_->setIsReducedParasiticNetwork(pi_elmore, true);
reduceElmoreDfs(drvr_pin, drvr_node, 0, 0.0, pi_elmore, ap);
@ -401,7 +401,7 @@ public:
const Pin *drvr_pin,
ParasiticNode *drvr_node,
float coupling_cap_factor,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *cnst_min_max,
@ -475,11 +475,11 @@ reduceToPiPoleResidue2(Parasitic *parasitic_network,
sta->network()->pathName(drvr_pin));
ReduceToPiPoleResidue2 reducer(sta);
reducer.makePiPoleResidue2(parasitic_network, drvr_pin, drvr_node,
coupling_cap_factor, TransRiseFall::rise(),
coupling_cap_factor, RiseFall::rise(),
op_cond, corner, cnst_min_max, ap);
if (!reducer.pinCapsOneValue())
reducer.makePiPoleResidue2(parasitic_network, drvr_pin, drvr_node,
coupling_cap_factor, TransRiseFall::fall(),
coupling_cap_factor, RiseFall::fall(),
op_cond, corner, cnst_min_max, ap);
}
}
@ -489,7 +489,7 @@ ReduceToPiPoleResidue2::makePiPoleResidue2(Parasitic *parasitic_network,
const Pin *drvr_pin,
ParasiticNode *drvr_node,
float coupling_cap_factor,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *cnst_min_max,
@ -499,10 +499,10 @@ ReduceToPiPoleResidue2::makePiPoleResidue2(Parasitic *parasitic_network,
reduceToPi(drvr_pin, drvr_node,
parasitics_->includesPinCaps(parasitic_network),
coupling_cap_factor,
tr, op_cond, corner, cnst_min_max, ap,
rf, op_cond, corner, cnst_min_max, ap,
c2, rpi, c1);
Parasitic *pi_pole_residue = parasitics_->makePiPoleResidue(drvr_pin,
tr, ap,
rf, ap,
c2, rpi, c1);
parasitics_->setIsReducedParasiticNetwork(pi_pole_residue, true);
findPolesResidues(parasitic_network, pi_pole_residue,

4
parasitics/SpefReader.cc
View File

@ -408,7 +408,7 @@ SpefReader::rspfDrvrBegin(Pin *drvr_pin,
if (drvr_pin) {
// Incremental parasitics do not overwrite existing parasitics.
if (!(increment_ &&
parasitics_->findPiElmore(drvr_pin, TransRiseFall::rise(), ap_))) {
parasitics_->findPiElmore(drvr_pin, RiseFall::rise(), ap_))) {
float c2 = pi->c2()->value(triple_index_) * cap_scale_;
float rpi = pi->r1()->value(triple_index_) * res_scale_;
float c1 = pi->c1()->value(triple_index_) * cap_scale_;
@ -416,7 +416,7 @@ SpefReader::rspfDrvrBegin(Pin *drvr_pin,
parasitics_->deleteParasitics(drvr_pin, ap_);
// Only one parasitic, save it under rise transition.
parasitic_ = parasitics_->makePiElmore(drvr_pin,
TransRiseFall::rise(),
RiseFall::rise(),
ap_, c2, rpi, c1);
}
}

96
sdc/Clock.cc
View File

@ -115,8 +115,8 @@ Clock::setMasterClk(Clock *master)
void
Clock::makeClkEdges()
{
clk_edges_ = new ClockEdge*[TransRiseFall::index_count];
for (auto tr : TransRiseFall::range()) {
clk_edges_ = new ClockEdge*[RiseFall::index_count];
for (auto tr : RiseFall::range()) {
clk_edges_[tr->index()] = new ClockEdge(this, tr);
}
}
@ -125,8 +125,8 @@ Clock::~Clock()
{
stringDelete(name_);
if (clk_edges_) {
delete clk_edges_[TransRiseFall::riseIndex()];
delete clk_edges_[TransRiseFall::fallIndex()];
delete clk_edges_[RiseFall::riseIndex()];
delete clk_edges_[RiseFall::fallIndex()];
delete [] clk_edges_;
}
delete waveform_;
@ -157,15 +157,15 @@ Clock::setAddToPins(bool add_to_pins)
void
Clock::setClkEdgeTimes()
{
setClkEdgeTime(TransRiseFall::rise());
setClkEdgeTime(TransRiseFall::fall());
setClkEdgeTime(RiseFall::rise());
setClkEdgeTime(RiseFall::fall());
}
void
Clock::setClkEdgeTime(const TransRiseFall *tr)
Clock::setClkEdgeTime(const RiseFall *rf)
{
float time = (tr == TransRiseFall::rise()) ? (*waveform_)[0]:(*waveform_)[1];
clk_edges_[tr->index()]->setTime(time);
float time = (rf == RiseFall::rise()) ? (*waveform_)[0]:(*waveform_)[1];
clk_edges_[rf->index()]->setTime(time);
}
Pin *
@ -179,9 +179,9 @@ Clock::defaultPin() const
}
ClockEdge *
Clock::edge(const TransRiseFall *tr) const
Clock::edge(const RiseFall *rf) const
{
return clk_edges_[tr->index()];
return clk_edges_[rf->index()];
}
void
@ -191,41 +191,41 @@ Clock::setIsPropagated(bool propagated)
}
void
Clock::slew(const TransRiseFall *tr,
Clock::slew(const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &slew,
bool &exists) const
{
slews_.value(tr, min_max, slew, exists);
slews_.value(rf, min_max, slew, exists);
}
float
Clock::slew(const TransRiseFall *tr,
Clock::slew(const RiseFall *rf,
const MinMax *min_max) const
{
float slew;
bool exists;
slews_.value(tr, min_max, slew, exists);
slews_.value(rf, min_max, slew, exists);
if (!exists)
slew = 0.0;
return slew;
}
void
Clock::setSlew(const TransRiseFallBoth *tr,
Clock::setSlew(const RiseFallBoth *rf,
const MinMaxAll *min_max,
float slew)
{
slews_.setValue(tr, min_max, slew);
slews_.setValue(rf, min_max, slew);
}
void
Clock::setSlew(const TransRiseFall *tr,
Clock::setSlew(const RiseFall *rf,
const MinMax *min_max,
float slew)
{
slews_.setValue(tr, min_max, slew);
slews_.setValue(rf, min_max, slew);
}
void
@ -235,23 +235,23 @@ Clock::removeSlew()
}
void
Clock::setSlewLimit(const TransRiseFallBoth *tr,
Clock::setSlewLimit(const RiseFallBoth *rf,
const PathClkOrData clk_data,
const MinMax *min_max,
float slew)
{
slew_limits_[int(clk_data)].setValue(tr, min_max, slew);
slew_limits_[int(clk_data)].setValue(rf, min_max, slew);
}
void
Clock::slewLimit(const TransRiseFall *tr,
Clock::slewLimit(const RiseFall *rf,
const PathClkOrData clk_data,
const MinMax *min_max,
// Return values.
float &slew,
bool &exists) const
{
slew_limits_[int(clk_data)].value(tr, min_max, slew, exists);
slew_limits_[int(clk_data)].value(rf, min_max, slew, exists);
}
void
@ -482,13 +482,13 @@ isPowerOfTwo(int i)
return (i & (i - 1)) == 0;
}
const TransRiseFall *
Clock::masterClkEdgeTr(const TransRiseFall *tr) const
const RiseFall *
Clock::masterClkEdgeTr(const RiseFall *rf) const
{
int edge_index = (tr == TransRiseFall::rise()) ? 0 : 1;
int edge_index = (rf == RiseFall::rise()) ? 0 : 1;
return ((*edges_)[edge_index] - 1) % 2
? TransRiseFall::fall()
: TransRiseFall::rise();
? RiseFall::fall()
: RiseFall::rise();
}
void
@ -529,12 +529,12 @@ Clock::isDivideByOneCombinational() const
////////////////////////////////////////////////////////////////
ClockEdge::ClockEdge(Clock *clock,
TransRiseFall *tr) :
RiseFall *rf) :
clock_(clock),
tr_(tr),
name_(stringPrint("%s %s", clock_->name(), tr_->asString())),
rf_(rf),
name_(stringPrint("%s %s", clock_->name(), rf_->asString())),
time_(0.0),
index_(clock_->index() * TransRiseFall::index_count + tr_->index())
index_(clock_->index() * RiseFall::index_count + rf_->index())
{
}
@ -552,7 +552,7 @@ ClockEdge::setTime(float time)
ClockEdge *
ClockEdge::opposite() const
{
return clock_->edge(tr_->opposite());
return clock_->edge(rf_->opposite());
}
float
@ -630,44 +630,44 @@ InterClockUncertainty::InterClockUncertainty(const Clock *src,
bool
InterClockUncertainty::empty() const
{
return uncertainties_[TransRiseFall::riseIndex()].empty()
&& uncertainties_[TransRiseFall::fallIndex()].empty();
return uncertainties_[RiseFall::riseIndex()].empty()
&& uncertainties_[RiseFall::fallIndex()].empty();
}
void
InterClockUncertainty::uncertainty(const TransRiseFall *src_tr,
const TransRiseFall *tgt_tr,
InterClockUncertainty::uncertainty(const RiseFall *src_rf,
const RiseFall *tgt_rf,
const SetupHold *setup_hold,
float &uncertainty,
bool &exists) const
{
uncertainties_[src_tr->index()].value(tgt_tr, setup_hold,
uncertainties_[src_rf->index()].value(tgt_rf, setup_hold,
uncertainty, exists);
}
void
InterClockUncertainty::setUncertainty(const TransRiseFallBoth *src_tr,
const TransRiseFallBoth *tgt_tr,
InterClockUncertainty::setUncertainty(const RiseFallBoth *src_rf,
const RiseFallBoth *tgt_rf,
const SetupHoldAll *setup_hold,
float uncertainty)
{
for (auto src_tr_index : src_tr->rangeIndex())
uncertainties_[src_tr_index].setValue(tgt_tr, setup_hold, uncertainty);
for (auto src_rf_index : src_rf->rangeIndex())
uncertainties_[src_rf_index].setValue(tgt_rf, setup_hold, uncertainty);
}
void
InterClockUncertainty::removeUncertainty(const TransRiseFallBoth *src_tr,
const TransRiseFallBoth *tgt_tr,
InterClockUncertainty::removeUncertainty(const RiseFallBoth *src_rf,
const RiseFallBoth *tgt_rf,
const SetupHoldAll *setup_hold)
{
for (auto src_tr_index : src_tr->rangeIndex())
uncertainties_[src_tr_index].removeValue(tgt_tr, setup_hold);
for (auto src_rf_index : src_rf->rangeIndex())
uncertainties_[src_rf_index].removeValue(tgt_rf, setup_hold);
}
const RiseFallMinMax *
InterClockUncertainty::uncertainties(TransRiseFall *src_tr) const
InterClockUncertainty::uncertainties(RiseFall *src_rf) const
{
return &uncertainties_[src_tr->index()];
return &uncertainties_[src_rf->index()];
}
bool

40
sdc/Clock.hh
View File

@ -51,32 +51,32 @@ public:
void setAddToPins(bool add_to_pins);
FloatSeq *waveform() { return waveform_; }
const FloatSeq *waveform() const { return waveform_; }
ClockEdge *edge(const TransRiseFall *tr) const;
ClockEdge *edge(const RiseFall *rf) const;
int index() const { return index_; }
bool isPropagated() const { return is_propagated_; }
void setIsPropagated(bool propagated);
// Ideal clock slew.
void slew(const TransRiseFall *tr,
void slew(const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &slew,
bool &exists) const;
// Return zero (default) if no slew exists.
float slew(const TransRiseFall *tr,
float slew(const RiseFall *rf,
const MinMax *min_max) const;
void setSlew(const TransRiseFall *tr,
void setSlew(const RiseFall *rf,
const MinMax *min_max,
float slew);
void setSlew(const TransRiseFallBoth *tr,
void setSlew(const RiseFallBoth *rf,
const MinMaxAll *min_max,
float slew);
void removeSlew();
RiseFallMinMax *slews() { return &slews_; }
void setSlewLimit(const TransRiseFallBoth *tr,
void setSlewLimit(const RiseFallBoth *rf,
const PathClkOrData clk_data,
const MinMax *min_max,
float slew);
void slewLimit(const TransRiseFall *tr,
void slewLimit(const RiseFall *rf,
const PathClkOrData clk_data,
const MinMax *min_max,
// Return values.
@ -115,7 +115,7 @@ public:
bool invert() const { return invert_; }
IntSeq *edges() const { return edges_; }
FloatSeq *edgeShifts() const { return edge_shifts_; }
const TransRiseFall *masterClkEdgeTr(const TransRiseFall *tr) const;
const RiseFall *masterClkEdgeTr(const RiseFall *rf) const;
bool combinational() const { return combinational_; }
bool isDivideByOneCombinational() const;
bool generatedUpToDate() const;
@ -157,7 +157,7 @@ protected:
void setMasterClk(Clock *master);
void makeClkEdges();
void setClkEdgeTimes();
void setClkEdgeTime(const TransRiseFall *tr);
void setClkEdgeTime(const RiseFall *rf);
void generateScaledClk(const Clock *src_clk,
float scale);
void generateEdgesClk(const Clock *src_clk);
@ -204,7 +204,7 @@ class ClockEdge
public:
Clock *clock() const { return clock_; }
~ClockEdge();
TransRiseFall *transition() const { return tr_; }
RiseFall *transition() const { return rf_; }
float time() const { return time_; }
const char *name() const { return name_; }
int index() const { return index_; }
@ -215,11 +215,11 @@ public:
friend class Clock; // builder
private:
DISALLOW_COPY_AND_ASSIGN(ClockEdge);
ClockEdge(Clock *clock, TransRiseFall *tr);
ClockEdge(Clock *clock, RiseFall *rf);
void setTime(float time);
Clock *clock_;
TransRiseFall *tr_;
RiseFall *rf_;
const char *name_;
float time_;
int index_;
@ -250,20 +250,20 @@ public:
const Clock *target);
const Clock *src() const { return src_; }
const Clock *target() const { return target_; }
void uncertainty(const TransRiseFall *src_tr,
const TransRiseFall *tgt_tr,
void uncertainty(const RiseFall *src_rf,
const RiseFall *tgt_rf,
const SetupHold *setup_hold,
// Return values.
float &uncertainty,
bool &exists) const;
void setUncertainty(const TransRiseFallBoth *src_tr,
const TransRiseFallBoth *tgt_tr,
void setUncertainty(const RiseFallBoth *src_rf,
const RiseFallBoth *tgt_rf,
const SetupHoldAll *setup_hold,
float uncertainty);
void removeUncertainty(const TransRiseFallBoth *src_tr,
const TransRiseFallBoth *tgt_tr,
void removeUncertainty(const RiseFallBoth *src_rf,
const RiseFallBoth *tgt_rf,
const SetupHoldAll *setup_hold);
const RiseFallMinMax *uncertainties(TransRiseFall *src_tr) const;
const RiseFallMinMax *uncertainties(RiseFall *src_rf) const;
bool empty() const;
private:
@ -271,7 +271,7 @@ private:
const Clock *src_;
const Clock *target_;
RiseFallMinMax uncertainties_[TransRiseFall::index_count];
RiseFallMinMax uncertainties_[RiseFall::index_count];
};
class InterClockUncertaintyLess

16
sdc/ClockInsertion.cc
View File

@ -27,23 +27,23 @@ ClockInsertion::ClockInsertion(const Clock *clk,
}
void
ClockInsertion::setDelay(const TransRiseFallBoth *tr,
ClockInsertion::setDelay(const RiseFallBoth *rf,
const MinMaxAll *min_max,
const EarlyLateAll *early_late,
float delay)
{
for (auto el_index : early_late->rangeIndex())
delays_[el_index].setValue(tr, min_max, delay);
delays_[el_index].setValue(rf, min_max, delay);
}
float
ClockInsertion::delay(const TransRiseFall *tr,
ClockInsertion::delay(const RiseFall *rf,
const MinMax *min_max,
const EarlyLate *early_late)
{
float insertion;
bool exists;
delays_[early_late->index()].value(tr, min_max, insertion, exists);
delays_[early_late->index()].value(rf, min_max, insertion, exists);
if (exists)
return insertion;
else
@ -51,7 +51,7 @@ ClockInsertion::delay(const TransRiseFall *tr,
}
void
ClockInsertion::delay(const TransRiseFall *tr,
ClockInsertion::delay(const RiseFall *rf,
const MinMax *min_max,
const EarlyLate *early_late,
// Return values.
@ -59,18 +59,18 @@ ClockInsertion::delay(const TransRiseFall *tr,
bool &exists)
{
delays_[early_late->index()].value(tr, min_max, insertion, exists);
delays_[early_late->index()].value(rf, min_max, insertion, exists);
if (!exists)
insertion = 0.0;
}
void
ClockInsertion::setDelay(const TransRiseFall *tr,
ClockInsertion::setDelay(const RiseFall *rf,
const MinMax *min_max,
const EarlyLate *early_late,
float delay)
{
delays_[early_late->index()].setValue(tr, min_max, delay);
delays_[early_late->index()].setValue(rf, min_max, delay);
}
void

8
sdc/ClockInsertion.hh
View File

@ -32,16 +32,16 @@ public:
ClockInsertion(const Clock *clk, const Pin *pin);
const Clock *clock() const { return clk_; }
const Pin *pin() const { return pin_; }
float delay(const TransRiseFall *tr, const MinMax *min_max,
float delay(const RiseFall *rf, const MinMax *min_max,
const EarlyLate *early_late);
void delay(const TransRiseFall *tr, const MinMax *min_max,
void delay(const RiseFall *rf, const MinMax *min_max,
const EarlyLate *early_late,
// Return values.
float &insertion, bool &exists);
RiseFallMinMax *delays(const EarlyLate *early_late);
void setDelay(const TransRiseFall *tr, const MinMax *min_max,
void setDelay(const RiseFall *rf, const MinMax *min_max,
const EarlyLate *early_late, float delay);
void setDelay(const TransRiseFallBoth *tr, const MinMaxAll *min_max,
void setDelay(const RiseFallBoth *rf, const MinMaxAll *min_max,
const EarlyLateAll *early_late, float delay);
void setDelays(RiseFallMinMax *delays);

16
sdc/ClockLatency.cc
View File

@ -27,20 +27,20 @@ ClockLatency::ClockLatency(const Clock *clk,
}
void
ClockLatency::setDelay(const TransRiseFallBoth *tr,
ClockLatency::setDelay(const RiseFallBoth *rf,
const MinMaxAll *min_max,
float delay)
{
delays_.setValue(tr, min_max, delay);
delays_.setValue(rf, min_max, delay);
}
float
ClockLatency::delay(const TransRiseFall *tr,
ClockLatency::delay(const RiseFall *rf,
const MinMax *min_max)
{
float latency;
bool exists;
delays_.value(tr, min_max, latency, exists);
delays_.value(rf, min_max, latency, exists);
if (exists)
return latency;
else
@ -48,24 +48,24 @@ ClockLatency::delay(const TransRiseFall *tr,
}
void
ClockLatency::delay(const TransRiseFall *tr,
ClockLatency::delay(const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &latency,
bool &exists)
{
delays_.value(tr, min_max, latency, exists);
delays_.value(rf, min_max, latency, exists);
if (!exists)
latency = 0.0;
}
void
ClockLatency::setDelay(const TransRiseFall *tr,
ClockLatency::setDelay(const RiseFall *rf,
const MinMax *min_max,
float delay)
{
delays_.setValue(tr, min_max, delay);
delays_.setValue(rf, min_max, delay);
}
void

8
sdc/ClockLatency.hh
View File

@ -33,18 +33,18 @@ public:
const Pin *pin);
const Clock *clock() const { return clk_; }
const Pin *pin() const { return pin_; }
float delay(const TransRiseFall *tr,
float delay(const RiseFall *rf,
const MinMax *min_max);
void delay(const TransRiseFall *tr,
void delay(const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &latency,
bool &exists);
RiseFallMinMax *delays();
void setDelay(const TransRiseFall *tr,
void setDelay(const RiseFall *rf,
const MinMax *min_max,
float delay);
void setDelay(const TransRiseFallBoth *tr,
void setDelay(const RiseFallBoth *rf,
const MinMaxAll *min_max,
float delay);
void setDelays(RiseFallMinMax *delays);

28
sdc/DataCheck.cc
View File

@ -30,40 +30,40 @@ DataCheck::DataCheck(Pin *from,
}
void
DataCheck::margin(const TransRiseFall *from_tr,
const TransRiseFall *to_tr,
DataCheck::margin(const RiseFall *from_rf,
const RiseFall *to_rf,
const SetupHold *setup_hold,
// Return values.
float &margin,
bool &exists) const
{
return margins_[from_tr->index()].value(to_tr, setup_hold,
return margins_[from_rf->index()].value(to_rf, setup_hold,
margin, exists);
}
void
DataCheck::setMargin(const TransRiseFallBoth *from_tr,
const TransRiseFallBoth *to_tr,
DataCheck::setMargin(const RiseFallBoth *from_rf,
const RiseFallBoth *to_rf,
const SetupHoldAll *setup_hold,
float margin)
{
for (auto from_tr_index : from_tr->rangeIndex())
margins_[from_tr_index].setValue(to_tr, setup_hold, margin);
for (auto from_rf_index : from_rf->rangeIndex())
margins_[from_rf_index].setValue(to_rf, setup_hold, margin);
}
void
DataCheck::removeMargin(const TransRiseFallBoth *from_tr,
const TransRiseFallBoth *to_tr,
DataCheck::removeMargin(const RiseFallBoth *from_rf,
const RiseFallBoth *to_rf,
const SetupHoldAll *setup_hold)
{
for (auto from_tr_index : from_tr->rangeIndex())
margins_[from_tr_index].removeValue(to_tr, setup_hold);
for (auto from_rf_index : from_rf->rangeIndex())
margins_[from_rf_index].removeValue(to_rf, setup_hold);
}
bool
DataCheck::empty() const
{
for (auto tr_index : TransRiseFall::rangeIndex()) {
for (auto tr_index : RiseFall::rangeIndex()) {
if (!margins_[tr_index].empty())
return false;
}
@ -77,8 +77,8 @@ DataCheck::marginIsOneValue(SetupHold *setup_hold,
bool &one_value) const
{
float value1, value2;
if (margins_[TransRiseFall::riseIndex()].isOneValue(setup_hold, value1)
&& margins_[TransRiseFall::fallIndex()].isOneValue(setup_hold, value2)
if (margins_[RiseFall::riseIndex()].isOneValue(setup_hold, value1)
&& margins_[RiseFall::fallIndex()].isOneValue(setup_hold, value2)
&& value1 == value2) {
value = value1;
one_value = true;

14
sdc/DataCheck.hh
View File

@ -38,18 +38,18 @@ public:
Pin *from() const { return from_; }
Pin *to() const { return to_; }
Clock *clk() const { return clk_; }
void margin(const TransRiseFall *from_tr,
const TransRiseFall *to_tr,
void margin(const RiseFall *from_rf,
const RiseFall *to_rf,
const SetupHold *setup_hold,
// Return values.
float &margin,
bool &exists) const;
void setMargin(const TransRiseFallBoth *from_tr,
const TransRiseFallBoth *to_tr,
void setMargin(const RiseFallBoth *from_rf,
const RiseFallBoth *to_rf,
const SetupHoldAll *setup_hold,
float margin);
void removeMargin(const TransRiseFallBoth *from_tr,
const TransRiseFallBoth *to_tr,
void removeMargin(const RiseFallBoth *from_rf,
const RiseFallBoth *to_rf,
const SetupHoldAll *setup_hold);
bool empty() const;
void marginIsOneValue(SetupHold *setup_hold,
@ -63,7 +63,7 @@ private:
Pin *from_;
Pin *to_;
Clock *clk_;
RiseFallMinMax margins_[TransRiseFall::index_count];
RiseFallMinMax margins_[RiseFall::index_count];
};
class DataCheckLess

24
sdc/DeratingFactors.cc
View File

@ -32,22 +32,22 @@ DeratingFactors::DeratingFactors()
void
DeratingFactors::setFactor(PathClkOrData clk_data,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const EarlyLate *early_late,
float factor)
{
for (auto tr1 : tr->range())
for (auto tr1 : rf->range())
factors_[int(clk_data)].setValue(tr1, early_late, factor);
}
void
DeratingFactors::factor(PathClkOrData clk_data,
const TransRiseFall *tr,
const RiseFall *rf,
const EarlyLate *early_late,
float &factor,
bool &exists) const
{
factors_[int(clk_data)].value(tr, early_late, factor, exists);
factors_[int(clk_data)].value(rf, early_late, factor, exists);
}
void
@ -98,22 +98,22 @@ DeratingFactorsGlobal::DeratingFactorsGlobal()
void
DeratingFactorsGlobal::setFactor(TimingDerateType type,
PathClkOrData clk_data,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const EarlyLate *early_late,
float factor)
{
factors_[TimingDerateIndex(type)].setFactor(clk_data, tr, early_late, factor);
factors_[TimingDerateIndex(type)].setFactor(clk_data, rf, early_late, factor);
}
void
DeratingFactorsGlobal::factor(TimingDerateType type,
PathClkOrData clk_data,
const TransRiseFall *tr,
const RiseFall *rf,
const EarlyLate *early_late,
float &factor,
bool &exists) const
{
factors_[TimingDerateIndex(type)].factor(clk_data, tr, early_late, factor, exists);
factors_[TimingDerateIndex(type)].factor(clk_data, rf, early_late, factor, exists);
}
void
@ -139,22 +139,22 @@ DeratingFactorsCell::DeratingFactorsCell()
void
DeratingFactorsCell::setFactor(TimingDerateType type,
PathClkOrData clk_data,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const EarlyLate *early_late,
float factor)
{
factors_[TimingDerateIndex(type)].setFactor(clk_data, tr, early_late, factor);
factors_[TimingDerateIndex(type)].setFactor(clk_data, rf, early_late, factor);
}
void
DeratingFactorsCell::factor(TimingDerateType type,
PathClkOrData clk_data,
const TransRiseFall *tr,
const RiseFall *rf,
const EarlyLate *early_late,
float &factor,
bool &exists) const
{
factors_[TimingDerateIndex(type)].factor(clk_data, tr, early_late, factor, exists);
factors_[TimingDerateIndex(type)].factor(clk_data, rf, early_late, factor, exists);
}
void

12
sdc/DeratingFactors.hh
View File

@ -30,11 +30,11 @@ class DeratingFactors
public:
DeratingFactors();
void setFactor(PathClkOrData clk_data,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const EarlyLate *early_late,
float factor);
void factor(PathClkOrData clk_data,
const TransRiseFall *tr,
const RiseFall *rf,
const EarlyLate *early_late,
float &factor,
bool &exists) const;
@ -60,12 +60,12 @@ public:
DeratingFactorsGlobal();
void setFactor(TimingDerateType type,
PathClkOrData clk_data,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const EarlyLate *early_late,
float factor);
void factor(TimingDerateType type,
PathClkOrData clk_data,
const TransRiseFall *tr,
const RiseFall *rf,
const EarlyLate *early_late,
float &factor,
bool &exists) const;
@ -84,12 +84,12 @@ public:
DeratingFactorsCell();
void setFactor(TimingDerateType type,
PathClkOrData clk_data,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const EarlyLate *early_late,
float factor);
void factor(TimingDerateType type,
PathClkOrData clk_data,
const TransRiseFall *tr,
const RiseFall *rf,
const EarlyLate *early_late,
float &factor,
bool &exists) const;

142
sdc/ExceptionPath.cc
View File

@ -162,9 +162,9 @@ checkFromThrusTo(ExceptionFrom *from,
|| (to
&& (!to->hasObjects()
&& to->transition()
== TransRiseFallBoth::riseFall()
== RiseFallBoth::riseFall()
&& (to->endTransition()
== TransRiseFallBoth::riseFall()))));
== RiseFallBoth::riseFall()))));
if (thrus) {
ExceptionThruSeq::Iterator thru_iter(thrus);
while (thru_iter.hasNext()) {
@ -239,11 +239,11 @@ ExceptionPath::firstPt()
}
bool
ExceptionPath::matchesFirstPt(const TransRiseFall *to_tr,
ExceptionPath::matchesFirstPt(const RiseFall *to_rf,
const MinMax *min_max)
{
ExceptionPt *first_pt = firstPt();
return first_pt->transition()->matches(to_tr)
return first_pt->transition()->matches(to_rf)
&& matches(min_max, false);
}
@ -932,9 +932,9 @@ GroupPath::overrides(ExceptionPath *exception) const
const int ExceptionPt::as_string_max_objects_ = 20;
ExceptionPt::ExceptionPt(const TransRiseFallBoth *tr,
ExceptionPt::ExceptionPt(const RiseFallBoth *rf,
bool own_pts) :
tr_(tr),
rf_(rf),
own_pts_(own_pts),
hash_(0)
{
@ -951,9 +951,9 @@ ExceptionPt::hash() const
ExceptionFromTo::ExceptionFromTo(PinSet *pins,
ClockSet *clks,
InstanceSet *insts,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
bool own_pts) :
ExceptionPt(tr, own_pts),
ExceptionPt(rf, own_pts),
pins_(pins),
clks_(clks),
insts_(insts)
@ -1074,7 +1074,7 @@ ExceptionFromTo::equal(ExceptionFromTo *from_to) const
return PinSet::equal(from_to->pins_, pins_)
&& ClockSet::equal(from_to->clks_, clks_)
&& InstanceSet::equal(from_to->insts_, insts_)
&& from_to->transition() == tr_;
&& from_to->transition() == rf_;
}
int
@ -1089,7 +1089,7 @@ ExceptionFromTo::nameCmp(ExceptionPt *pt2,
if (clk_cmp == 0) {
int inst_cmp = setNameCmp(insts_, pt2->instances(), network);
if (inst_cmp == 0)
return tr_->index() - pt2->transition()->index();
return rf_->index() - pt2->transition()->index();
else
return inst_cmp;
}
@ -1304,9 +1304,9 @@ ExceptionFromTo::objectCount() const
ExceptionFrom::ExceptionFrom(PinSet *pins,
ClockSet *clks,
InstanceSet *insts,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
bool own_pts) :
ExceptionFromTo(pins, clks, insts, tr, own_pts)
ExceptionFromTo(pins, clks, insts, rf, own_pts)
{
}
@ -1314,7 +1314,7 @@ void
ExceptionFrom::findHash()
{
ExceptionFromTo::findHash();
hash_ += tr_->index() * 31 + 29;
hash_ += rf_->index() * 31 + 29;
}
ExceptionFrom *
@ -1329,13 +1329,13 @@ ExceptionFrom::clone()
InstanceSet *insts = nullptr;
if (insts_)
insts = new InstanceSet(*insts_);
return new ExceptionFrom(pins, clks, insts, tr_, true);
return new ExceptionFrom(pins, clks, insts, rf_, true);
}
bool
ExceptionFrom::intersectsPts(ExceptionFrom *from) const
{
return from->transition() == tr_
return from->transition() == rf_
&& ((pins_ && PinSet::intersects(pins_, from->pins()))
|| (clks_ && ClockSet::intersects(clks_, from->clks()))
|| (insts_ && InstanceSet::intersects(insts_, from->instances())));
@ -1344,9 +1344,9 @@ ExceptionFrom::intersectsPts(ExceptionFrom *from) const
const char *
ExceptionFrom::cmdKeyword() const
{
if (tr_ == TransRiseFallBoth::rise())
if (rf_ == RiseFallBoth::rise())
return "-rise_from";
else if (tr_ == TransRiseFallBoth::fall())
else if (rf_ == RiseFallBoth::fall())
return "-fall_from";
else
return "-from";
@ -1357,11 +1357,11 @@ ExceptionFrom::cmdKeyword() const
ExceptionTo::ExceptionTo(PinSet *pins,
ClockSet *clks,
InstanceSet *insts,
const TransRiseFallBoth *tr,
const TransRiseFallBoth *end_tr,
const RiseFallBoth *rf,
const RiseFallBoth *end_rf,
bool own_pts) :
ExceptionFromTo(pins, clks, insts, tr, own_pts),
end_tr_(end_tr)
ExceptionFromTo(pins, clks, insts, rf, own_pts),
end_rf_(end_rf)
{
}
@ -1377,7 +1377,7 @@ ExceptionTo::clone()
InstanceSet *insts = nullptr;
if (insts_)
insts = new InstanceSet(*insts_);
return new ExceptionTo(pins, clks, insts, tr_, end_tr_, true);
return new ExceptionTo(pins, clks, insts, rf_, end_rf_, true);
}
const char *
@ -1387,8 +1387,8 @@ ExceptionTo::asString(const Network *network) const
if (hasObjects())
str += ExceptionFromTo::asString(network);
if (end_tr_ != TransRiseFallBoth::riseFall())
str += (end_tr_ == TransRiseFallBoth::rise()) ? " -rise" : " -fall";
if (end_rf_ != RiseFallBoth::riseFall())
str += (end_rf_ == RiseFallBoth::rise()) ? " -rise" : " -fall";
char *result = makeTmpString(str.size() + 1);
strcpy(result, str.c_str());
@ -1398,8 +1398,8 @@ ExceptionTo::asString(const Network *network) const
bool
ExceptionTo::intersectsPts(ExceptionTo *to) const
{
return to->transition() == tr_
&& to->endTransition() == end_tr_
return to->transition() == rf_
&& to->endTransition() == end_rf_
&& ((pins_ && PinSet::intersects(pins_, to->pins()))
|| (clks_ && ClockSet::intersects(clks_, to->clks()))
|| (insts_ && InstanceSet::intersects(insts_, to->instances())));
@ -1408,65 +1408,65 @@ ExceptionTo::intersectsPts(ExceptionTo *to) const
bool
ExceptionTo::matchesFilter(const Pin *pin,
const ClockEdge *clk_edge,
const TransRiseFall *end_tr,
const RiseFall *end_rf,
const Network *network) const
{
// "report -to reg" does match clock pins.
return matches(pin, clk_edge, end_tr, true, network);
return matches(pin, clk_edge, end_rf, true, network);
}
bool
ExceptionTo::matches(const Pin *pin,
const ClockEdge *clk_edge,
const TransRiseFall *end_tr,
const RiseFall *end_rf,
const Network *network) const
{
// "exception -to reg" does not match reg clock pins.
return matches(pin, clk_edge, end_tr, false, network);
return matches(pin, clk_edge, end_rf, false, network);
}
bool
ExceptionTo::matches(const Pin *pin,
const ClockEdge *clk_edge,
const TransRiseFall *end_tr,
const RiseFall *end_rf,
bool inst_matches_reg_clk_pin,
const Network *network) const
{
return (pins_
&& pins_->hasKey(const_cast<Pin*>(pin))
&& tr_->matches(end_tr)
&& end_tr_->matches(end_tr))
&& rf_->matches(end_rf)
&& end_rf_->matches(end_rf))
|| (clk_edge
&& clks_
&& clks_->hasKey(const_cast<Clock*>(clk_edge->clock()))
&& tr_->matches(clk_edge->transition())
&& end_tr_->matches(end_tr))
&& rf_->matches(clk_edge->transition())
&& end_rf_->matches(end_rf))
|| (insts_
&& (inst_matches_reg_clk_pin
|| !network->isRegClkPin(pin))
&& insts_->hasKey(network->instance(pin))
&& network->direction(pin)->isAnyInput()
&& tr_->matches(end_tr)
&& end_tr_->matches(end_tr))
&& rf_->matches(end_rf)
&& end_rf_->matches(end_rf))
|| (pins_ == nullptr
&& clks_ == nullptr
&& insts_ == nullptr
&& end_tr_->matches(end_tr));
&& end_rf_->matches(end_rf));
}
bool
ExceptionTo::matches(const Pin *pin,
const TransRiseFall *end_tr) const
const RiseFall *end_rf) const
{
return (pins_
&& pins_->hasKey(const_cast<Pin*>(pin))
&& tr_->matches(end_tr)
&& end_tr_->matches(end_tr))
&& rf_->matches(end_rf)
&& end_rf_->matches(end_rf))
|| (pins_ == nullptr
&& clks_ == nullptr
&& insts_ == nullptr
&& end_tr_->matches(end_tr));
&& end_rf_->matches(end_rf));
}
bool
@ -1479,9 +1479,9 @@ ExceptionTo::matches(const Clock *clk) const
const char *
ExceptionTo::cmdKeyword() const
{
if (tr_ == TransRiseFallBoth::rise())
if (rf_ == RiseFallBoth::rise())
return "-rise_to";
else if (tr_ == TransRiseFallBoth::fall())
else if (rf_ == RiseFallBoth::fall())
return "-fall_to";
else
return "-to";
@ -1494,7 +1494,7 @@ ExceptionTo::nameCmp(ExceptionPt *pt2,
ExceptionTo *to2 = dynamic_cast<ExceptionTo*>(pt2);
int cmp = ExceptionFromTo::nameCmp(pt2, network);
if (cmp == 0)
return end_tr_->index() - to2->endTransition()->index();
return end_rf_->index() - to2->endTransition()->index();
else
return cmp;
}
@ -1504,10 +1504,10 @@ ExceptionTo::nameCmp(ExceptionPt *pt2,
ExceptionThru::ExceptionThru(PinSet *pins,
NetSet *nets,
InstanceSet *insts,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
bool own_pts,
const Network *network) :
ExceptionPt(tr, own_pts),
ExceptionPt(rf, own_pts),
pins_(pins),
edges_(nullptr),
nets_(nets),
@ -1739,9 +1739,9 @@ ExceptionThru::asString(const Network *network) const
}
if (obj_count == as_string_max_objects_)
str += ", ...";
if (tr_ == TransRiseFallBoth::rise())
if (rf_ == RiseFallBoth::rise())
str += " rise";
else if (tr_ == TransRiseFallBoth::fall())
else if (rf_ == RiseFallBoth::fall())
str += " fall";
char *result = makeTmpString(str.size() + 1);
@ -1779,7 +1779,7 @@ ExceptionThru::clone(const Network *network)
InstanceSet *insts = nullptr;
if (insts_)
insts = new InstanceSet(*insts_);
return new ExceptionThru(pins, nets, insts, tr_, true, network);
return new ExceptionThru(pins, nets, insts, rf_, true, network);
}
bool
@ -1915,7 +1915,7 @@ ExceptionThru::allPins(const Network *network,
bool
ExceptionThru::matches(const Pin *from_pin,
const Pin *to_pin,
const TransRiseFall *to_tr,
const RiseFall *to_rf,
const Network *network)
{
EdgePins edge_pins(const_cast<Pin*>(from_pin), const_cast<Pin*>(to_pin));
@ -1923,7 +1923,7 @@ ExceptionThru::matches(const Pin *from_pin,
|| (edges_ && edges_->hasKey(&edge_pins))
|| (nets_ && nets_->hasKey(network->net(to_pin)))
|| (insts_ && insts_->hasKey(network->instance(to_pin))))
&& tr_->matches(to_tr);
&& rf_->matches(to_rf);
}
void
@ -1957,7 +1957,7 @@ ExceptionThru::findHash()
}
hash_ += hash * hash_inst;
}
hash_ += tr_->index() * 13;
hash_ += rf_->index() * 13;
}
bool
@ -1967,7 +1967,7 @@ ExceptionThru::equal(ExceptionThru *thru) const
return PinSet::equal(thru->pins_, pins_)
&& NetSet::equal(thru->nets_, nets_)
&& InstanceSet::equal(thru->insts_, insts_)
&& tr_ == thru->tr_;
&& rf_ == thru->rf_;
}
int
@ -1982,7 +1982,7 @@ ExceptionThru::nameCmp(ExceptionPt *pt2,
if (net_cmp == 0) {
int inst_cmp = setNameCmp(insts_, pt2->instances(), network);
if (inst_cmp == 0)
return tr_->index() - pt2->transition()->index();
return rf_->index() - pt2->transition()->index();
else
return inst_cmp;
}
@ -2071,7 +2071,7 @@ ExceptionThru::deleteObjects(ExceptionThru *pt)
bool
ExceptionThru::intersectsPts(ExceptionThru *thru) const
{
return thru->transition() == tr_
return thru->transition() == rf_
&& ((pins_ && PinSet::intersects(pins_, thru->pins()))
|| (nets_ && NetSet::intersects(nets_, thru->nets()))
|| (insts_ && InstanceSet::intersects(insts_, thru->instances())));
@ -2210,13 +2210,13 @@ ExpandedExceptionVisitor::visitExpansions()
{
ExceptionFrom *from = exception_->from();
if (from) {
const TransRiseFallBoth *tr = from->transition();
const RiseFallBoth *rf = from->transition();
PinSet::Iterator pin_iter(from->pins());
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
PinSet pins;
pins.insert(pin);
ExceptionFrom expanded_from(&pins, nullptr, nullptr, tr, false);
ExceptionFrom expanded_from(&pins, nullptr, nullptr, rf, false);
expandThrus(&expanded_from);
}
ClockSet::Iterator clk_iter(from->clks());
@ -2224,7 +2224,7 @@ ExpandedExceptionVisitor::visitExpansions()
Clock *clk = clk_iter.next();
ClockSet clks;
clks.insert(clk);
ExceptionFrom expanded_from(nullptr, &clks, nullptr, tr, false);
ExceptionFrom expanded_from(nullptr, &clks, nullptr, rf, false);
expandThrus(&expanded_from);
}
InstanceSet::Iterator inst_iter(from->instances());
@ -2232,7 +2232,7 @@ ExpandedExceptionVisitor::visitExpansions()
Instance *inst = inst_iter.next();
InstanceSet insts;
insts.insert(inst);
ExceptionFrom expanded_from(nullptr, nullptr, &insts, tr, false);
ExceptionFrom expanded_from(nullptr, nullptr, &insts, rf, false);
expandThrus(&expanded_from);
}
}
@ -2261,13 +2261,13 @@ ExpandedExceptionVisitor::expandThru(ExceptionFrom *expanded_from,
{
if (thru_iter.hasNext()) {
ExceptionThru *thru = thru_iter.next();
const TransRiseFallBoth *tr = thru->transition();
const RiseFallBoth *rf = thru->transition();
PinSet::Iterator pin_iter(thru->pins());
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
PinSet pins;
pins.insert(pin);
ExceptionThru expanded_thru(&pins, nullptr, nullptr, tr, false, network_);
ExceptionThru expanded_thru(&pins, nullptr, nullptr, rf, false, network_);
expanded_thrus->push_back(&expanded_thru);
expandThru(expanded_from, thru_iter, expanded_thrus);
expanded_thrus->pop_back();
@ -2277,7 +2277,7 @@ ExpandedExceptionVisitor::expandThru(ExceptionFrom *expanded_from,
Net *net = net_iter.next();
NetSet nets;
nets.insert(net);
ExceptionThru expanded_thru(nullptr, &nets, nullptr, tr, false, network_);
ExceptionThru expanded_thru(nullptr, &nets, nullptr, rf, false, network_);
expanded_thrus->push_back(&expanded_thru);
expandThru(expanded_from, thru_iter, expanded_thrus);
expanded_thrus->pop_back();
@ -2287,7 +2287,7 @@ ExpandedExceptionVisitor::expandThru(ExceptionFrom *expanded_from,
Instance *inst = inst_iter.next();
InstanceSet insts;
insts.insert(inst);
ExceptionThru expanded_thru(nullptr, nullptr, &insts, tr, false, network_);
ExceptionThru expanded_thru(nullptr, nullptr, &insts, rf, false, network_);
expanded_thrus->push_back(&expanded_thru);
expandThru(expanded_from, thru_iter, expanded_thrus);
expanded_thrus->pop_back();
@ -2304,14 +2304,14 @@ ExpandedExceptionVisitor::expandTo(ExceptionFrom *expanded_from,
{
ExceptionTo *to = exception_->to();
if (to) {
const TransRiseFallBoth *tr = to->transition();
const TransRiseFallBoth *end_tr = to->endTransition();
const RiseFallBoth *rf = to->transition();
const RiseFallBoth *end_rf = to->endTransition();
PinSet::Iterator pin_iter(to->pins());
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
PinSet pins;
pins.insert(pin);
ExceptionTo expanded_to(&pins, nullptr, nullptr, tr, end_tr, false);
ExceptionTo expanded_to(&pins, nullptr, nullptr, rf, end_rf, false);
visit(expanded_from, expanded_thrus, &expanded_to);
}
ClockSet::Iterator clk_iter(to->clks());
@ -2319,7 +2319,7 @@ ExpandedExceptionVisitor::expandTo(ExceptionFrom *expanded_from,
Clock *clk = clk_iter.next();
ClockSet clks;
clks.insert(clk);
ExceptionTo expanded_to(nullptr, &clks, nullptr, tr, end_tr, false);
ExceptionTo expanded_to(nullptr, &clks, nullptr, rf, end_rf, false);
visit(expanded_from, expanded_thrus, &expanded_to);
}
InstanceSet::Iterator inst_iter(to->instances());
@ -2327,7 +2327,7 @@ ExpandedExceptionVisitor::expandTo(ExceptionFrom *expanded_from,
Instance *inst = inst_iter.next();
InstanceSet insts;
insts.insert(inst);
ExceptionTo expanded_to(nullptr, nullptr, &insts, tr, end_tr, false);
ExceptionTo expanded_to(nullptr, nullptr, &insts, rf, end_rf, false);
visit(expanded_from, expanded_thrus, &expanded_to);
}
}
@ -2356,14 +2356,14 @@ ExceptionState::setNextState(ExceptionState *next_state)
bool
ExceptionState::matchesNextThru(const Pin *from_pin,
const Pin *to_pin,
const TransRiseFall *to_tr,
const RiseFall *to_rf,
const MinMax *min_max,
const Network *network) const
{
// Don't advance the state if the exception is complete (no next_thru_).
return next_thru_
&& exception_->matches(min_max, false)
&& next_thru_->matches(from_pin, to_pin, to_tr, network);
&& next_thru_->matches(from_pin, to_pin, to_rf, network);
}
bool

39
sdc/ExceptionPath.hh
View File

@ -25,8 +25,8 @@
namespace sta {
class TransRiseFall;
class TransRiseFallBoth;
class RiseFall;
class RiseFallBoth;
class MinMaxAll;
class Network;
class Pin;
@ -67,7 +67,8 @@ public:
const MinMaxAll *minMax() const { return min_max_; }
virtual bool matches(const MinMax *min_max,
bool exact) const;
bool matchesFirstPt(const TransRiseFall *to_tr, const MinMax *min_max);
bool matchesFirstPt(const RiseFall *to_rf,
const MinMax *min_max);
ExceptionState *firstState();
virtual bool resetMatch(ExceptionFrom *from,
ExceptionThruSeq *thrus,
@ -323,13 +324,13 @@ private:
class ExceptionPt
{
public:
ExceptionPt(const TransRiseFallBoth *tr,
ExceptionPt(const RiseFallBoth *rf,
bool own_pts);
virtual ~ExceptionPt() {};
virtual bool isFrom() const { return false; }
virtual bool isThru() const { return false; }
virtual bool isTo() const { return false; }
const TransRiseFallBoth *transition() const { return tr_; }
const RiseFallBoth *transition() const { return rf_; }
virtual PinSet *pins() = 0;
virtual ClockSet *clks() = 0;
virtual InstanceSet *instances() = 0;
@ -355,7 +356,7 @@ public:
Network *network) = 0;
protected:
const TransRiseFallBoth *tr_;
const RiseFallBoth *rf_;
// True when the pin/net/inst/edge sets are owned by the exception point.
bool own_pts_;
// Hash is cached because there may be many objects to speed up
@ -378,7 +379,7 @@ class ExceptionFromTo : public ExceptionPt
public:
ExceptionFromTo(PinSet *pins, ClockSet *clks,
InstanceSet *insts,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
bool own_pts);
~ExceptionFromTo();
virtual PinSet *pins() { return pins_; }
@ -431,7 +432,7 @@ public:
ExceptionFrom(PinSet *pins,
ClockSet *clks,
InstanceSet *insts,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
bool own_pts);
ExceptionFrom *clone();
virtual bool isFrom() const { return true; }
@ -453,39 +454,39 @@ public:
ClockSet *clks,
InstanceSet *insts,
// -to|-rise_to|-fall_to
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
// -rise|-fall endpoint transition.
const TransRiseFallBoth *end_tr,
const RiseFallBoth *end_rf,
bool own_pts);
ExceptionTo *clone();
virtual bool isTo() const { return true; }
const char *asString(const Network *network) const;
const TransRiseFallBoth *endTransition() { return end_tr_; }
const RiseFallBoth *endTransition() { return end_rf_; }
bool intersectsPts(ExceptionTo *to) const;
virtual int typePriority() const { return 1; }
bool matches(const Pin *pin,
const ClockEdge *clk_edge,
const TransRiseFall *end_tr,
const RiseFall *end_rf,
const Network *network) const;
bool matches(const Pin *pin,
const TransRiseFall *end_tr) const;
const RiseFall *end_rf) const;
bool matches(const Clock *clk) const;
bool matchesFilter(const Pin *pin,
const ClockEdge *clk_edge,
const TransRiseFall *end_tr,
const RiseFall *end_rf,
const Network *network) const;
virtual int nameCmp(ExceptionPt *pt, const Network *network) const;
protected:
bool matches(const Pin *pin,
const ClockEdge *clk_edge,
const TransRiseFall *end_tr,
const RiseFall *end_rf,
bool inst_matches_reg_clk_pin,
const Network *network) const;
virtual const char *cmdKeyword() const;
// -rise|-fall endpoint transition.
const TransRiseFallBoth *end_tr_;
const RiseFallBoth *end_rf_;
private:
DISALLOW_COPY_AND_ASSIGN(ExceptionTo);
@ -497,7 +498,7 @@ public:
ExceptionThru(PinSet *pins,
NetSet *nets,
InstanceSet *insts,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
bool own_pts,
const Network *network);
~ExceptionThru();
@ -515,7 +516,7 @@ public:
PinSet *pins);
bool matches(const Pin *from_pin,
const Pin *to_pin,
const TransRiseFall *to_tr,
const RiseFall *to_rf,
const Network *network);
bool equal(ExceptionThru *thru) const;
virtual int nameCmp(ExceptionPt *pt,
@ -637,7 +638,7 @@ public:
ExceptionPath *exception() { return exception_; }
bool matchesNextThru(const Pin *from_pin,
const Pin *to_pin,
const TransRiseFall *to_tr,
const RiseFall *to_rf,
const MinMax *min_max,
const Network *network) const;
bool isComplete() const;

60
sdc/InputDrive.cc
View File

@ -21,7 +21,7 @@ namespace sta {
InputDrive::InputDrive()
{
for (auto tr_index : TransRiseFall::rangeIndex()) {
for (auto tr_index : RiseFall::rangeIndex()) {
for (auto mm_index : MinMax::rangeIndex())
drive_cells_[tr_index][mm_index] = nullptr;
}
@ -29,7 +29,7 @@ InputDrive::InputDrive()
InputDrive::~InputDrive()
{
for (auto tr_index : TransRiseFall::rangeIndex()) {
for (auto tr_index : RiseFall::rangeIndex()) {
for (auto mm_index : MinMax::rangeIndex()) {
InputDriveCell *drive_cell = drive_cells_[tr_index][mm_index];
delete drive_cell;
@ -38,43 +38,43 @@ InputDrive::~InputDrive()
}
void
InputDrive::setSlew(const TransRiseFallBoth *tr,
InputDrive::setSlew(const RiseFallBoth *rf,
const MinMaxAll *min_max,
float slew)
{
slews_.setValue(tr, min_max, slew);
slews_.setValue(rf, min_max, slew);
}
void
InputDrive::setDriveResistance(const TransRiseFallBoth *tr,
InputDrive::setDriveResistance(const RiseFallBoth *rf,
const MinMaxAll *min_max,
float res)
{
drive_resistances_.setValue(tr, min_max, res);
drive_resistances_.setValue(rf, min_max, res);
}
void
InputDrive::driveResistance(const TransRiseFall *tr,
InputDrive::driveResistance(const RiseFall *rf,
const MinMax *min_max,
float &res,
bool &exists)
{
drive_resistances_.value(tr, min_max, res, exists);
drive_resistances_.value(rf, min_max, res, exists);
}
bool
InputDrive::hasDriveResistance(const TransRiseFall *tr, const MinMax *min_max)
InputDrive::hasDriveResistance(const RiseFall *rf, const MinMax *min_max)
{
return drive_resistances_.hasValue(tr, min_max);
return drive_resistances_.hasValue(rf, min_max);
}
bool
InputDrive::driveResistanceMinMaxEqual(const TransRiseFall *tr)
InputDrive::driveResistanceMinMaxEqual(const RiseFall *rf)
{
float min_res, max_res;
bool min_exists, max_exists;
drive_resistances_.value(tr, MinMax::min(), min_res, min_exists);
drive_resistances_.value(tr, MinMax::max(), max_res, max_exists);
drive_resistances_.value(rf, MinMax::min(), min_res, min_exists);
drive_resistances_.value(rf, MinMax::max(), max_res, max_exists);
return min_exists && max_exists && min_res == max_res;
}
@ -84,12 +84,12 @@ InputDrive::setDriveCell(LibertyLibrary *library,
LibertyPort *from_port,
float *from_slews,
LibertyPort *to_port,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const MinMaxAll *min_max)
{
for (auto tr_index : tr->rangeIndex()) {
for (auto rf_index : rf->rangeIndex()) {
for (auto mm_index : min_max->rangeIndex()) {
InputDriveCell *drive = drive_cells_[tr_index][mm_index];
InputDriveCell *drive = drive_cells_[rf_index][mm_index];
if (drive) {
drive->setLibrary(library);
drive->setCell(cell);
@ -100,21 +100,21 @@ InputDrive::setDriveCell(LibertyLibrary *library,
else {
drive = new InputDriveCell(library, cell, from_port,
from_slews, to_port);
drive_cells_[tr_index][mm_index] = drive;
drive_cells_[rf_index][mm_index] = drive;
}
}
}
}
void
InputDrive::driveCell(const TransRiseFall *tr,
InputDrive::driveCell(const RiseFall *rf,
const MinMax *min_max,
LibertyCell *&cell,
LibertyPort *&from_port,
float *&from_slews,
LibertyPort *&to_port)
{
InputDriveCell *drive = drive_cells_[tr->index()][min_max->index()];
InputDriveCell *drive = drive_cells_[rf->index()][min_max->index()];
if (drive) {
cell = drive->cell();
from_port = drive->fromPort();
@ -126,24 +126,24 @@ InputDrive::driveCell(const TransRiseFall *tr,
}
InputDriveCell *
InputDrive::driveCell(const TransRiseFall *tr,
InputDrive::driveCell(const RiseFall *rf,
const MinMax *min_max)
{
return drive_cells_[tr->index()][min_max->index()];
return drive_cells_[rf->index()][min_max->index()];
}
bool
InputDrive::hasDriveCell(const TransRiseFall *tr,
InputDrive::hasDriveCell(const RiseFall *rf,
const MinMax *min_max)
{
return drive_cells_[tr->index()][min_max->index()] != nullptr;
return drive_cells_[rf->index()][min_max->index()] != nullptr;
}
bool
InputDrive::driveCellsEqual()
{
int rise_index = TransRiseFall::riseIndex();
int fall_index = TransRiseFall::fallIndex();
int rise_index = RiseFall::riseIndex();
int fall_index = RiseFall::fallIndex();
int min_index = MinMax::minIndex();
int max_index = MinMax::maxIndex();
InputDriveCell *drive1 = drive_cells_[rise_index][min_index];
@ -156,12 +156,12 @@ InputDrive::driveCellsEqual()
}
void
InputDrive::slew(const TransRiseFall *tr,
InputDrive::slew(const RiseFall *rf,
const MinMax *min_max,
float &slew,
bool &exists)
{
slews_.value(tr, min_max, slew, exists);
slews_.value(rf, min_max, slew, exists);
}
////////////////////////////////////////////////////////////////
@ -206,15 +206,15 @@ InputDriveCell::setToPort(LibertyPort *to_port)
void
InputDriveCell::setFromSlews(float *from_slews)
{
for (auto tr_index : TransRiseFall::rangeIndex())
for (auto tr_index : RiseFall::rangeIndex())
from_slews_[tr_index] = from_slews[tr_index];
}
bool
InputDriveCell::equal(InputDriveCell *drive) const
{
int rise_index = TransRiseFall::riseIndex();
int fall_index = TransRiseFall::fallIndex();
int rise_index = RiseFall::riseIndex();
int fall_index = RiseFall::fallIndex();
return cell_ == drive->cell_
&& from_port_ == drive->from_port_
&& from_slews_[rise_index] == drive->from_slews_[rise_index]

24
sdc/InputDrive.hh
View File

@ -36,39 +36,39 @@ class InputDrive
public:
explicit InputDrive();
~InputDrive();
void setSlew(const TransRiseFallBoth *tr,
void setSlew(const RiseFallBoth *rf,
const MinMaxAll *min_max,
float slew);
void setDriveResistance(const TransRiseFallBoth *tr,
void setDriveResistance(const RiseFallBoth *rf,
const MinMaxAll *min_max,
float res);
void driveResistance(const TransRiseFall *tr,
void driveResistance(const RiseFall *rf,
const MinMax *min_max,
float &res,
bool &exists);
bool hasDriveResistance(const TransRiseFall *tr,
bool hasDriveResistance(const RiseFall *rf,
const MinMax *min_max);
bool driveResistanceMinMaxEqual(const TransRiseFall *tr);
bool driveResistanceMinMaxEqual(const RiseFall *rf);
void setDriveCell(LibertyLibrary *library,
LibertyCell *cell,
LibertyPort *from_port,
float *from_slews,
LibertyPort *to_port,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const MinMaxAll *min_max);
void driveCell(const TransRiseFall *tr,
void driveCell(const RiseFall *rf,
const MinMax *min_max,
LibertyCell *&cell,
LibertyPort *&from_port,
float *&from_slews,
LibertyPort *&to_port);
InputDriveCell *driveCell(const TransRiseFall *tr,
InputDriveCell *driveCell(const RiseFall *rf,
const MinMax *min_max);
bool hasDriveCell(const TransRiseFall *tr,
bool hasDriveCell(const RiseFall *rf,
const MinMax *min_max);
// True if rise/fall/min/max drive cells are equal.
bool driveCellsEqual();
void slew(const TransRiseFall *tr,
void slew(const RiseFall *rf,
const MinMax *min_max,
float &slew,
bool &exists);
@ -80,7 +80,7 @@ private:
RiseFallMinMax slews_;
RiseFallMinMax drive_resistances_;
// Separate rise/fall/min/max drive cells.
InputDriveCell *drive_cells_[TransRiseFall::index_count][MinMax::index_count];
InputDriveCell *drive_cells_[RiseFall::index_count][MinMax::index_count];
};
class InputDriveCell
@ -109,7 +109,7 @@ private:
LibertyLibrary *library_;
LibertyCell *cell_;
LibertyPort *from_port_;
float from_slews_[TransRiseFall::index_count];
float from_slews_[RiseFall::index_count];
LibertyPort *to_port_;
};

4
sdc/PortDelay.cc
View File

@ -66,14 +66,14 @@ PortDelay::setNetworkLatencyIncluded(bool included)
network_latency_included_ = included;
}
TransRiseFall *
RiseFall *
PortDelay::refTransition() const
{
// Reference pin transition is the clock transition.
if (clk_edge_)
return clk_edge_->transition();
else
return TransRiseFall::rise();
return RiseFall::rise();
}
InputDelay::InputDelay(Pin *pin,

2
sdc/PortDelay.hh
View File

@ -41,7 +41,7 @@ public:
bool networkLatencyIncluded() const;
void setNetworkLatencyIncluded(bool included);
Pin *refPin() const { return ref_pin_; }
TransRiseFall *refTransition() const;
RiseFall *refTransition() const;
protected:
PortDelay(Pin *pin,

16
sdc/PortExtCap.cc
View File

@ -25,39 +25,39 @@ PortExtCap::PortExtCap(Port *port) :
}
void
PortExtCap::pinCap(const TransRiseFall *tr,
PortExtCap::pinCap(const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &cap,
bool &exists)
{
pin_cap_.value(tr, min_max, cap, exists);
pin_cap_.value(rf, min_max, cap, exists);
}
void
PortExtCap::setPinCap(float cap,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max)
{
pin_cap_.setValue(tr, min_max, cap);
pin_cap_.setValue(rf, min_max, cap);
}
void
PortExtCap::wireCap(const TransRiseFall *tr,
PortExtCap::wireCap(const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &cap,
bool &exists)
{
wire_cap_.value(tr, min_max, cap, exists);
wire_cap_.value(rf, min_max, cap, exists);
}
void
PortExtCap::setWireCap(float cap,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max)
{
wire_cap_.setValue(tr, min_max, cap);
wire_cap_.setValue(rf, min_max, cap);
}
void

8
sdc/PortExtCap.hh
View File

@ -34,21 +34,21 @@ class PortExtCap
public:
explicit PortExtCap(Port *port);
Port *port() { return port_; }
void pinCap(const TransRiseFall *tr,
void pinCap(const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &cap, bool &exists);
RiseFallMinMax *pinCap() { return &pin_cap_; }
void setPinCap(float cap,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max);
void wireCap(const TransRiseFall *tr,
void wireCap(const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &cap, bool &exists);
RiseFallMinMax *wireCap() { return &wire_cap_; }
void setWireCap(float cap,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max);
void setFanout(int fanout,
const MinMax *min_max);

114
sdc/RiseFallMinMax.cc
View File

@ -27,7 +27,7 @@ RiseFallMinMax::RiseFallMinMax()
void
RiseFallMinMax::clear()
{
for (int tr_index=0; tr_index<TransRiseFall::index_count; tr_index++) {
for (int tr_index=0; tr_index<RiseFall::index_count; tr_index++) {
for (int mm_index = 0; mm_index < MinMax::index_count; mm_index++) {
exists_[tr_index][mm_index] = false;
}
@ -36,7 +36,7 @@ RiseFallMinMax::clear()
RiseFallMinMax::RiseFallMinMax(float init_value)
{
for (int tr_index=0;tr_index<TransRiseFall::index_count;tr_index++) {
for (int tr_index=0;tr_index<RiseFall::index_count;tr_index++) {
for (int mm_index = 0; mm_index < MinMax::index_count; mm_index++) {
values_[tr_index][mm_index] = init_value;
exists_[tr_index][mm_index] = true;
@ -46,7 +46,7 @@ RiseFallMinMax::RiseFallMinMax(float init_value)
RiseFallMinMax::RiseFallMinMax(const RiseFallMinMax *rfmm)
{
for (int tr_index=0;tr_index<TransRiseFall::index_count;tr_index++) {
for (int tr_index=0;tr_index<RiseFall::index_count;tr_index++) {
for (int mm_index = 0; mm_index < MinMax::index_count; mm_index++) {
values_[tr_index][mm_index] = rfmm->values_[tr_index][mm_index];
exists_[tr_index][mm_index] = rfmm->exists_[tr_index][mm_index];
@ -57,105 +57,105 @@ RiseFallMinMax::RiseFallMinMax(const RiseFallMinMax *rfmm)
void
RiseFallMinMax::setValue(float value)
{
setValue(TransRiseFallBoth::riseFall(), MinMaxAll::all(), value);
setValue(RiseFallBoth::riseFall(), MinMaxAll::all(), value);
}
void
RiseFallMinMax::setValue(const TransRiseFallBoth *tr,
RiseFallMinMax::setValue(const RiseFallBoth *rf,
const MinMaxAll *min_max,
float value)
{
for (auto tr_index : tr->rangeIndex()) {
for (auto rf_index : rf->rangeIndex()) {
for (auto mm_index : min_max->rangeIndex()) {
values_[tr_index][mm_index] = value;
exists_[tr_index][mm_index] = true;
values_[rf_index][mm_index] = value;
exists_[rf_index][mm_index] = true;
}
}
}
void
RiseFallMinMax::removeValue(const TransRiseFallBoth *tr,
RiseFallMinMax::removeValue(const RiseFallBoth *rf,
const MinMax *min_max)
{
int mm_index = min_max->index();
for (auto tr_index : tr->rangeIndex())
exists_[tr_index][mm_index] = false;
for (auto rf_index : rf->rangeIndex())
exists_[rf_index][mm_index] = false;
}
void
RiseFallMinMax::removeValue(const TransRiseFallBoth *tr,
RiseFallMinMax::removeValue(const RiseFallBoth *rf,
const MinMaxAll *min_max)
{
for (auto mm : min_max->range())
removeValue(tr, mm);
removeValue(rf, mm);
}
void
RiseFallMinMax::mergeValue(const TransRiseFallBoth *tr,
RiseFallMinMax::mergeValue(const RiseFallBoth *rf,
const MinMaxAll *min_max,
float value)
{
for (auto tr_index : tr->rangeIndex()) {
for (auto rf_index : rf->rangeIndex()) {
for (auto mm : min_max->range()) {
int mm_index = mm->index();
if (!exists_[tr_index][mm_index]
|| mm->compare(value, values_[tr_index][mm_index])) {
values_[tr_index][mm_index] = value;
exists_[tr_index][mm_index] = true;
if (!exists_[rf_index][mm_index]
|| mm->compare(value, values_[rf_index][mm_index])) {
values_[rf_index][mm_index] = value;
exists_[rf_index][mm_index] = true;
}
}
}
}
void
RiseFallMinMax::setValue(const TransRiseFallBoth *tr,
RiseFallMinMax::setValue(const RiseFallBoth *rf,
const MinMax *min_max,
float value)
{
int mm_index = min_max->index();
for (auto tr_index : tr->rangeIndex()) {
values_[tr_index][mm_index] = value;
exists_[tr_index][mm_index] = true;
for (auto rf_index : rf->rangeIndex()) {
values_[rf_index][mm_index] = value;
exists_[rf_index][mm_index] = true;
}
}
void
RiseFallMinMax::setValue(const TransRiseFall *tr,
RiseFallMinMax::setValue(const RiseFall *rf,
const MinMax *min_max,
float value)
{
int tr_index = tr->index();
int rf_index = rf->index();
int mm_index = min_max->index();
values_[tr_index][mm_index] = value;
exists_[tr_index][mm_index] = true;
values_[rf_index][mm_index] = value;
exists_[rf_index][mm_index] = true;
}
void
RiseFallMinMax::setValues(RiseFallMinMax *values)
{
for (int tr_index=0;tr_index<TransRiseFall::index_count;tr_index++) {
for (int rf_index=0;rf_index<RiseFall::index_count;rf_index++) {
for (int mm_index = 0; mm_index < MinMax::index_count; mm_index++) {
values_[tr_index][mm_index] = values->values_[tr_index][mm_index];
exists_[tr_index][mm_index] = values->exists_[tr_index][mm_index];
values_[rf_index][mm_index] = values->values_[rf_index][mm_index];
exists_[rf_index][mm_index] = values->exists_[rf_index][mm_index];
}
}
}
void
RiseFallMinMax::value(const TransRiseFall *tr,
RiseFallMinMax::value(const RiseFall *rf,
const MinMax *min_max,
float &value, bool &exists) const
{
exists = exists_[tr->index()][min_max->index()];
exists = exists_[rf->index()][min_max->index()];
if (exists)
value = values_[tr->index()][min_max->index()];
value = values_[rf->index()][min_max->index()];
}
float
RiseFallMinMax::value(const TransRiseFall *tr,
RiseFallMinMax::value(const RiseFall *rf,
const MinMax *min_max) const
{
return values_[tr->index()][min_max->index()];
return values_[rf->index()][min_max->index()];
}
bool
@ -167,9 +167,9 @@ RiseFallMinMax::hasValue() const
bool
RiseFallMinMax::empty() const
{
for (int tr_index=0;tr_index<TransRiseFall::index_count;tr_index++) {
for (int rf_index=0;rf_index<RiseFall::index_count;rf_index++) {
for (int mm_index = 0; mm_index < MinMax::index_count; mm_index++) {
if (exists_[tr_index][mm_index])
if (exists_[rf_index][mm_index])
return false;
}
}
@ -177,9 +177,9 @@ RiseFallMinMax::empty() const
}
bool
RiseFallMinMax::hasValue(const TransRiseFall *tr, const MinMax *min_max) const
RiseFallMinMax::hasValue(const RiseFall *rf, const MinMax *min_max) const
{
return exists_[tr->index()][min_max->index()];
return exists_[rf->index()][min_max->index()];
}
void
@ -187,17 +187,17 @@ RiseFallMinMax::mergeWith(RiseFallMinMax *rfmm)
{
for (auto min_max : MinMax::range()) {
int mm_index = min_max->index();
for (auto tr_index : TransRiseFall::rangeIndex()) {
bool exists1 = exists_[tr_index][mm_index];
bool exists2 = rfmm->exists_[tr_index][mm_index];
for (auto rf_index : RiseFall::rangeIndex()) {
bool exists1 = exists_[rf_index][mm_index];
bool exists2 = rfmm->exists_[rf_index][mm_index];
if (exists1 && exists2) {
float rfmm_value = rfmm->values_[tr_index][mm_index];
if (min_max->compare(rfmm_value, values_[tr_index][mm_index]))
values_[tr_index][mm_index] = rfmm_value;
float rfmm_value = rfmm->values_[rf_index][mm_index];
if (min_max->compare(rfmm_value, values_[rf_index][mm_index]))
values_[rf_index][mm_index] = rfmm_value;
}
else if (!exists1 && exists2) {
values_[tr_index][mm_index] = rfmm->values_[tr_index][mm_index];
exists_[tr_index][mm_index] = true;
values_[rf_index][mm_index] = rfmm->values_[rf_index][mm_index];
exists_[rf_index][mm_index] = true;
}
}
}
@ -206,14 +206,14 @@ RiseFallMinMax::mergeWith(RiseFallMinMax *rfmm)
bool
RiseFallMinMax::equal(const RiseFallMinMax *values) const
{
for (int tr_index=0;tr_index<TransRiseFall::index_count;tr_index++) {
for (int rf_index=0;rf_index<RiseFall::index_count;rf_index++) {
for (int mm_index = 0; mm_index < MinMax::index_count; mm_index++) {
bool exists1 = exists_[tr_index][mm_index];
bool exists2 = values->exists_[tr_index][mm_index];
bool exists1 = exists_[rf_index][mm_index];
bool exists2 = values->exists_[rf_index][mm_index];
if (exists1 != exists2)
return false;
if (exists1 && exists2
&& values_[tr_index][mm_index] != values->values_[tr_index][mm_index])
&& values_[rf_index][mm_index] != values->values_[rf_index][mm_index])
return false;
}
}
@ -232,10 +232,10 @@ RiseFallMinMax::isOneValue(float &value) const
{
if (exists_[0][0]) {
value = values_[0][0];
for (int tr_index=0;tr_index<TransRiseFall::index_count;tr_index++) {
for (int rf_index=0;rf_index<RiseFall::index_count;rf_index++) {
for (int mm_index=0; mm_index<MinMax::index_count;mm_index++) {
if (!exists_[tr_index][mm_index]
|| values_[tr_index][mm_index] != value)
if (!exists_[rf_index][mm_index]
|| values_[rf_index][mm_index] != value)
return false;
}
}
@ -253,9 +253,9 @@ RiseFallMinMax::isOneValue(const MinMax *min_max,
int mm_index = min_max->index();
if (exists_[0][mm_index]) {
value = values_[0][mm_index];
for (int tr_index=0;tr_index<TransRiseFall::index_count;tr_index++) {
if (!exists_[tr_index][mm_index]
|| values_[tr_index][mm_index] != value)
for (int rf_index=0;rf_index<RiseFall::index_count;rf_index++) {
if (!exists_[rf_index][mm_index]
|| values_[rf_index][mm_index] != value)
return false;
}
return true;

22
sdc/RiseFallMinMax.hh
View File

@ -30,32 +30,32 @@ public:
RiseFallMinMax();
RiseFallMinMax(const RiseFallMinMax *rfmm);
explicit RiseFallMinMax(float init_value);
float value(const TransRiseFall *tr,
float value(const RiseFall *rf,
const MinMax *min_max) const;
void value(const TransRiseFall *tr,
void value(const RiseFall *rf,
const MinMax *min_max,
float &value,
bool &exists) const;
bool hasValue() const;
bool empty() const;
bool hasValue(const TransRiseFall *tr,
bool hasValue(const RiseFall *rf,
const MinMax *min_max) const;
void setValue(const TransRiseFallBoth *tr,
void setValue(const RiseFallBoth *rf,
const MinMaxAll *min_max,
float value);
void setValue(const TransRiseFallBoth *tr,
void setValue(const RiseFallBoth *rf,
const MinMax *min_max,
float value);
void setValue(const TransRiseFall *tr,
void setValue(const RiseFall *rf,
const MinMax *min_max, float value);
void setValue(float value);
void mergeValue(const TransRiseFallBoth *tr,
void mergeValue(const RiseFallBoth *rf,
const MinMaxAll *min_max,
float value);
void setValues(RiseFallMinMax *values);
void removeValue(const TransRiseFallBoth *tr,
void removeValue(const RiseFallBoth *rf,
const MinMax *min_max);
void removeValue(const TransRiseFallBoth *tr,
void removeValue(const RiseFallBoth *rf,
const MinMaxAll *min_max);
// Merge all values of rfmm.
void mergeWith(RiseFallMinMax *rfmm);
@ -68,8 +68,8 @@ public:
float &value) const;
private:
float values_[TransRiseFall::index_count][MinMax::index_count];
bool exists_[TransRiseFall::index_count][MinMax::index_count];
float values_[RiseFall::index_count][MinMax::index_count];
bool exists_[RiseFall::index_count][MinMax::index_count];
};
} // namespace

44
sdc/RiseFallValues.cc
View File

@ -27,13 +27,13 @@ RiseFallValues::RiseFallValues()
void
RiseFallValues::clear()
{
for (auto tr_index : TransRiseFall::rangeIndex())
for (auto tr_index : RiseFall::rangeIndex())
exists_[tr_index] = false;
}
RiseFallValues::RiseFallValues(float init_value)
{
for (auto tr_index : TransRiseFall::rangeIndex()) {
for (auto tr_index : RiseFall::rangeIndex()) {
values_[tr_index] = init_value;
exists_[tr_index] = true;
}
@ -42,57 +42,57 @@ RiseFallValues::RiseFallValues(float init_value)
void
RiseFallValues::setValue(float value)
{
setValue(TransRiseFallBoth::riseFall(), value);
setValue(RiseFallBoth::riseFall(), value);
}
void
RiseFallValues::setValue(const TransRiseFallBoth *tr,
RiseFallValues::setValue(const RiseFallBoth *rf,
float value)
{
for (auto tr_index : tr->rangeIndex()) {
values_[tr_index] = value;
exists_[tr_index] = true;
for (auto rf_index : rf->rangeIndex()) {
values_[rf_index] = value;
exists_[rf_index] = true;
}
}
void
RiseFallValues::setValue(const TransRiseFall *tr,
RiseFallValues::setValue(const RiseFall *rf,
float value)
{
int tr_index = tr->index();
values_[tr_index] = value;
exists_[tr_index] = true;
int rf_index = rf->index();
values_[rf_index] = value;
exists_[rf_index] = true;
}
void
RiseFallValues::setValues(RiseFallValues *values)
{
for (auto tr_index : TransRiseFall::rangeIndex()) {
values_[tr_index] = values->values_[tr_index];
exists_[tr_index] = values->exists_[tr_index];
for (auto rf_index : RiseFall::rangeIndex()) {
values_[rf_index] = values->values_[rf_index];
exists_[rf_index] = values->exists_[rf_index];
}
}
void
RiseFallValues::value(const TransRiseFall *tr,
RiseFallValues::value(const RiseFall *rf,
float &value, bool &exists) const
{
int tr_index = tr->index();
exists = exists_[tr_index];
int rf_index = rf->index();
exists = exists_[rf_index];
if (exists)
value = values_[tr_index];
value = values_[rf_index];
}
float
RiseFallValues::value(const TransRiseFall *tr) const
RiseFallValues::value(const RiseFall *rf) const
{
return values_[tr->index()];
return values_[rf->index()];
}
bool
RiseFallValues::hasValue(const TransRiseFall *tr) const
RiseFallValues::hasValue(const RiseFall *rf) const
{
return exists_[tr->index()];
return exists_[rf->index()];
}
} // namespace

14
sdc/RiseFallValues.hh
View File

@ -28,12 +28,12 @@ class RiseFallValues
public:
RiseFallValues();
explicit RiseFallValues(float init_value);
float value(const TransRiseFall *tr) const;
void value(const TransRiseFall *tr,
float value(const RiseFall *rf) const;
void value(const RiseFall *rf,
float &value, bool &exists) const;
bool hasValue(const TransRiseFall *tr) const;
void setValue(const TransRiseFallBoth *tr, float value);
void setValue(const TransRiseFall *tr, float value);
bool hasValue(const RiseFall *rf) const;
void setValue(const RiseFallBoth *rf, float value);
void setValue(const RiseFall *rf, float value);
void setValue(float value);
void setValues(RiseFallValues *values);
void clear();
@ -41,8 +41,8 @@ public:
private:
DISALLOW_COPY_AND_ASSIGN(RiseFallValues);
float values_[TransRiseFall::index_count];
bool exists_[TransRiseFall::index_count];
float values_[RiseFall::index_count];
bool exists_[RiseFall::index_count];
};
} // namespace

392
sdc/Sdc.cc
View File

File diff suppressed because it is too large Load Diff

172
sdc/Sdc.hh
View File

@ -197,42 +197,42 @@ public:
const MinMax *min_max);
void setTimingDerate(TimingDerateType type,
PathClkOrData clk_data,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const EarlyLate *early_late,
float derate);
// Delay type is always net for net derating.
void setTimingDerate(const Net *net,
PathClkOrData clk_data,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const EarlyLate *early_late,
float derate);
void setTimingDerate(const Instance *inst,
TimingDerateType type,
PathClkOrData clk_data,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const EarlyLate *early_late,
float derate);
void setTimingDerate(const LibertyCell *cell,
TimingDerateType type,
PathClkOrData clk_data,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const EarlyLate *early_late,
float derate);
float timingDerateInstance(const Pin *pin,
TimingDerateType type,
PathClkOrData clk_data,
const TransRiseFall *tr,
const RiseFall *rf,
const EarlyLate *early_late) const;
float timingDerateNet(const Pin *pin,
PathClkOrData clk_data,
const TransRiseFall *tr,
const RiseFall *rf,
const EarlyLate *early_late) const;
void unsetTimingDerate();
void setInputSlew(Port *port, const TransRiseFallBoth *tr,
void setInputSlew(Port *port, const RiseFallBoth *rf,
const MinMaxAll *min_max, float slew);
// Set the rise/fall drive resistance on design port.
void setDriveResistance(Port *port,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const MinMaxAll *min_max,
float res);
// Set the drive on design port using external cell timing arcs of
@ -243,7 +243,7 @@ public:
LibertyPort *from_port,
float *from_slews,
LibertyPort *to_port,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const MinMaxAll *min_max);
void setLatchBorrowLimit(Pin *pin,
float limit);
@ -259,31 +259,31 @@ public:
// Return values.
float &limit,
bool &exists);
void setMinPulseWidth(const TransRiseFallBoth *tr,
void setMinPulseWidth(const RiseFallBoth *rf,
float min_width);
void setMinPulseWidth(const Pin *pin,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
float min_width);
void setMinPulseWidth(const Instance *inst,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
float min_width);
void setMinPulseWidth(const Clock *clk,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
float min_width);
// Return min pulse with respecting precidence.
void minPulseWidth(const Pin *pin,
const Clock *clk,
const TransRiseFall *hi_low,
const RiseFall *hi_low,
float &min_width,
bool &exists) const;
void setSlewLimit(Clock *clk,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const PathClkOrData clk_data,
const MinMax *min_max,
float slew);
bool haveClkSlewLimits() const;
void slewLimit(Clock *clk,
const TransRiseFall *tr,
const RiseFall *rf,
const PathClkOrData clk_data,
const MinMax *min_max,
float &slew,
@ -385,14 +385,14 @@ public:
void removePropagatedClock(Pin *pin);
bool isPropagatedClock(const Pin *pin);
void setClockSlew(Clock *clk,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const MinMaxAll *min_max,
float slew);
void removeClockSlew(Clock *clk);
// Latency can be on a clk, pin, or clk/pin combination.
void setClockLatency(Clock *clk,
Pin *pin,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const MinMaxAll *min_max,
float delay);
void removeClockLatency(const Clock *clk,
@ -400,7 +400,7 @@ public:
ClockLatency *clockLatency(Edge *edge) const;
bool hasClockLatency(const Pin *pin) const;
void clockLatency(Edge *edge,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &latency,
@ -411,30 +411,30 @@ public:
// This does NOT check for latency on clk (without pin).
void clockLatency(const Clock *clk,
const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &latency,
bool &exists) const;
void clockLatency(const Clock *clk,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &latency,
bool &exists) const;
float clockLatency(const Clock *clk,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max) const;
// Clock insertion delay (set_clk_latency -source).
// Insertion delay can be on a clk, pin, or clk/pin combination.
void setClockInsertion(const Clock *clk,
const Pin *pin,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const MinMaxAll *min_max,
const EarlyLateAll *early_late,
float delay);
void setClockInsertion(const Clock *clk, const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max,
const EarlyLate *early_late,
float delay);
@ -442,13 +442,13 @@ public:
const Pin *pin);
bool hasClockInsertion(const Pin *pin) const;
float clockInsertion(const Clock *clk,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max,
const EarlyLate *early_late) const;
// Respects precedence of pin/clk and set_input_delay on clk pin.
void clockInsertion(const Clock *clk,
const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max,
const EarlyLate *early_late,
// Return values.
@ -462,15 +462,15 @@ public:
virtual void removeClockUncertainty(Pin *pin,
const SetupHoldAll *setup_hold);
virtual void setClockUncertainty(Clock *from_clk,
const TransRiseFallBoth *from_tr,
const RiseFallBoth *from_rf,
Clock *to_clk,
const TransRiseFallBoth *to_tr,
const RiseFallBoth *to_rf,
const SetupHoldAll *setup_hold,
float uncertainty);
virtual void removeClockUncertainty(Clock *from_clk,
const TransRiseFallBoth *from_tr,
const RiseFallBoth *from_rf,
Clock *to_clk,
const TransRiseFallBoth *to_tr,
const RiseFallBoth *to_rf,
const SetupHoldAll *setup_hold);
ClockGroups *makeClockGroups(const char *name,
bool logically_exclusive,
@ -498,78 +498,78 @@ public:
const Clock *clk) const;
bool clkStopPropagation(const Clock *clk,
const Pin *from_pin,
const TransRiseFall *from_tr,
const RiseFall *from_rf,
const Pin *to_pin,
const TransRiseFall *to_tr) const;
void setClockGatingCheck(const TransRiseFallBoth *tr,
const RiseFall *to_rf) const;
void setClockGatingCheck(const RiseFallBoth *rf,
const SetupHold *setup_hold,
float margin);
void setClockGatingCheck(Instance *inst,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const SetupHold *setup_hold,
float margin,
LogicValue active_value);
void setClockGatingCheck(Clock *clk,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const SetupHold *setup_hold,
float margin);
void setClockGatingCheck(const Pin *pin,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const SetupHold *setup_hold,
float margin,
LogicValue active_value);
void setDataCheck(Pin *from,
const TransRiseFallBoth *from_tr,
const RiseFallBoth *from_rf,
Pin *to,
const TransRiseFallBoth *to_tr,
const RiseFallBoth *to_rf,
Clock *clk,
const SetupHoldAll *setup_hold,
float margin);
void removeDataCheck(Pin *from,
const TransRiseFallBoth *from_tr,
const RiseFallBoth *from_rf,
Pin *to,
const TransRiseFallBoth *to_tr,
const RiseFallBoth *to_rf,
Clock *clk,
const SetupHoldAll *setup_hold);
DataCheckSet *dataChecksFrom(const Pin *from) const;
DataCheckSet *dataChecksTo(const Pin *to) const;
void setInputDelay(Pin *pin,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
Clock *clk,
const TransRiseFall *clk_tr,
const RiseFall *clk_rf,
Pin *ref_pin,
bool source_latency_included,
bool network_latency_included,
const MinMaxAll *min_max,
bool add, float delay);
void removeInputDelay(Pin *pin,
TransRiseFallBoth *tr,
RiseFallBoth *rf,
Clock *clk,
TransRiseFall *clk_tr,
RiseFall *clk_rf,
MinMaxAll *min_max);
void setOutputDelay(Pin *pin,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
Clock *clk,
const TransRiseFall *clk_tr,
const RiseFall *clk_tr,
Pin *ref_pin,
bool source_latency_included,
bool network_latency_included,
const MinMaxAll *min_max,
bool add, float delay);
void removeOutputDelay(Pin *pin,
TransRiseFallBoth *tr,
RiseFallBoth *rf,
Clock *clk,
TransRiseFall *clk_tr,
RiseFall *clk_rf,
MinMaxAll *min_max);
// Set port external pin load (set_load -pin_load port).
void setPortExtPinCap(Port *port,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max,
float cap);
// Set port external wire load (set_load -wire port).
void setPortExtWireCap(Port *port,
bool subtract_pin_cap,
const TransRiseFall *tr,
const RiseFall *rf,
const Corner *corner,
const MinMax *min_max,
float cap);
@ -594,7 +594,7 @@ public:
bool &exists) const;
// Pin capacitance derated by operating conditions and instance pvt.
float pinCapacitance(const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *min_max);
@ -733,19 +733,19 @@ public:
ExceptionFrom *makeExceptionFrom(PinSet *from_pins,
ClockSet *from_clks,
InstanceSet *from_insts,
const TransRiseFallBoth *from_tr);
const RiseFallBoth *from_rf);
// Make an exception -through specification.
ExceptionThru *makeExceptionThru(PinSet *pins,
NetSet *nets,
InstanceSet *insts,
const TransRiseFallBoth *tr);
const RiseFallBoth *rf);
bool exceptionToInvalid(const Pin *pin);
// Make an exception -to specification.
ExceptionTo *makeExceptionTo(PinSet *pins,
ClockSet *clks,
InstanceSet *insts,
const TransRiseFallBoth *tr,
const TransRiseFallBoth *end_tr);
const RiseFallBoth *rf,
const RiseFallBoth *end_rf);
FilterPath *makeFilterPath(ExceptionFrom *from,
ExceptionThruSeq *thrus,
ExceptionTo *to);
@ -848,28 +848,28 @@ public:
bool &exists);
// Inter-clock uncertainty.
void clockUncertainty(const Clock *src_clk,
const TransRiseFall *src_tr,
const RiseFall *src_rf,
const Clock *tgt_clk,
const TransRiseFall *tgt_tr,
const RiseFall *tgt_rf,
const SetupHold *setup_hold,
float &uncertainty, bool &exists);
void clockGatingMarginEnablePin(const Pin *enable_pin,
const TransRiseFall *enable_tr,
const RiseFall *enable_rf,
const SetupHold *setup_hold,
bool &exists, float &margin);
void clockGatingMarginInstance(Instance *inst,
const TransRiseFall *enable_tr,
const RiseFall *enable_rf,
const SetupHold *setup_hold,
bool &exists, float &margin);
void clockGatingMarginClkPin(const Pin *clk_pin,
const TransRiseFall *enable_tr,
const RiseFall *enable_rf,
const SetupHold *setup_hold,
bool &exists, float &margin);
void clockGatingMarginClk(const Clock *clk,
const TransRiseFall *enable_tr,
const RiseFall *enable_rf,
const SetupHold *setup_hold,
bool &exists, float &margin);
void clockGatingMargin(const TransRiseFall *enable_tr,
void clockGatingMargin(const RiseFall *enable_rf,
const SetupHold *setup_hold,
bool &exists, float &margin);
// Gated clock active (non-controlling) logic value.
@ -901,7 +901,7 @@ public:
PortExtCap *portExtCap(Port *port) const;
bool hasPortExtCap(Port *port) const;
void portExtCap(Port *port,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &pin_cap,
@ -911,13 +911,13 @@ public:
int &fanout,
bool &has_fanout) const;
float portExtCap(Port *port,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max) const;
// Connected total capacitance.
// pin_cap = pin capacitance + port external pin
// wire_cap = port external wire capacitance + net wire capacitance
void connectedCap(const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *min_max,
@ -937,40 +937,40 @@ public:
// that start at pin/net/instance also). Transition tr applies to
// pin, not clk.
bool exceptionFromStates(const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const Clock *clk,
const TransRiseFall *clk_tr,
const RiseFall *clk_rf,
const MinMax *min_max,
ExceptionStateSet *&states) const;
bool exceptionFromStates(const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const Clock *clk,
const TransRiseFall *clk_tr,
const RiseFall *clk_rf,
const MinMax *min_max,
bool include_filter,
ExceptionStateSet *&states) const;
void exceptionFromClkStates(const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const Clock *clk,
const TransRiseFall *clk_tr,
const RiseFall *clk_rf,
const MinMax *min_max,
ExceptionStateSet *&states) const;
void filterRegQStates(const Pin *to_pin,
const TransRiseFall *to_tr,
const RiseFall *to_rf,
const MinMax *min_max,
ExceptionStateSet *&states) const;
// Return hierarchical -thru exceptions that start between
// from_pin and to_pin.
void exceptionThruStates(const Pin *from_pin,
const Pin *to_pin,
const TransRiseFall *to_tr,
const RiseFall *to_rf,
const MinMax *min_max,
ExceptionStateSet *&states) const;
// Find the highest priority exception with first exception pt at
// pin/clk end.
void exceptionTo(ExceptionPathType type,
const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ClockEdge *clk_edge,
const MinMax *min_max,
bool match_min_max_exactly,
@ -979,14 +979,14 @@ public:
int &hi_priority) const;
virtual bool exceptionMatchesTo(ExceptionPath *exception,
const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ClockEdge *clk_edge,
const MinMax *min_max,
bool match_min_max_exactly,
bool require_to_pin) const;
bool isCompleteTo(ExceptionState *state,
const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ClockEdge *clk_edge,
const MinMax *min_max,
bool match_min_max_exactly,
@ -1122,19 +1122,19 @@ protected:
ExceptionPathSet &expansions);
bool exceptionFromStates(const ExceptionPathSet *exceptions,
const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max,
bool include_filter,
ExceptionStateSet *&states) const;
void exceptionThruStates(const ExceptionPathSet *exceptions,
const TransRiseFall *to_tr,
const RiseFall *to_rf,
const MinMax *min_max,
// Return value.
ExceptionStateSet *&states) const;
void exceptionTo(const ExceptionPathSet *to_exceptions,
ExceptionPathType type,
const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ClockEdge *clk_edge,
const MinMax *min_max,
bool match_min_max_exactly,
@ -1144,7 +1144,7 @@ protected:
void exceptionTo(ExceptionPath *exception,
ExceptionPathType type,
const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const ClockEdge *clk_edge,
const MinMax *min_max,
bool match_min_max_exactly,
@ -1219,7 +1219,7 @@ protected:
void deannotateHierClkLatency(const Pin *hpin);
void initInstancePvtMaps();
void pinCaps(const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *min_max,
@ -1228,7 +1228,7 @@ protected:
float &fanout,
bool &has_ext_cap) const;
void netCaps(const Pin *drvr_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *min_max,
@ -1239,12 +1239,12 @@ protected:
bool &has_set_load) const;
// connectedCap pin_cap.
float connectedPinCap(const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *min_max);
float portCapacitance(Instance *inst, LibertyPort *port,
const TransRiseFall *tr,
const RiseFall *rf,
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *min_max) const;
@ -1261,8 +1261,8 @@ protected:
ClockSense sense);
bool clkStopSense(const Pin *to_pin,
const Clock *clk,
const TransRiseFall *from_tr,
const TransRiseFall *to_tr) const;
const RiseFall *from_rf,
const RiseFall *to_rf) const;
void disconnectPinBefore(Pin *pin,
ExceptionPathSet *exceptions);
void clockGroupsDeleteClkRefs(Clock *clk);

182
sdc/WriteSdc.cc
View File

@ -52,9 +52,9 @@ typedef Set<ClockSense*> ClockSenseSet;
typedef Vector<ClockSense*> ClockSenseSeq;
static const char *
transRiseFallFlag(const TransRiseFall *tr);
transRiseFallFlag(const RiseFall *rf);
static const char *
transRiseFallFlag(const TransRiseFallBoth *tr);
transRiseFallFlag(const RiseFallBoth *rf);
static const char *
minMaxFlag(const MinMaxAll *min_max);
static const char *
@ -678,9 +678,9 @@ writeInterClockUncertainty(InterClockUncertainty *uncertainty) const
const Clock *src_clk = uncertainty->src();
const Clock *tgt_clk = uncertainty->target();
const RiseFallMinMax *src_rise =
uncertainty->uncertainties(TransRiseFall::rise());
uncertainty->uncertainties(RiseFall::rise());
const RiseFallMinMax *src_fall =
uncertainty->uncertainties(TransRiseFall::fall());
uncertainty->uncertainties(RiseFall::fall());
float value;
if (src_rise->equal(src_fall)
&& src_rise->isOneValue(value)) {
@ -693,19 +693,19 @@ writeInterClockUncertainty(InterClockUncertainty *uncertainty) const
fprintf(stream_, "\n");
}
else {
for (auto src_tr : TransRiseFall::range()) {
for (auto tgt_tr : TransRiseFall::range()) {
for (auto src_rf : RiseFall::range()) {
for (auto tgt_rf : RiseFall::range()) {
for (auto setup_hold : SetupHold::range()) {
float value;
bool exists;
sdc_->clockUncertainty(src_clk, src_tr, tgt_clk, tgt_tr,
sdc_->clockUncertainty(src_clk, src_rf, tgt_clk, tgt_rf,
setup_hold, value, exists);
if (exists) {
fprintf(stream_, "set_clock_uncertainty -%s_from ",
src_tr == TransRiseFall::rise() ? "rise" : "fall");
src_rf == RiseFall::rise() ? "rise" : "fall");
writeGetClock(uncertainty->src());
fprintf(stream_, " -%s_to ",
tgt_tr == TransRiseFall::rise() ? "rise" : "fall");
tgt_rf == RiseFall::rise() ? "rise" : "fall");
writeGetClock(uncertainty->target());
fprintf(stream_, " %s ",
setupHoldFlag(setup_hold));
@ -762,13 +762,13 @@ WriteSdc::writePortDelay(PortDelay *port_delay,
RiseFallMinMax *delays = port_delay->delays();
float rise_min, rise_max, fall_min, fall_max;
bool rise_min_exists, rise_max_exists, fall_min_exists, fall_max_exists;
delays->value(TransRiseFall::rise(), MinMax::min(),
delays->value(RiseFall::rise(), MinMax::min(),
rise_min, rise_min_exists);
delays->value(TransRiseFall::rise(), MinMax::max(),
delays->value(RiseFall::rise(), MinMax::max(),
rise_max, rise_max_exists);
delays->value(TransRiseFall::fall(), MinMax::min(),
delays->value(RiseFall::fall(), MinMax::min(),
fall_min, fall_min_exists);
delays->value(TransRiseFall::fall(), MinMax::max(),
delays->value(RiseFall::fall(), MinMax::max(),
fall_max, fall_max_exists);
// Try to compress the four port delays.
if (rise_min_exists
@ -779,7 +779,7 @@ WriteSdc::writePortDelay(PortDelay *port_delay,
&& fall_min == rise_min
&& fall_max == rise_min)
writePortDelay(port_delay, is_input_delay, rise_min,
TransRiseFallBoth::riseFall(), MinMaxAll::all(), sdc_cmd);
RiseFallBoth::riseFall(), MinMaxAll::all(), sdc_cmd);
else if (rise_min_exists
&& rise_max_exists
&& rise_max == rise_min
@ -787,9 +787,9 @@ WriteSdc::writePortDelay(PortDelay *port_delay,
&& fall_max_exists
&& fall_min == fall_max) {
writePortDelay(port_delay, is_input_delay, rise_min,
TransRiseFallBoth::rise(), MinMaxAll::all(), sdc_cmd);
RiseFallBoth::rise(), MinMaxAll::all(), sdc_cmd);
writePortDelay(port_delay, is_input_delay, fall_min,
TransRiseFallBoth::fall(), MinMaxAll::all(), sdc_cmd);
RiseFallBoth::fall(), MinMaxAll::all(), sdc_cmd);
}
else if (rise_min_exists
&& fall_min_exists
@ -798,23 +798,23 @@ WriteSdc::writePortDelay(PortDelay *port_delay,
&& fall_max_exists
&& rise_max == fall_max) {
writePortDelay(port_delay, is_input_delay, rise_min,
TransRiseFallBoth::riseFall(), MinMaxAll::min(), sdc_cmd);
RiseFallBoth::riseFall(), MinMaxAll::min(), sdc_cmd);
writePortDelay(port_delay, is_input_delay, rise_max,
TransRiseFallBoth::riseFall(), MinMaxAll::max(), sdc_cmd);
RiseFallBoth::riseFall(), MinMaxAll::max(), sdc_cmd);
}
else {
if (rise_min_exists)
writePortDelay(port_delay, is_input_delay, rise_min,
TransRiseFallBoth::rise(), MinMaxAll::min(), sdc_cmd);
RiseFallBoth::rise(), MinMaxAll::min(), sdc_cmd);
if (rise_max_exists)
writePortDelay(port_delay, is_input_delay, rise_max,
TransRiseFallBoth::rise(), MinMaxAll::max(), sdc_cmd);
RiseFallBoth::rise(), MinMaxAll::max(), sdc_cmd);
if (fall_min_exists)
writePortDelay(port_delay, is_input_delay, fall_min,
TransRiseFallBoth::fall(), MinMaxAll::min(), sdc_cmd);
RiseFallBoth::fall(), MinMaxAll::min(), sdc_cmd);
if (fall_max_exists)
writePortDelay(port_delay, is_input_delay, fall_max,
TransRiseFallBoth::fall(), MinMaxAll::max(), sdc_cmd);
RiseFallBoth::fall(), MinMaxAll::max(), sdc_cmd);
}
}
@ -822,7 +822,7 @@ void
WriteSdc::writePortDelay(PortDelay *port_delay,
bool is_input_delay,
float delay,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const MinMaxAll *min_max,
const char *sdc_cmd) const
{
@ -831,11 +831,11 @@ WriteSdc::writePortDelay(PortDelay *port_delay,
ClockEdge *clk_edge = port_delay->clkEdge();
if (clk_edge) {
writeClockKey(clk_edge->clock());
if (clk_edge->transition() == TransRiseFall::fall())
if (clk_edge->transition() == RiseFall::fall())
fprintf(stream_, " -clock_fall");
}
fprintf(stream_, "%s%s -add_delay ",
transRiseFallFlag(tr),
transRiseFallFlag(rf),
minMaxFlag(min_max));
Pin *ref_pin = port_delay->refPin();
if (ref_pin) {
@ -1352,9 +1352,9 @@ WriteSdc::writeExceptionFrom(ExceptionFrom *from) const
void
WriteSdc::writeExceptionTo(ExceptionTo *to) const
{
const TransRiseFallBoth *end_tr = to->endTransition();
if (end_tr != TransRiseFallBoth::riseFall())
fprintf(stream_, "%s ", transRiseFallFlag(end_tr));
const RiseFallBoth *end_rf = to->endTransition();
if (end_rf != RiseFallBoth::riseFall())
fprintf(stream_, "%s ", transRiseFallFlag(end_rf));
if (to->hasObjects())
writeExceptionFromTo(to, "to", false);
}
@ -1364,11 +1364,11 @@ WriteSdc::writeExceptionFromTo(ExceptionFromTo *from_to,
const char *from_to_key,
bool map_hpin_to_drvr) const
{
const TransRiseFallBoth *tr = from_to->transition();
const RiseFallBoth *rf = from_to->transition();
const char *tr_prefix = "-";
if (tr == TransRiseFallBoth::rise())
if (rf == RiseFallBoth::rise())
tr_prefix = "-rise_";
else if (tr == TransRiseFallBoth::fall())
else if (rf == RiseFallBoth::fall())
tr_prefix = "-fall_";
fprintf(stream_, "\\\n %s%s ", tr_prefix, from_to_key);
bool multi_objs =
@ -1411,11 +1411,11 @@ WriteSdc::writeExceptionFromTo(ExceptionFromTo *from_to,
void
WriteSdc::writeExceptionThru(ExceptionThru *thru) const
{
const TransRiseFallBoth *tr = thru->transition();
const RiseFallBoth *rf = thru->transition();
const char *tr_prefix = "-";
if (tr == TransRiseFallBoth::rise())
if (rf == RiseFallBoth::rise())
tr_prefix = "-rise_";
else if (tr == TransRiseFallBoth::fall())
else if (rf == RiseFallBoth::fall())
tr_prefix = "-fall_";
fprintf(stream_, "\\\n %sthrough ", tr_prefix);
PinSeq pins;
@ -1524,17 +1524,17 @@ WriteSdc::writeDataCheck(DataCheck *check) const
bool one_value;
check->marginIsOneValue(setup_hold, margin, one_value);
if (one_value)
writeDataCheck(check, TransRiseFallBoth::riseFall(),
TransRiseFallBoth::riseFall(), setup_hold, margin);
writeDataCheck(check, RiseFallBoth::riseFall(),
RiseFallBoth::riseFall(), setup_hold, margin);
else {
for (auto from_tr : TransRiseFall::range()) {
for (auto to_tr : TransRiseFall::range()) {
for (auto from_rf : RiseFall::range()) {
for (auto to_rf : RiseFall::range()) {
float margin;
bool margin_exists;
check->margin(from_tr, to_tr, setup_hold, margin, margin_exists);
check->margin(from_rf, to_rf, setup_hold, margin, margin_exists);
if (margin_exists) {
writeDataCheck(check, from_tr->asRiseFallBoth(),
to_tr->asRiseFallBoth(), setup_hold, margin);
writeDataCheck(check, from_rf->asRiseFallBoth(),
to_rf->asRiseFallBoth(), setup_hold, margin);
}
}
}
@ -1544,22 +1544,22 @@ WriteSdc::writeDataCheck(DataCheck *check) const
void
WriteSdc::writeDataCheck(DataCheck *check,
TransRiseFallBoth *from_tr,
TransRiseFallBoth *to_tr,
RiseFallBoth *from_rf,
RiseFallBoth *to_rf,
SetupHold *setup_hold,
float margin) const
{
const char *from_key = "-from";
if (from_tr == TransRiseFallBoth::rise())
if (from_rf == RiseFallBoth::rise())
from_key = "-rise_from";
else if (from_tr == TransRiseFallBoth::fall())
else if (from_rf == RiseFallBoth::fall())
from_key = "-fall_from";
fprintf(stream_, "set_data_check %s ", from_key);
writeGetPin(check->from(), true);
const char *to_key = "-to";
if (to_tr == TransRiseFallBoth::rise())
if (to_rf == RiseFallBoth::rise())
to_key = "-rise_to";
else if (to_tr == TransRiseFallBoth::fall())
else if (to_rf == RiseFallBoth::fall())
to_key = "-fall_to";
fprintf(stream_, " %s ", to_key);
writeGetPin(check->to(), false);
@ -1640,7 +1640,7 @@ WriteSdc::writeDriveResistances() const
Port *port = port_iter->next();
InputDrive *drive = sdc_->findInputDrive(port);
if (drive) {
for (auto tr : TransRiseFall::range()) {
for (auto tr : RiseFall::range()) {
if (drive->driveResistanceMinMaxEqual(tr)) {
float res;
bool exists;
@ -1682,13 +1682,13 @@ WriteSdc::writeDrivingCells() const
Port *port = port_iter->next();
InputDrive *drive = sdc_->findInputDrive(port);
if (drive) {
InputDriveCell *drive_rise_min = drive->driveCell(TransRiseFall::rise(),
InputDriveCell *drive_rise_min = drive->driveCell(RiseFall::rise(),
MinMax::min());
InputDriveCell *drive_rise_max = drive->driveCell(TransRiseFall::rise(),
InputDriveCell *drive_rise_max = drive->driveCell(RiseFall::rise(),
MinMax::max());
InputDriveCell *drive_fall_min = drive->driveCell(TransRiseFall::fall(),
InputDriveCell *drive_fall_min = drive->driveCell(RiseFall::fall(),
MinMax::min());
InputDriveCell *drive_fall_max = drive->driveCell(TransRiseFall::fall(),
InputDriveCell *drive_fall_max = drive->driveCell(RiseFall::fall(),
MinMax::max());
if (drive_rise_min
&& drive_rise_max
@ -1703,25 +1703,25 @@ WriteSdc::writeDrivingCells() const
if (drive_rise_min
&& drive_rise_max
&& drive_rise_min->equal(drive_rise_max))
writeDrivingCell(port, drive_rise_min, TransRiseFall::rise(), nullptr);
writeDrivingCell(port, drive_rise_min, RiseFall::rise(), nullptr);
else {
if (drive_rise_min)
writeDrivingCell(port, drive_rise_min, TransRiseFall::rise(),
writeDrivingCell(port, drive_rise_min, RiseFall::rise(),
MinMax::min());
if (drive_rise_max)
writeDrivingCell(port, drive_rise_max, TransRiseFall::rise(),
writeDrivingCell(port, drive_rise_max, RiseFall::rise(),
MinMax::max());
}
if (drive_fall_min
&& drive_fall_max
&& drive_fall_min->equal(drive_fall_max))
writeDrivingCell(port, drive_fall_min, TransRiseFall::fall(), nullptr);
writeDrivingCell(port, drive_fall_min, RiseFall::fall(), nullptr);
else {
if (drive_fall_min)
writeDrivingCell(port, drive_fall_min, TransRiseFall::fall(),
writeDrivingCell(port, drive_fall_min, RiseFall::fall(),
MinMax::min());
if (drive_fall_max)
writeDrivingCell(port, drive_fall_max, TransRiseFall::fall(),
writeDrivingCell(port, drive_fall_max, RiseFall::fall(),
MinMax::max());
}
}
@ -1733,7 +1733,7 @@ WriteSdc::writeDrivingCells() const
void
WriteSdc::writeDrivingCell(Port *port,
InputDriveCell *drive_cell,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max) const
{
LibertyCell *cell = drive_cell->cell();
@ -1742,8 +1742,8 @@ WriteSdc::writeDrivingCell(Port *port,
float *from_slews = drive_cell->fromSlews();
LibertyLibrary *lib = drive_cell->library();
fprintf(stream_, "set_driving_cell");
if (tr)
fprintf(stream_, " %s", transRiseFallFlag(tr));
if (rf)
fprintf(stream_, " %s", transRiseFallFlag(rf));
if (min_max)
fprintf(stream_, " %s", minMaxFlag(min_max));
// Only write -library if it was specified in the sdc.
@ -1756,9 +1756,9 @@ WriteSdc::writeDrivingCell(Port *port,
fprintf(stream_,
" -pin {%s} -input_transition_rise ",
to_port->name());
writeTime(from_slews[TransRiseFall::riseIndex()]);
writeTime(from_slews[RiseFall::riseIndex()]);
fprintf(stream_, " -input_transition_fall ");
writeTime(from_slews[TransRiseFall::fallIndex()]);
writeTime(from_slews[RiseFall::fallIndex()]);
fprintf(stream_, " ");
writeGetPort(port);
fprintf(stream_, "\n");
@ -2059,7 +2059,7 @@ WriteSdc::writeDerating(DeratingFactors *factors,
}
}
else {
for (auto tr : TransRiseFall::range()) {
for (auto tr : RiseFall::range()) {
float factor;
bool exists;
factors->factor(clk_data, tr, early_late, factor, exists);
@ -2141,8 +2141,8 @@ WriteSdc::writeMinPulseWidths(RiseFallValues *min_widths,
{
bool hi_exists, low_exists;
float hi, low;
min_widths->value(TransRiseFall::rise(), hi, hi_exists);
min_widths->value(TransRiseFall::fall(), low, low_exists);
min_widths->value(RiseFall::rise(), hi, hi_exists);
min_widths->value(RiseFall::fall(), low, low_exists);
if (hi_exists && low_exists
&& hi == low)
writeMinPulseWidth("", hi, write_obj);
@ -2270,13 +2270,13 @@ WriteSdc::writeClkSlewLimits() const
Clock *clk = clk_iter.next();
float rise_clk_limit, fall_clk_limit, rise_data_limit, fall_data_limit;
bool rise_clk_exists, fall_clk_exists, rise_data_exists, fall_data_exists;
clk->slewLimit(TransRiseFall::rise(), PathClkOrData::clk, min_max,
clk->slewLimit(RiseFall::rise(), PathClkOrData::clk, min_max,
rise_clk_limit, rise_clk_exists);
clk->slewLimit(TransRiseFall::fall(), PathClkOrData::clk, min_max,
clk->slewLimit(RiseFall::fall(), PathClkOrData::clk, min_max,
fall_clk_limit, fall_clk_exists);
clk->slewLimit(TransRiseFall::rise(), PathClkOrData::data, min_max,
clk->slewLimit(RiseFall::rise(), PathClkOrData::data, min_max,
rise_data_limit, rise_data_exists);
clk->slewLimit(TransRiseFall::fall(), PathClkOrData::data, min_max,
clk->slewLimit(RiseFall::fall(), PathClkOrData::data, min_max,
fall_data_limit, fall_data_exists);
if (rise_clk_exists && fall_clk_exists
&& rise_data_exists && fall_data_exists
@ -2709,13 +2709,13 @@ WriteSdc::writeRiseFallMinMaxCmd(const char *sdc_cmd,
{
float fall_min, fall_max, rise_min, rise_max;
bool fall_min_exists, fall_max_exists, rise_min_exists, rise_max_exists;
values->value(TransRiseFall::fall(), MinMax::min(),
values->value(RiseFall::fall(), MinMax::min(),
fall_min, fall_min_exists);
values->value(TransRiseFall::fall(), MinMax::max(),
values->value(RiseFall::fall(), MinMax::max(),
fall_max, fall_max_exists);
values->value(TransRiseFall::rise(), MinMax::min(),
values->value(RiseFall::rise(), MinMax::min(),
rise_min, rise_min_exists);
values->value(TransRiseFall::rise(), MinMax::max(),
values->value(RiseFall::rise(), MinMax::max(),
rise_max, rise_max_exists);
if (fall_min_exists && fall_max_exists
&& rise_min_exists && rise_max_exists) {
@ -2724,46 +2724,46 @@ WriteSdc::writeRiseFallMinMaxCmd(const char *sdc_cmd,
&& fall_max == rise_min) {
// rise/fall/min/max match.
writeRiseFallMinMaxCmd(sdc_cmd, rise_min, scale,
TransRiseFallBoth::riseFall(), MinMaxAll::all(),
RiseFallBoth::riseFall(), MinMaxAll::all(),
write_object);
}
else if (rise_min == fall_min
&& rise_max == fall_max) {
// rise/fall match.
writeRiseFallMinMaxCmd(sdc_cmd, rise_min, scale,
TransRiseFallBoth::riseFall(), MinMaxAll::min(),
RiseFallBoth::riseFall(), MinMaxAll::min(),
write_object);
writeRiseFallMinMaxCmd(sdc_cmd, rise_max, scale,
TransRiseFallBoth::riseFall(), MinMaxAll::max(),
RiseFallBoth::riseFall(), MinMaxAll::max(),
write_object);
}
else if (rise_min == rise_max
&& fall_min == fall_max) {
// min/max match.
writeRiseFallMinMaxCmd(sdc_cmd, rise_min, scale,
TransRiseFallBoth::rise(), MinMaxAll::all(),
RiseFallBoth::rise(), MinMaxAll::all(),
write_object);
writeRiseFallMinMaxCmd(sdc_cmd, fall_min, scale,
TransRiseFallBoth::fall(), MinMaxAll::all(),
RiseFallBoth::fall(), MinMaxAll::all(),
write_object);
}
}
else {
if (rise_min_exists)
writeRiseFallMinMaxCmd(sdc_cmd, rise_min, scale,
TransRiseFallBoth::rise(), MinMaxAll::min(),
RiseFallBoth::rise(), MinMaxAll::min(),
write_object);
if (rise_max_exists)
writeRiseFallMinMaxCmd(sdc_cmd, rise_max, scale,
TransRiseFallBoth::rise(), MinMaxAll::max(),
RiseFallBoth::rise(), MinMaxAll::max(),
write_object);
if (fall_min_exists)
writeRiseFallMinMaxCmd(sdc_cmd, fall_min, scale,
TransRiseFallBoth::fall(), MinMaxAll::min(),
RiseFallBoth::fall(), MinMaxAll::min(),
write_object);
if (fall_max_exists)
writeRiseFallMinMaxCmd(sdc_cmd, fall_max, scale,
TransRiseFallBoth::fall(), MinMaxAll::max(),
RiseFallBoth::fall(), MinMaxAll::max(),
write_object);
}
}
@ -2772,13 +2772,13 @@ void
WriteSdc::writeRiseFallMinMaxCmd(const char *sdc_cmd,
float value,
float scale,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const MinMaxAll *min_max,
WriteSdcObject &write_object) const
{
fprintf(stream_, "%s%s%s ",
sdc_cmd,
transRiseFallFlag(tr),
transRiseFallFlag(rf),
minMaxFlag(min_max));
writeFloat(value / scale);
fprintf(stream_, " ");
@ -2951,19 +2951,19 @@ WriteSdc::writeIntSeq(IntSeq *ints) const
////////////////////////////////////////////////////////////////
static const char *
transRiseFallFlag(const TransRiseFall *tr)
transRiseFallFlag(const RiseFall *rf)
{
return (tr == TransRiseFall::rise()) ? "-rise" : "-fall";
return (rf == RiseFall::rise()) ? "-rise" : "-fall";
}
static const char *
transRiseFallFlag(const TransRiseFallBoth *tr)
transRiseFallFlag(const RiseFallBoth *rf)
{
if (tr == TransRiseFallBoth::rise())
if (rf == RiseFallBoth::rise())
return " -rise";
else if (tr == TransRiseFallBoth::fall())
else if (rf == RiseFallBoth::fall())
return " -fall";
else if (tr == TransRiseFallBoth::riseFall())
else if (rf == RiseFallBoth::riseFall())
return "";
else {
internalError("unknown transition");

10
sdc/WriteSdcPvt.hh
View File

@ -88,7 +88,7 @@ public:
void writePortDelay(PortDelay *port_delay,
bool is_input_delay,
float delay,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const MinMaxAll *min_max,
const char *sdc_cmd) const;
void writeClockSenses() const;
@ -111,8 +111,8 @@ public:
void writeDataChecks() const;
void writeDataCheck(DataCheck *check) const;
void writeDataCheck(DataCheck *check,
TransRiseFallBoth *from_tr,
TransRiseFallBoth *to_tr,
RiseFallBoth *from_rf,
RiseFallBoth *to_rf,
SetupHold *setup_hold,
float margin) const;
void writeEnvironment() const;
@ -126,7 +126,7 @@ public:
void writeInputTransitions() const;
void writeDrivingCell(Port *port,
InputDriveCell *drive_cell,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max) const;
void writeConstants() const;
virtual void writeConstant(Pin *pin) const;
@ -220,7 +220,7 @@ public:
void writeRiseFallMinMaxCmd(const char *sdc_cmd,
float value,
float scale,
const TransRiseFallBoth *tr,
const RiseFallBoth *rf,
const MinMaxAll *min_max,
WriteSdcObject &write_object) const;
void writeMinMaxFloatValuesCmd(const char *sdc_cmd,

4
sdf/ReportAnnotation.cc
View File

@ -403,7 +403,7 @@ ReportAnnotated::findWidthPeriodCount(Pin *pin)
int width_index = TimingRole::width()->index();
if (report_role_[width_index]) {
for (auto hi_low : TransRiseFall::range()) {
for (auto hi_low : RiseFall::range()) {
port->minPulseWidth(hi_low, value, exists);
if (exists) {
edge_count_[width_index]++;
@ -557,7 +557,7 @@ ReportAnnotated::reportWidthPeriodArcs(Pin *pin,
if (report_role_[width_index]
&& (max_lines_ == 0 || i < max_lines_)) {
bool report = false;
for (auto hi_low : TransRiseFall::range()) {
for (auto hi_low : RiseFall::range()) {
port->minPulseWidth(hi_low, value, exists);
if (exists) {
edge_count_[width_index]++;

6
sdf/SdfReader.cc
View File

@ -581,19 +581,19 @@ SdfReader::timingCheckWidth(SdfPortSpec *edge,
else {
Pin *pin = network_->findPin(instance_, port_name);
if (pin) {
const TransRiseFall *tr = edge->transition()->asRiseFall();
const RiseFall *rf = edge->transition()->asRiseFall();
float **values = triple->values();
float *value_ptr = values[triple_min_index_];
if (value_ptr) {
float value = *value_ptr;
graph_->setWidthCheckAnnotation(pin, tr, arc_delay_min_index_,
graph_->setWidthCheckAnnotation(pin, rf, arc_delay_min_index_,
value);
}
if (triple_max_index_ != null_index_) {
value_ptr = values[triple_max_index_];
if (value_ptr) {
float value = *value_ptr;
graph_->setWidthCheckAnnotation(pin, tr, arc_delay_max_index_,
graph_->setWidthCheckAnnotation(pin, rf, arc_delay_max_index_,
value);
}
}

98
sdf/SdfWriter.cc
View File

@ -81,12 +81,12 @@ protected:
bool use_clk_edge);
void writeEdgeCheck(Edge *edge,
const char *sdf_check,
int clk_tr_index,
TimingArc *arcs[TransRiseFall::index_count][TransRiseFall::index_count]);
int clk_rf_index,
TimingArc *arcs[RiseFall::index_count][RiseFall::index_count]);
void writeTimingCheckHeader();
void writeTimingCheckTrailer();
void writeWidthCheck(const Pin *pin,
const TransRiseFall *hi_low,
const RiseFall *hi_low,
float min_width,
float max_width);
void writePeriodCheck(const Pin *pin,
@ -94,7 +94,7 @@ protected:
const char *sdfEdge(const Transition *tr);
void writeArcDelays(Edge *edge);
void writeSdfTuple(RiseFallMinMax &delays,
TransRiseFall *tr);
RiseFall *rf);
void writeSdfTuple(float min_delay,
float max_delay);
void writeSdfDelay(double delay);
@ -416,45 +416,45 @@ SdfWriter::writeArcDelays(Edge *edge)
TimingArcSetArcIterator arc_iter(arc_set);
while (arc_iter.hasNext()) {
TimingArc *arc = arc_iter.next();
TransRiseFall *tr = arc->toTrans()->asRiseFall();
RiseFall *rf = arc->toTrans()->asRiseFall();
ArcDelay min_delay = graph_->arcDelay(edge, arc, arc_delay_min_index_);
delays.setValue(tr, MinMax::min(), delayAsFloat(min_delay));
delays.setValue(rf, MinMax::min(), delayAsFloat(min_delay));
ArcDelay max_delay = graph_->arcDelay(edge, arc, arc_delay_max_index_);
delays.setValue(tr, MinMax::max(), delayAsFloat(max_delay));
delays.setValue(rf, MinMax::max(), delayAsFloat(max_delay));
}
if (delays.hasValue(TransRiseFall::rise(), MinMax::min())
&& delays.hasValue(TransRiseFall::fall(), MinMax::min())) {
if (delays.hasValue(RiseFall::rise(), MinMax::min())
&& delays.hasValue(RiseFall::fall(), MinMax::min())) {
// Rise and fall.
writeSdfTuple(delays, TransRiseFall::rise());
writeSdfTuple(delays, RiseFall::rise());
// Merge rise/fall values if they are the same.
if (!(fuzzyEqual(delays.value(TransRiseFall::rise(), MinMax::min()),
delays.value(TransRiseFall::fall(), MinMax::min()))
&& fuzzyEqual(delays.value(TransRiseFall::rise(), MinMax::max()),
delays.value(TransRiseFall::fall(),MinMax::max())))) {
if (!(fuzzyEqual(delays.value(RiseFall::rise(), MinMax::min()),
delays.value(RiseFall::fall(), MinMax::min()))
&& fuzzyEqual(delays.value(RiseFall::rise(), MinMax::max()),
delays.value(RiseFall::fall(),MinMax::max())))) {
gzprintf(stream_, " ");
writeSdfTuple(delays, TransRiseFall::fall());
writeSdfTuple(delays, RiseFall::fall());
}
}
else if (delays.hasValue(TransRiseFall::rise(), MinMax::min()))
else if (delays.hasValue(RiseFall::rise(), MinMax::min()))
// Rise only.
writeSdfTuple(delays, TransRiseFall::rise());
else if (delays.hasValue(TransRiseFall::fall(), MinMax::min())) {
writeSdfTuple(delays, RiseFall::rise());
else if (delays.hasValue(RiseFall::fall(), MinMax::min())) {
// Fall only.
gzprintf(stream_, "() ");
writeSdfTuple(delays, TransRiseFall::fall());
writeSdfTuple(delays, RiseFall::fall());
}
}
void
SdfWriter::writeSdfTuple(RiseFallMinMax &delays,
TransRiseFall *tr)
RiseFall *rf)
{
gzprintf(stream_, "(");
writeSdfDelay(delays.value(tr, MinMax::min()));
writeSdfDelay(delays.value(rf, MinMax::min()));
gzprintf(stream_, "::");
writeSdfDelay(delays.value(tr, MinMax::max()));
writeSdfDelay(delays.value(rf, MinMax::max()));
gzprintf(stream_, ")");
}
@ -503,7 +503,7 @@ SdfWriter::writeTimingChecks(const Instance *inst,
writeCheck(edge, sdf_check);
}
}
for (auto hi_low : TransRiseFall::range()) {
for (auto hi_low : RiseFall::range()) {
float min_width, max_width;
bool exists;
graph_delay_calc_->minPulseWidth(pin, hi_low, arc_delay_min_index_,
@ -564,22 +564,22 @@ SdfWriter::writeCheck(Edge *edge,
{
TimingArcSet *arc_set = edge->timingArcSet();
// Examine the arcs to see if the check requires clk or data edge specifiers.
TimingArc *arcs[TransRiseFall::index_count][TransRiseFall::index_count] =
TimingArc *arcs[RiseFall::index_count][RiseFall::index_count] =
{{nullptr, nullptr}, {nullptr, nullptr}};
TimingArcSetArcIterator arc_iter(arc_set);
while (arc_iter.hasNext()) {
TimingArc *arc = arc_iter.next();
TransRiseFall *clk_tr = arc->fromTrans()->asRiseFall();
TransRiseFall *data_tr = arc->toTrans()->asRiseFall();;
arcs[clk_tr->index()][data_tr->index()] = arc;
RiseFall *clk_rf = arc->fromTrans()->asRiseFall();
RiseFall *data_rf = arc->toTrans()->asRiseFall();;
arcs[clk_rf->index()][data_rf->index()] = arc;
}
if (arcs[TransRiseFall::fallIndex()][TransRiseFall::riseIndex()] == nullptr
&& arcs[TransRiseFall::fallIndex()][TransRiseFall::fallIndex()] == nullptr)
writeEdgeCheck(edge, sdf_check, TransRiseFall::riseIndex(), arcs);
else if (arcs[TransRiseFall::riseIndex()][TransRiseFall::riseIndex()] == nullptr
&& arcs[TransRiseFall::riseIndex()][TransRiseFall::fallIndex()] == nullptr)
writeEdgeCheck(edge, sdf_check, TransRiseFall::fallIndex(), arcs);
if (arcs[RiseFall::fallIndex()][RiseFall::riseIndex()] == nullptr
&& arcs[RiseFall::fallIndex()][RiseFall::fallIndex()] == nullptr)
writeEdgeCheck(edge, sdf_check, RiseFall::riseIndex(), arcs);
else if (arcs[RiseFall::riseIndex()][RiseFall::riseIndex()] == nullptr
&& arcs[RiseFall::riseIndex()][RiseFall::fallIndex()] == nullptr)
writeEdgeCheck(edge, sdf_check, RiseFall::fallIndex(), arcs);
else {
// No special case; write all the checks with data and clock edge specifiers.
TimingArcSetArcIterator arc_iter(arc_set);
@ -593,38 +593,38 @@ SdfWriter::writeCheck(Edge *edge,
void
SdfWriter::writeEdgeCheck(Edge *edge,
const char *sdf_check,
int clk_tr_index,
TimingArc *arcs[TransRiseFall::index_count][TransRiseFall::index_count])
int clk_rf_index,
TimingArc *arcs[RiseFall::index_count][RiseFall::index_count])
{
// SDF requires edge specifiers on the data port to define separate
// rise/fall check values.
// Check the rise/fall margins to see if they are the same to avoid adding
// data port edge specifiers if they aren't necessary.
if (arcs[clk_tr_index][TransRiseFall::riseIndex()]
&& arcs[clk_tr_index][TransRiseFall::fallIndex()]
&& arcs[clk_tr_index][TransRiseFall::riseIndex()]
&& arcs[clk_tr_index][TransRiseFall::fallIndex()]
if (arcs[clk_rf_index][RiseFall::riseIndex()]
&& arcs[clk_rf_index][RiseFall::fallIndex()]
&& arcs[clk_rf_index][RiseFall::riseIndex()]
&& arcs[clk_rf_index][RiseFall::fallIndex()]
&& fuzzyEqual(graph_->arcDelay(edge,
arcs[clk_tr_index][TransRiseFall::riseIndex()],
arcs[clk_rf_index][RiseFall::riseIndex()],
arc_delay_min_index_),
graph_->arcDelay(edge,
arcs[clk_tr_index][TransRiseFall::fallIndex()],
arcs[clk_rf_index][RiseFall::fallIndex()],
arc_delay_min_index_))
&& fuzzyEqual(graph_->arcDelay(edge,
arcs[clk_tr_index][TransRiseFall::riseIndex()],
arcs[clk_rf_index][RiseFall::riseIndex()],
arc_delay_max_index_),
graph_->arcDelay(edge,
arcs[clk_tr_index][TransRiseFall::fallIndex()],
arcs[clk_rf_index][RiseFall::fallIndex()],
arc_delay_max_index_)))
// Rise/fall margins are the same, so no data edge specifier is required.
writeCheck(edge, arcs[clk_tr_index][TransRiseFall::riseIndex()],
writeCheck(edge, arcs[clk_rf_index][RiseFall::riseIndex()],
sdf_check, false, true);
else {
if (arcs[clk_tr_index][TransRiseFall::riseIndex()])
writeCheck(edge, arcs[clk_tr_index][TransRiseFall::riseIndex()],
if (arcs[clk_rf_index][RiseFall::riseIndex()])
writeCheck(edge, arcs[clk_rf_index][RiseFall::riseIndex()],
sdf_check, true, true);
if (arcs[clk_tr_index][TransRiseFall::fallIndex()])
writeCheck(edge, arcs[clk_tr_index][TransRiseFall::fallIndex()],
if (arcs[clk_rf_index][RiseFall::fallIndex()])
writeCheck(edge, arcs[clk_rf_index][RiseFall::fallIndex()],
sdf_check, true, true);
}
}
@ -683,7 +683,7 @@ SdfWriter::writeCheck(Edge *edge,
void
SdfWriter::writeWidthCheck(const Pin *pin,
const TransRiseFall *hi_low,
const RiseFall *hi_low,
float min_width,
float max_width)
{

8
search/CheckMaxSkews.cc
View File

@ -199,15 +199,15 @@ CheckMaxSkews:: visitMaxSkewChecks(Vertex *vertex,
TimingArcSetArcIterator arc_iter(arc_set);
while (arc_iter.hasNext()) {
TimingArc *arc = arc_iter.next();
TransRiseFall *clk_tr = arc->fromTrans()->asRiseFall();
TransRiseFall *ref_tr = arc->toTrans()->asRiseFall();
VertexPathIterator clk_path_iter(vertex, clk_tr, clk_min_max, search);
RiseFall *clk_rf = arc->fromTrans()->asRiseFall();
RiseFall *ref_rf = arc->toTrans()->asRiseFall();
VertexPathIterator clk_path_iter(vertex, clk_rf, clk_min_max, search);
while (clk_path_iter.hasNext()) {
PathVertex *clk_path = clk_path_iter.next();
if (clk_path->isClock(search)) {
const PathAnalysisPt *clk_ap = clk_path->pathAnalysisPt(sta_);
PathAnalysisPt *ref_ap = clk_ap->tgtClkAnalysisPt();
VertexPathIterator ref_path_iter(ref_vertex, ref_tr, ref_ap, sta_);
VertexPathIterator ref_path_iter(ref_vertex, ref_rf, ref_ap, sta_);
while (ref_path_iter.hasNext()) {
PathVertex *ref_path = ref_path_iter.next();
if (ref_path->isClock(search)) {

20
search/CheckMinPulseWidths.cc
View File

@ -311,7 +311,7 @@ MinPulseWidthCheck::pin(const StaState *sta) const
return open_path_.pin(sta);
}
const TransRiseFall *
const RiseFall *
MinPulseWidthCheck::openTransition(const StaState *sta) const
{
return open_path_.transition(sta);
@ -324,8 +324,8 @@ MinPulseWidthCheck::closePath(const StaState *sta,
{
PathAnalysisPt *open_ap = open_path_.pathAnalysisPt(sta);
PathAnalysisPt *close_ap = open_ap->tgtClkAnalysisPt();
const TransRiseFall *open_tr = open_path_.transition(sta);
const TransRiseFall *close_tr = open_tr->opposite();
const RiseFall *open_rf = open_path_.transition(sta);
const RiseFall *close_rf = open_rf->opposite();
Tag *open_tag = open_path_.tag(sta);
ClkInfo *open_clk_info = open_tag->clkInfo();
ClkInfo close_clk_info(open_clk_info->clkEdge()->opposite(),
@ -339,7 +339,7 @@ MinPulseWidthCheck::closePath(const StaState *sta,
open_clk_info->crprClkPath(),
sta);
Tag close_tag(0,
close_tr->index(),
close_rf->index(),
close_ap->index(),
&close_clk_info,
open_tag->isClock(),
@ -351,7 +351,7 @@ MinPulseWidthCheck::closePath(const StaState *sta,
open_tag->asString(sta));
debugPrint1(sta->debug(), "mpw", 3, " close %s\n",
close_tag.asString(sta));
VertexPathIterator close_iter(open_path_.vertex(sta), close_tr,
VertexPathIterator close_iter(open_path_.vertex(sta), close_rf,
close_ap, sta);
while (close_iter.hasNext()) {
PathVertex *close_path = close_iter.next();
@ -445,16 +445,16 @@ minPulseWidth(const Path *path,
{
Pin *pin = path->pin(sta);
Clock *clk = path->clock(sta);
const TransRiseFall *tr = path->transition(sta);
const RiseFall *rf = path->transition(sta);
Sdc *sdc = sta->sdc();
// set_min_pulse_width command.
sdc->minPulseWidth(pin, clk, tr, min_width, exists);
sdc->minPulseWidth(pin, clk, rf, min_width, exists);
if (!exists) {
GraphDelayCalc *graph_dcalc = sta->graphDelayCalc();
const MinMax *min_max = path->minMax(sta);
const PathAnalysisPt *path_ap = path->pathAnalysisPt(sta);
const DcalcAnalysisPt *dcalc_ap = path_ap->dcalcAnalysisPt();
graph_dcalc->minPulseWidth(pin, tr, dcalc_ap->index(), min_max,
graph_dcalc->minPulseWidth(pin, rf, dcalc_ap->index(), min_max,
min_width, exists);
}
}
@ -503,8 +503,8 @@ MinPulseWidthSlackLess::operator()(const MinPulseWidthCheck *check1,
// Break ties for the sake of regression stability.
&& (sta_->network()->pinLess(pin1, pin2)
|| (pin1 == pin2
&& check1->openPath()->trIndex(sta_)
< check2->openPath()->trIndex(sta_))));
&& check1->openPath()->rfIndex(sta_)
< check2->openPath()->rfIndex(sta_))));
}
} // namespace

4
search/CheckMinPulseWidths.hh
View File

@ -25,7 +25,7 @@
namespace sta {
class TransRiseFall;
class RiseFall;
class MinPulseWidthCheck;
class MinPulseWidthCheckVisitor;
@ -68,7 +68,7 @@ public:
MinPulseWidthCheck(Path *open_path);
MinPulseWidthCheck *copy();
Pin *pin(const StaState *sta) const;
const TransRiseFall *openTransition(const StaState *sta) const;
const RiseFall *openTransition(const StaState *sta) const;
Arrival width(const StaState *sta) const;
float minWidth(const StaState *sta) const;
Slack slack(const StaState *sta) const;

56
search/CheckSlewLimits.cc
View File

@ -63,13 +63,13 @@ PinSlewLimitSlackLess::operator()(Pin *pin1,
Pin *pin2) const
{
const Corner *corner1, *corner2;
const TransRiseFall *tr1, *tr2;
const RiseFall *rf1, *rf2;
Slew slew1, slew2;
float limit1, limit2, slack1, slack2;
check_slew_limit_->checkSlews(pin1, corner_, min_max_,
corner1, tr1, slew1, limit1, slack1);
corner1, rf1, slew1, limit1, slack1);
check_slew_limit_->checkSlews(pin2, corner_, min_max_,
corner2, tr2, slew2, limit2, slack2);
corner2, rf2, slew2, limit2, slack2);
return slack1 < slack2
|| (fuzzyEqual(slack1, slack2)
// Break ties for the sake of regression stability.
@ -102,23 +102,23 @@ CheckSlewLimits::checkSlews(const Pin *pin,
const MinMax *min_max,
// Return values.
const Corner *&corner1,
const TransRiseFall *&tr,
const RiseFall *&rf,
Slew &slew,
float &limit,
float &slack) const
{
corner1 = nullptr;
tr = nullptr;
rf = nullptr;
slew = 0.0;
limit = 0.0;
slack = MinMax::min()->initValue();
if (corner)
checkSlews1(pin, corner, min_max,
corner1, tr, slew, limit, slack);
corner1, rf, slew, limit, slack);
else {
for (auto corner : *sta_->corners()) {
checkSlews1(pin, corner, min_max,
corner1, tr, slew, limit, slack);
corner1, rf, slew, limit, slack);
}
}
}
@ -129,7 +129,7 @@ CheckSlewLimits::checkSlews1(const Pin *pin,
const MinMax *min_max,
// Return values.
const Corner *&corner1,
const TransRiseFall *&tr,
const RiseFall *&rf,
Slew &slew,
float &limit,
float &slack) const
@ -137,10 +137,10 @@ CheckSlewLimits::checkSlews1(const Pin *pin,
Vertex *vertex, *bidirect_drvr_vertex;
sta_->graph()->pinVertices(pin, vertex, bidirect_drvr_vertex);
checkSlews1(vertex, corner, min_max,
corner1, tr, slew, limit, slack);
corner1, rf, slew, limit, slack);
if (bidirect_drvr_vertex)
checkSlews1(bidirect_drvr_vertex, corner, min_max,
corner1, tr, slew, limit, slack);
corner1, rf, slew, limit, slack);
}
void
@ -149,18 +149,18 @@ CheckSlewLimits::checkSlews1(Vertex *vertex,
const MinMax *min_max,
// Return values.
const Corner *&corner,
const TransRiseFall *&tr,
const RiseFall *&rf,
Slew &slew,
float &limit,
float &slack) const
{
for (auto tr1 : TransRiseFall::range()) {
for (auto rf1 : RiseFall::range()) {
float limit1;
bool limit1_exists;
findLimit(vertex->pin(), vertex, tr1, min_max, limit1, limit1_exists);
findLimit(vertex->pin(), vertex, rf1, min_max, limit1, limit1_exists);
if (limit1_exists) {
checkSlew(vertex, corner1, min_max, tr1, limit1,
corner, tr, slew, slack, limit);
checkSlew(vertex, corner1, min_max, rf1, limit1,
corner, rf, slew, slack, limit);
}
}
}
@ -168,7 +168,7 @@ CheckSlewLimits::checkSlews1(Vertex *vertex,
void
CheckSlewLimits::findLimit(const Pin *pin,
const Vertex *vertex,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &limit,
@ -188,7 +188,7 @@ CheckSlewLimits::findLimit(const Pin *pin,
PathClkOrData clk_data = is_clk ? PathClkOrData::clk : PathClkOrData::data;
float clk_limit;
bool clk_limit_exists;
sdc->slewLimit(clk, tr, clk_data, min_max,
sdc->slewLimit(clk, rf, clk_data, min_max,
clk_limit, clk_limit_exists);
if (clk_limit_exists
&& (!exists
@ -263,17 +263,17 @@ void
CheckSlewLimits::checkSlew(Vertex *vertex,
const Corner *corner1,
const MinMax *min_max,
const TransRiseFall *tr1,
const RiseFall *rf1,
float limit1,
// Return values.
const Corner *&corner,
const TransRiseFall *&tr,
const RiseFall *&rf,
Slew &slew,
float &slack,
float &limit) const
{
const DcalcAnalysisPt *dcalc_ap = corner1->findDcalcAnalysisPt(min_max);
Slew slew1 = sta_->graph()->slew(vertex, tr1, dcalc_ap->index());
Slew slew1 = sta_->graph()->slew(vertex, rf1, dcalc_ap->index());
float slew2 = delayAsFloat(slew1);
float slack1 = (min_max == MinMax::max())
? limit1 - slew2 : slew2 - limit1;
@ -281,9 +281,9 @@ CheckSlewLimits::checkSlew(Vertex *vertex,
|| (slack1 < slack
// Break ties for the sake of regression stability.
|| (fuzzyEqual(slack1, slack)
&& tr1->index() < tr->index()))) {
&& rf1->index() < rf->index()))) {
corner = corner1;
tr = tr1;
rf = rf1;
slew = slew1;
slack = slack1;
limit = limit1;
@ -320,11 +320,11 @@ CheckSlewLimits::pinSlewLimitViolations(Instance *inst,
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
const Corner *corner1;
const TransRiseFall *tr;
const RiseFall *rf;
Slew slew;
float limit, slack;
checkSlews(pin, corner, min_max, corner1, tr, slew, limit, slack );
if (tr && slack < 0.0)
checkSlews(pin, corner, min_max, corner1, rf, slew, limit, slack );
if (rf && slack < 0.0)
violators->push_back(pin);
}
delete pin_iter;
@ -363,11 +363,11 @@ CheckSlewLimits::pinMinSlewLimitSlack(Instance *inst,
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
const Corner *corner1;
const TransRiseFall *tr;
const RiseFall *rf;
Slew slew;
float limit, slack;
checkSlews(pin, corner, min_max, corner1, tr, slew, limit, slack);
if (tr
checkSlews(pin, corner, min_max, corner1, rf, slew, limit, slack);
if (rf
&& (min_slack_pin == 0
|| slack < min_slack)) {
min_slack_pin = pin;

12
search/CheckSlewLimits.hh
View File

@ -41,7 +41,7 @@ public:
// Return values.
// Corner is nullptr for no slew limit.
const Corner *&corner1,
const TransRiseFall *&tr,
const RiseFall *&rf,
Slew &slew,
float &limit,
float &slack) const;
@ -58,7 +58,7 @@ protected:
const MinMax *min_max,
// Return values.
const Corner *&corner1,
const TransRiseFall *&tr,
const RiseFall *&rf,
Slew &slew,
float &limit,
float &slack) const;
@ -67,24 +67,24 @@ protected:
const MinMax *min_max,
// Return values.
const Corner *&corner,
const TransRiseFall *&tr,
const RiseFall *&rf,
Slew &slew,
float &limit,
float &slack) const;
void checkSlew(Vertex *vertex,
const Corner *corner1,
const MinMax *min_max,
const TransRiseFall *tr1,
const RiseFall *rf1,
float limit1,
// Return values.
const Corner *&corner,
const TransRiseFall *&tr,
const RiseFall *&rf,
Slew &slew,
float &slack,
float &limit) const;
void findLimit(const Pin *pin,
const Vertex *vertex,
const TransRiseFall *tr,
const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &limit1,

6
search/ClkInfo.cc
View File

@ -40,7 +40,7 @@ ClkInfo::ClkInfo(ClockEdge *clk_edge,
bool is_propagated,
const Pin *gen_clk_src,
bool is_gen_clk_src_path,
const TransRiseFall *pulse_clk_sense,
const RiseFall *pulse_clk_sense,
Arrival insertion,
float latency,
ClockUncertainties *uncertainties,
@ -152,11 +152,11 @@ ClkInfo::clock() const
return nullptr;
}
TransRiseFall *
RiseFall *
ClkInfo::pulseClkSense() const
{
if (is_pulse_clk_)
return TransRiseFall::find(pulse_clk_sense_);
return RiseFall::find(pulse_clk_sense_);
else
return nullptr;
}

6
search/ClkInfo.hh
View File

@ -34,7 +34,7 @@ public:
bool is_propagated,
const Pin *gen_clk_src,
bool is_gen_clk_src_path,
const TransRiseFall *pulse_clk_sense,
const RiseFall *pulse_clk_sense,
Arrival insertion,
float latency,
ClockUncertainties *uncertainties,
@ -49,7 +49,7 @@ public:
bool isPropagated() const { return is_propagated_; }
const Pin *genClkSrc() const { return gen_clk_src_; }
bool isPulseClk() const { return is_pulse_clk_; }
TransRiseFall *pulseClkSense() const;
RiseFall *pulseClkSense() const;
int pulseClkSenseTrIndex() const { return pulse_clk_sense_; }
float latency() const { return latency_; }
Arrival &insertion() { return insertion_; }
@ -87,7 +87,7 @@ private:
unsigned int is_propagated_:1;
unsigned int is_gen_clk_src_path_:1;
unsigned int is_pulse_clk_:1;
unsigned int pulse_clk_sense_:TransRiseFall::index_bit_count;
unsigned int pulse_clk_sense_:RiseFall::index_bit_count;
unsigned int path_ap_index_:path_ap_index_bit_count;
};

30
search/ClkSkew.cc
View File

@ -181,11 +181,11 @@ ClkSkews::findClkSkew(ClockSet *clks,
Edge *edge = edge_iter.next();
if (edge->role()->genericRole() == TimingRole::regClkToQ()) {
Vertex *q_vertex = edge->to(graph_);
TransRiseFall *tr = edge->timingArcSet()->isRisingFallingEdge();
TransRiseFallBoth *src_tr = tr
? tr->asRiseFallBoth()
: TransRiseFallBoth::riseFall();
findClkSkewFrom(src_vertex, q_vertex, src_tr, clks,
RiseFall *rf = edge->timingArcSet()->isRisingFallingEdge();
RiseFallBoth *src_rf = rf
? rf->asRiseFallBoth()
: RiseFallBoth::riseFall();
findClkSkewFrom(src_vertex, q_vertex, src_rf, clks,
corner, setup_hold, skews);
}
}
@ -210,7 +210,7 @@ ClkSkews::hasClkPaths(Vertex *vertex,
void
ClkSkews::findClkSkewFrom(Vertex *src_vertex,
Vertex *q_vertex,
TransRiseFallBoth *src_tr,
RiseFallBoth *src_rf,
ClockSet *clks,
const Corner *corner,
const SetupHold *setup_hold,
@ -231,11 +231,11 @@ ClkSkews::findClkSkewFrom(Vertex *src_vertex,
|| ((setup_hold == SetupHold::min()
&& role->genericRole() == TimingRole::hold())))) {
Vertex *tgt_vertex = edge->from(graph_);
TransRiseFall *tgt_tr1 = edge->timingArcSet()->isRisingFallingEdge();
TransRiseFallBoth *tgt_tr = tgt_tr1
? tgt_tr1->asRiseFallBoth()
: TransRiseFallBoth::riseFall();
findClkSkew(src_vertex, src_tr, tgt_vertex, tgt_tr,
RiseFall *tgt_rf1 = edge->timingArcSet()->isRisingFallingEdge();
RiseFallBoth *tgt_rf = tgt_rf1
? tgt_rf1->asRiseFallBoth()
: RiseFallBoth::riseFall();
findClkSkew(src_vertex, src_rf, tgt_vertex, tgt_rf,
clks, corner, setup_hold, skews);
}
}
@ -244,9 +244,9 @@ ClkSkews::findClkSkewFrom(Vertex *src_vertex,
void
ClkSkews::findClkSkew(Vertex *src_vertex,
TransRiseFallBoth *src_tr,
RiseFallBoth *src_rf,
Vertex *tgt_vertex,
TransRiseFallBoth *tgt_tr,
RiseFallBoth *tgt_rf,
ClockSet *clks,
const Corner *corner,
const SetupHold *setup_hold,
@ -258,7 +258,7 @@ ClkSkews::findClkSkew(Vertex *src_vertex,
while (src_iter.hasNext()) {
PathVertex *src_path = src_iter.next();
Clock *src_clk = src_path->clock(this);
if (src_tr->matches(src_path->transition(this))
if (src_rf->matches(src_path->transition(this))
&& src_path->minMax(this) == setup_hold
&& clks->hasKey(src_clk)) {
Corner *src_corner = src_path->pathAnalysisPt(this)->corner();
@ -269,7 +269,7 @@ ClkSkews::findClkSkew(Vertex *src_vertex,
PathVertex *tgt_path = tgt_iter.next();
Clock *tgt_clk = tgt_path->clock(this);
if (tgt_clk == src_clk
&& tgt_tr->matches(tgt_path->transition(this))
&& tgt_rf->matches(tgt_path->transition(this))
&& tgt_path->minMax(this) == tgt_min_max
&& tgt_path->pathAnalysisPt(this)->corner() == src_corner) {
ClkSkew probe(src_path, tgt_path, this);

6
search/ClkSkew.hh
View File

@ -46,15 +46,15 @@ protected:
ClockSet *clks);
void findClkSkewFrom(Vertex *src_vertex,
Vertex *q_vertex,
TransRiseFallBoth *src_tr,
RiseFallBoth *src_rf,
ClockSet *clks,
const Corner *corner,
const SetupHold *setup_hold,
ClkSkewMap &skews);
void findClkSkew(Vertex *src_vertex,
TransRiseFallBoth *src_tr,
RiseFallBoth *src_rf,
Vertex *tgt_vertex,
TransRiseFallBoth *tgt_tr,
RiseFallBoth *tgt_rf,
ClockSet *clks,
const Corner *corner,
const SetupHold *setup_hold,

88
search/FindRegister.cc
View File

@ -85,7 +85,7 @@ public:
FindRegVisitor(StaState *sta);
virtual ~FindRegVisitor() {}
void visitRegs(ClockSet *clks,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches);
@ -93,7 +93,7 @@ private:
DISALLOW_COPY_AND_ASSIGN(FindRegVisitor);
void visitRegs(const Pin *clk_pin,
TimingSense clk_sense,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches);
virtual void visitReg(Instance *inst) = 0;
@ -101,7 +101,7 @@ private:
Sequential *seq) = 0;
void visitFanoutRegs(Vertex *from_vertex,
TimingSense from_sense,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches,
SearchPred &clk_pred,
@ -110,14 +110,14 @@ private:
Instance *inst,
LibertyCell *cell,
TimingSense clk_sense,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches,
bool &has_seqs,
bool &matches);
bool findInferedSequential(LibertyCell *cell,
TimingSense clk_sense,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches);
bool hasTimingCheck(LibertyCell *cell,
@ -133,7 +133,7 @@ FindRegVisitor::FindRegVisitor(StaState *sta) :
void
FindRegVisitor::visitRegs(ClockSet *clks,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches)
{
@ -148,14 +148,14 @@ FindRegVisitor::visitRegs(ClockSet *clks,
Vertex *vertex, *bidirect_drvr_vertex;
graph_->pinVertices(pin, vertex, bidirect_drvr_vertex);
visitFanoutRegs(vertex, TimingSense::positive_unate,
clk_tr, edge_triggered,
clk_rf, edge_triggered,
latches, clk_pred,
visited_vertices);
// Clocks defined on bidirect pins blow it out both ends.
if (bidirect_drvr_vertex)
visitFanoutRegs(bidirect_drvr_vertex,
TimingSense::positive_unate,
clk_tr, edge_triggered,
clk_rf, edge_triggered,
latches, clk_pred,
visited_vertices);
}
@ -166,7 +166,7 @@ FindRegVisitor::visitRegs(ClockSet *clks,
while (reg_clk_iter.hasNext()) {
Vertex *vertex = reg_clk_iter.next();
visitRegs(vertex->pin(), TimingSense::positive_unate,
TransRiseFallBoth::riseFall(),
RiseFallBoth::riseFall(),
edge_triggered, latches);
}
}
@ -175,7 +175,7 @@ FindRegVisitor::visitRegs(ClockSet *clks,
void
FindRegVisitor::visitFanoutRegs(Vertex *from_vertex,
TimingSense from_sense,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches,
SearchPred &clk_pred,
@ -191,11 +191,11 @@ FindRegVisitor::visitFanoutRegs(Vertex *from_vertex,
const Pin *to_pin = to_vertex->pin();
TimingSense to_sense = pathSenseThru(from_sense, edge->sense());
if (to_vertex->isRegClk())
visitRegs(to_pin, to_sense, clk_tr, edge_triggered, latches);
visitRegs(to_pin, to_sense, clk_rf, edge_triggered, latches);
// Even register clock pins can have combinational fanout arcs.
if (clk_pred.searchThru(edge)
&& clk_pred.searchTo(to_vertex))
visitFanoutRegs(to_vertex, to_sense, clk_tr, edge_triggered, latches,
visitFanoutRegs(to_vertex, to_sense, clk_rf, edge_triggered, latches,
clk_pred, visited_vertices);
}
}
@ -204,20 +204,20 @@ FindRegVisitor::visitFanoutRegs(Vertex *from_vertex,
void
FindRegVisitor::visitRegs(const Pin *clk_pin,
TimingSense clk_sense,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches)
{
Instance *inst = network_->instance(clk_pin);
LibertyCell *cell = network_->libertyCell(inst);
if (!edge_triggered || !latches
|| clk_tr != TransRiseFallBoth::riseFall()) {
|| clk_rf != RiseFallBoth::riseFall()) {
bool matches, has_seqs;
findSequential(clk_pin, inst, cell, clk_sense, clk_tr,
findSequential(clk_pin, inst, cell, clk_sense, clk_rf,
edge_triggered, latches,
has_seqs, matches);
if (!has_seqs)
matches = findInferedSequential(cell, clk_sense, clk_tr,
matches = findInferedSequential(cell, clk_sense, clk_rf,
edge_triggered, latches);
if (matches)
visitReg(inst);
@ -233,7 +233,7 @@ FindRegVisitor::findSequential(const Pin *clk_pin,
Instance *inst,
LibertyCell *cell,
TimingSense clk_sense,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches,
bool &has_seqs,
@ -247,7 +247,7 @@ FindRegVisitor::findSequential(const Pin *clk_pin,
Sequential *seq = seq_iter.next();
if ((seq->isRegister() && edge_triggered)
|| (seq->isLatch() && latches)) {
if (clk_tr == TransRiseFallBoth::riseFall()) {
if (clk_rf == RiseFallBoth::riseFall()) {
visitSequential(inst, seq);
matches = true;
break;
@ -258,9 +258,9 @@ FindRegVisitor::findSequential(const Pin *clk_pin,
TimingSense port_sense = clk_func->portTimingSense(port);
TimingSense path_sense = pathSenseThru(clk_sense, port_sense);
if ((path_sense == TimingSense::positive_unate
&& clk_tr == TransRiseFallBoth::rise())
&& clk_rf == RiseFallBoth::rise())
|| (path_sense == TimingSense::negative_unate
&& clk_tr == TransRiseFallBoth::fall())) {
&& clk_rf == RiseFallBoth::fall())) {
visitSequential(inst, seq);
matches = true;
break;
@ -273,22 +273,22 @@ FindRegVisitor::findSequential(const Pin *clk_pin,
bool
FindRegVisitor::findInferedSequential(LibertyCell *cell,
TimingSense clk_sense,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches)
{
bool matches = false;
const TransRiseFall *clk_tr1 = clk_tr->asRiseFall();
const RiseFall *clk_rf1 = clk_rf->asRiseFall();
LibertyCellTimingArcSetIterator set_iter(cell);
while (set_iter.hasNext()) {
TimingArcSet *set = set_iter.next();
TimingArcSetArcIterator arc_iter(set);
TimingArc *arc = arc_iter.next();
TransRiseFall *arc_clk_tr = arc->fromTrans()->asRiseFall();
bool tr_matches = (clk_tr == TransRiseFallBoth::riseFall()
|| (arc_clk_tr == clk_tr1
RiseFall *arc_clk_rf = arc->fromTrans()->asRiseFall();
bool tr_matches = (clk_rf == RiseFallBoth::riseFall()
|| (arc_clk_rf == clk_rf1
&& clk_sense == TimingSense::positive_unate)
|| (arc_clk_tr == clk_tr1->opposite()
|| (arc_clk_rf == clk_rf1->opposite()
&& clk_sense == TimingSense::negative_unate));
TimingRole *role = set->role();
if (tr_matches
@ -323,7 +323,7 @@ class FindRegInstances : public FindRegVisitor
public:
explicit FindRegInstances(StaState *sta);
InstanceSet *findRegs(ClockSet *clks,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches);
@ -344,12 +344,12 @@ FindRegInstances::FindRegInstances(StaState *sta) :
InstanceSet *
FindRegInstances::findRegs(ClockSet *clks,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches)
{
regs_ = new InstanceSet;
visitRegs(clks, clk_tr, edge_triggered, latches);
visitRegs(clks, clk_rf, edge_triggered, latches);
return regs_;
}
@ -367,13 +367,13 @@ FindRegInstances::visitReg(Instance *inst)
InstanceSet *
findRegInstances(ClockSet *clks,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches,
StaState *sta)
{
FindRegInstances find_regs(sta);
return find_regs.findRegs(clks, clk_tr, edge_triggered, latches);
return find_regs.findRegs(clks, clk_rf, edge_triggered, latches);
}
////////////////////////////////////////////////////////////////
@ -383,7 +383,7 @@ class FindRegPins : public FindRegVisitor
public:
explicit FindRegPins(StaState *sta);
PinSet *findPins(ClockSet *clks,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches);
@ -411,12 +411,12 @@ FindRegPins::FindRegPins(StaState *sta) :
PinSet *
FindRegPins::findPins(ClockSet *clks,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches)
{
pins_ = new PinSet;
visitRegs(clks, clk_tr, edge_triggered, latches);
visitRegs(clks, clk_rf, edge_triggered, latches);
return pins_;
}
@ -509,22 +509,22 @@ hasMinPulseWidthCheck(LibertyPort *port)
{
float ignore;
bool exists;
port->minPulseWidth(TransRiseFall::rise(), ignore, exists);
port->minPulseWidth(RiseFall::rise(), ignore, exists);
if (exists)
return true;
port->minPulseWidth(TransRiseFall::fall(), ignore, exists);
port->minPulseWidth(RiseFall::fall(), ignore, exists);
return exists;
}
PinSet *
findRegDataPins(ClockSet *clks,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches,
StaState *sta)
{
FindRegDataPins find_regs(sta);
return find_regs.findPins(clks, clk_tr, edge_triggered, latches);
return find_regs.findPins(clks, clk_rf, edge_triggered, latches);
}
////////////////////////////////////////////////////////////////
@ -576,13 +576,13 @@ FindRegClkPins::seqExpr2(Sequential *)
PinSet *
findRegClkPins(ClockSet *clks,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches,
StaState *sta)
{
FindRegClkPins find_regs(sta);
return find_regs.findPins(clks, clk_tr, edge_triggered, latches);
return find_regs.findPins(clks, clk_rf, edge_triggered, latches);
}
////////////////////////////////////////////////////////////////
@ -621,13 +621,13 @@ FindRegAsyncPins::matchPin(Pin *pin)
PinSet *
findRegAsyncPins(ClockSet *clks,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches,
StaState *sta)
{
FindRegAsyncPins find_regs(sta);
return find_regs.findPins(clks, clk_tr, edge_triggered, latches);
return find_regs.findPins(clks, clk_rf, edge_triggered, latches);
}
////////////////////////////////////////////////////////////////
@ -715,13 +715,13 @@ FindRegOutputPins::seqExpr2(Sequential *)
PinSet *
findRegOutputPins(ClockSet *clks,
const TransRiseFallBoth *clk_tr,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches,
StaState *sta)
{
FindRegOutputPins find_regs(sta);
return find_regs.findPins(clks, clk_tr, edge_triggered, latches);
return find_regs.findPins(clks, clk_rf, edge_triggered, latches);
}
////////////////////////////////////////////////////////////////

10
search/FindRegister.hh
View File

@ -25,19 +25,19 @@
namespace sta {
InstanceSet *
findRegInstances(ClockSet *clks, const TransRiseFallBoth *clk_tr,
findRegInstances(ClockSet *clks, const RiseFallBoth *clk_rf,
bool edge_triggered, bool latches, StaState *sta);
PinSet *
findRegDataPins(ClockSet *clks, const TransRiseFallBoth *clk_tr,
findRegDataPins(ClockSet *clks, const RiseFallBoth *clk_rf,
bool edge_triggered, bool latches, StaState *sta);
PinSet *
findRegClkPins(ClockSet *clks, const TransRiseFallBoth *clk_tr,
findRegClkPins(ClockSet *clks, const RiseFallBoth *clk_rf,
bool edge_triggered, bool latches, StaState *sta);
PinSet *
findRegAsyncPins(ClockSet *clks, const TransRiseFallBoth *clk_tr,
findRegAsyncPins(ClockSet *clks, const RiseFallBoth *clk_rf,
bool edge_triggered, bool latches, StaState *sta);
PinSet *
findRegOutputPins(ClockSet *clks, const TransRiseFallBoth *clk_tr,
findRegOutputPins(ClockSet *clks, const RiseFallBoth *clk_rf,
bool edge_triggered, bool latches, StaState *sta);
void

14
search/GatedClk.cc
View File

@ -230,28 +230,28 @@ GatedClk::functionClkOperands(FuncExpr *root_expr,
}
}
TransRiseFall *
RiseFall *
GatedClk::gatedClkActiveTrans(LogicValue active_value,
const MinMax *min_max) const
{
TransRiseFall *leading_tr;
RiseFall *leading_rf;
switch (active_value) {
case LogicValue::one:
case LogicValue::unknown:
leading_tr = TransRiseFall::rise();
leading_rf = RiseFall::rise();
break;
case LogicValue::zero:
leading_tr = TransRiseFall::fall();
leading_rf = RiseFall::fall();
break;
default:
internalError("illegal gated clock active value");
leading_tr = TransRiseFall::rise();
leading_rf = RiseFall::rise();
break;
}
if (min_max == MinMax::max())
return leading_tr;
return leading_rf;
else
return leading_tr->opposite();
return leading_rf->opposite();
}
} // namespace

2
search/GatedClk.hh
View File

@ -38,7 +38,7 @@ public:
void gatedClkEnables(Vertex *clk_vertex,
// Return value.
PinSet &enable_pins);
TransRiseFall *gatedClkActiveTrans(LogicValue active_value,
RiseFall *gatedClkActiveTrans(LogicValue active_value,
const MinMax *min_max) const;
protected:

46
search/Genclks.cc
View File

@ -691,7 +691,7 @@ Genclks::makeSrcFilter(Clock *gclk)
{
ClockSet *from_clks = new ClockSet;
from_clks->insert(gclk->masterClk());
const TransRiseFallBoth *rf = TransRiseFallBoth::riseFall();
const RiseFallBoth *rf = RiseFallBoth::riseFall();
ExceptionFrom *from = sdc_->makeExceptionFrom(nullptr,from_clks,nullptr,rf);
PinSet *thru_pins = new PinSet;
@ -723,7 +723,7 @@ Genclks::seedSrcPins(Clock *gclk,
for (auto path_ap : corners_->pathAnalysisPts()) {
const MinMax *min_max = path_ap->pathMinMax();
const EarlyLate *early_late = min_max;
for (auto tr : TransRiseFall::range()) {
for (auto tr : RiseFall::range()) {
Tag *tag = makeTag(gclk, master_clk, master_pin, tr, src_filter,
path_ap);
Arrival insert = search_->clockInsertion(master_clk, master_pin, tr,
@ -740,7 +740,7 @@ Tag *
Genclks::makeTag(const Clock *gclk,
const Clock *master_clk,
const Pin *master_pin,
const TransRiseFall *master_tr,
const RiseFall *master_rf,
FilterPath *src_filter,
const PathAnalysisPt *path_ap)
{
@ -751,11 +751,11 @@ Genclks::makeTag(const Clock *gclk,
state = state->nextState();
ExceptionStateSet *states = new ExceptionStateSet;
states->insert(state);
ClkInfo *clk_info = search_->findClkInfo(master_clk->edge(master_tr),
ClkInfo *clk_info = search_->findClkInfo(master_clk->edge(master_rf),
master_pin, true, nullptr, true,
nullptr, 0.0, 0.0, nullptr,
path_ap, nullptr);
return search_->findTag(master_tr, path_ap, clk_info, false, nullptr, false,
return search_->findTag(master_rf, path_ap, clk_info, false, nullptr, false,
states, true);
}
@ -928,16 +928,16 @@ Genclks::clearSrcPaths()
}
int
Genclks::srcPathIndex(const TransRiseFall *clk_tr,
Genclks::srcPathIndex(const RiseFall *clk_rf,
const PathAnalysisPt *path_ap) const
{
return path_ap->index() * TransRiseFall::index_count + clk_tr->index();
return path_ap->index() * RiseFall::index_count + clk_rf->index();
}
void
Genclks::recordSrcPaths(Clock *gclk)
{
int path_count = TransRiseFall::index_count
int path_count = RiseFall::index_count
* corners_->pathAnalysisPtCount();
bool divide_by_1 = gclk->isDivideByOneCombinational();
@ -957,16 +957,16 @@ Genclks::recordSrcPaths(Clock *gclk)
if (src_clk_edge
&& matchesSrcFilter(path, gclk)) {
const EarlyLate *early_late = path->minMax(this);
TransRiseFall *src_clk_tr = src_clk_edge->transition();
const TransRiseFall *tr = path->transition(this);
bool inverting_path = (tr != src_clk_tr);
RiseFall *src_clk_rf = src_clk_edge->transition();
const RiseFall *rf = path->transition(this);
bool inverting_path = (rf != src_clk_rf);
const PathAnalysisPt *path_ap = path->pathAnalysisPt(this);
int path_index = srcPathIndex(tr, path_ap);
int path_index = srcPathIndex(rf, path_ap);
PathVertexRep &src_path = src_paths[path_index];
if ((!divide_by_1
|| (inverting_path == invert))
&& (!has_edges
|| src_clk_tr == gclk->masterClkEdgeTr(tr))
|| src_clk_rf == gclk->masterClkEdgeTr(rf))
&& (src_path.isNull()
|| fuzzyGreater(path->arrival(this),
src_path.arrival(this),
@ -974,7 +974,7 @@ Genclks::recordSrcPaths(Clock *gclk)
debugPrint4(debug_, "genclk", 2, " %s insertion %s %s %s\n",
network_->pathName(gclk_pin),
early_late->asString(),
tr->asString(),
rf->asString(),
delayAsString(path->arrival(this), this));
src_path.init(path, this);
found_src_paths = true;
@ -1042,7 +1042,7 @@ Genclks::srcPath(const ClockEdge *clk_edge,
void
Genclks::srcPath(const Clock *gclk,
const Pin *src_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const PathAnalysisPt *path_ap,
// Return value.
PathVertex &src_path) const
@ -1050,7 +1050,7 @@ Genclks::srcPath(const Clock *gclk,
PathVertexRep *src_paths =
genclk_src_paths_.findKey(ClockPinPair(gclk, src_pin));
if (src_paths) {
int path_index = srcPathIndex(tr, path_ap);
int path_index = srcPathIndex(rf, path_ap);
src_path.init(src_paths[path_index], this);
}
else
@ -1060,17 +1060,17 @@ Genclks::srcPath(const Clock *gclk,
Arrival
Genclks::insertionDelay(const Clock *clk,
const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const EarlyLate *early_late,
const PathAnalysisPt *path_ap) const
{
PathVertex src_path;
PathAnalysisPt *insert_ap = path_ap->insertionAnalysisPt(early_late);
srcPath(clk, pin, tr, insert_ap, src_path);
srcPath(clk, pin, rf, insert_ap, src_path);
if (clk->pllFdbk()) {
const MinMax *min_max = path_ap->pathMinMax();
PathAnalysisPt *pll_ap = path_ap->insertionAnalysisPt(min_max->opposite());
Arrival pll_delay = pllDelay(clk, tr, pll_ap);
Arrival pll_delay = pllDelay(clk, rf, pll_ap);
if (src_path.isNull())
return -pll_delay;
else {
@ -1112,7 +1112,7 @@ Genclks::makePllFilter(const Clock *gclk)
{
PinSet *from_pins = new PinSet;
from_pins->insert(gclk->pllOut());
TransRiseFallBoth *rf = TransRiseFallBoth::riseFall();
RiseFallBoth *rf = RiseFallBoth::riseFall();
ExceptionFrom *from = sdc_->makeExceptionFrom(from_pins,nullptr,nullptr,rf);
PinSet *to_pins = new PinSet;
@ -1135,7 +1135,7 @@ Genclks::seedPllPin(const Clock *gclk,
tag_bldr.init(vertex);
copyGenClkSrcPaths(vertex, &tag_bldr);
for (auto path_ap : corners_->pathAnalysisPts()) {
for (auto tr : TransRiseFall::range()) {
for (auto tr : RiseFall::range()) {
Tag *tag = makeTag(gclk, gclk, pll_out_pin, tr, pll_filter, path_ap);
tag_bldr.setArrival(tag, 0.0, nullptr);
}
@ -1217,14 +1217,14 @@ Genclks::findPllArrivals(const Clock *gclk,
Arrival
Genclks::pllDelay(const Clock *clk,
const TransRiseFall *tr,
const RiseFall *rf,
const PathAnalysisPt *path_ap) const
{
Vertex *fdbk_vertex = graph_->pinLoadVertex(clk->pllFdbk());
GenclkInfo *genclk_info = genclkInfo(clk);
if (genclk_info) {
FilterPath *pll_filter = genclk_info->pllFilter();
VertexPathIterator fdbk_path_iter(fdbk_vertex, tr, path_ap, this);
VertexPathIterator fdbk_path_iter(fdbk_vertex, rf, path_ap, this);
while (fdbk_path_iter.hasNext()) {
Path *path = fdbk_path_iter.next();
if (matchesPllFilter(path, pll_filter))

10
search/Genclks.hh
View File

@ -59,7 +59,7 @@ public:
// Generated clock insertion delay.
Arrival insertionDelay(const Clock *clk,
const Pin *pin,
const TransRiseFall *tr,
const RiseFall *rf,
const EarlyLate *early_late,
const PathAnalysisPt *path_ap) const;
// Generated clock source path for a clock path root.
@ -74,12 +74,12 @@ public:
PathVertex &src_path) const;
void srcPath(const Clock *clk,
const Pin *src_pin,
const TransRiseFall *tr,
const RiseFall *rf,
const PathAnalysisPt *path_ap,
// Return value.
PathVertex &src_path) const;
Arrival pllDelay(const Clock *clk,
const TransRiseFall *tr,
const RiseFall *rf,
const PathAnalysisPt *path_ap) const;
Vertex *srcPathVertex(const Pin *pin) const;
Level clkPinMaxLevel(Clock *clk) const;
@ -95,7 +95,7 @@ private:
void seedClkVertices(Clock *clk,
BfsBkwdIterator &iter,
VertexSet *fanins);
int srcPathIndex(const TransRiseFall *clk_tr,
int srcPathIndex(const RiseFall *clk_rf,
const PathAnalysisPt *path_ap) const;
bool matchesSrcFilter(Path *path,
const Clock *gclk) const;
@ -119,7 +119,7 @@ private:
virtual Tag *makeTag(const Clock *gclk,
const Clock *master_clk,
const Pin *master_pin,
const TransRiseFall *tr,
const RiseFall *rf,
FilterPath *src_filter,
const PathAnalysisPt *path_ap);
void seedSrcPins(Clock *clk,

44
search/Latches.cc
View File

@ -205,11 +205,11 @@ Latches::latchRequired(const Path *data_path,
Delay &time_given_to_startpoint)
{
Vertex *data_vertex = data_path->vertex(this);
const TransRiseFall *data_tr = data_path->transition(this);
ArcDelay setup = latchSetupMargin(data_vertex,data_tr,disable_path,path_ap);
const RiseFall *data_rf = data_path->transition(this);
ArcDelay setup = latchSetupMargin(data_vertex,data_rf,disable_path,path_ap);
ExceptionPath *excpt = search_->exceptionTo(ExceptionPathType::any,
data_path, data_vertex->pin(),
data_tr,
data_rf,
enable_path->clkEdge(this),
path_ap->pathMinMax(), false,
false);
@ -235,8 +235,8 @@ Latches::latchEnableOtherPath(Path *path,
ClockEdge *clk_edge = path->clkEdge(this);
ClockEdge *other_clk_edge =
path->clkInfo(this)->isPulseClk() ? clk_edge:clk_edge->opposite();
TransRiseFall *other_tr = path->transition(this)->opposite();
VertexPathIterator path_iter(vertex, other_tr, tgt_clk_path_ap, this);
RiseFall *other_rf = path->transition(this)->opposite();
VertexPathIterator path_iter(vertex, other_rf, tgt_clk_path_ap, this);
while (path_iter.hasNext()) {
PathVertex *path = path_iter.next();
if (path->isClock(this)
@ -259,11 +259,11 @@ Latches::latchEnablePath(Path *q_path,
const PathAnalysisPt *tgt_clk_path_ap = path_ap->tgtClkAnalysisPt();
const Instance *latch = network_->instance(q_path->pin(this));
Vertex *en_vertex;
TransRiseFall *en_tr;
RiseFall *en_rf;
LatchEnableState state;
latchDtoQEnable(d_q_edge, latch, en_vertex, en_tr, state);
latchDtoQEnable(d_q_edge, latch, en_vertex, en_rf, state);
if (state == LatchEnableState::enabled) {
VertexPathIterator path_iter(en_vertex, en_tr, tgt_clk_path_ap, this);
VertexPathIterator path_iter(en_vertex, en_rf, tgt_clk_path_ap, this);
while (path_iter.hasNext()) {
PathVertex *path = path_iter.next();
const ClockEdge *clk_edge = path->clkEdge(this);
@ -293,9 +293,9 @@ Latches::latchOutArrival(Path *data_path,
Vertex *data_vertex = d_q_edge->from(graph_);
const Instance *inst = network_->instance(data_vertex->pin());
Vertex *enable_vertex;
TransRiseFall *enable_tr;
RiseFall *enable_rf;
LatchEnableState state;
latchDtoQEnable(d_q_edge, inst, enable_vertex, enable_tr, state);
latchDtoQEnable(d_q_edge, inst, enable_vertex, enable_rf, state);
// Latch enable may be missing if library is malformed.
switch (state) {
case LatchEnableState::closed:
@ -313,7 +313,7 @@ Latches::latchOutArrival(Path *data_path,
break;
case LatchEnableState::enabled: {
const PathAnalysisPt *tgt_clk_path_ap = path_ap->tgtClkAnalysisPt();
VertexPathIterator enable_iter(enable_vertex, enable_tr,
VertexPathIterator enable_iter(enable_vertex, enable_rf,
tgt_clk_path_ap, this);
while (enable_iter.hasNext()) {
PathVertex *enable_path = enable_iter.next();
@ -353,7 +353,7 @@ Latches::latchOutArrival(Path *data_path,
en_clk_info->uncertainties(),
path_ap,
crpr_clk_path);
TransRiseFall *q_tr = d_q_arc->toTrans()->asRiseFall();
RiseFall *q_rf = d_q_arc->toTrans()->asRiseFall();
ExceptionStateSet *states = nullptr;
// Latch data pin is a valid exception -from pin.
if (sdc_->exceptionFromStates(data_path->pin(this),
@ -362,11 +362,11 @@ Latches::latchOutArrival(Path *data_path,
MinMax::max(), states)
// -from enable non-filter exceptions apply.
&& sdc_->exceptionFromStates(enable_vertex->pin(),
enable_tr,
enable_rf,
en_clk_edge->clock(),
en_clk_edge->transition(),
MinMax::max(), false, states))
q_tag = search_->findTag(q_tr, path_ap, q_clk_info, false,
q_tag = search_->findTag(q_rf, path_ap, q_clk_info, false,
nullptr, false, states, true);
}
return;
@ -395,13 +395,13 @@ Latches::exceptionTo(Path *data_path,
ArcDelay
Latches::latchSetupMargin(Vertex *data_vertex,
const TransRiseFall *data_tr,
const RiseFall *data_rf,
const Path *disable_path,
const PathAnalysisPt *path_ap)
{
if (disable_path) {
Vertex *enable_vertex = disable_path->vertex(this);
const TransRiseFall *disable_tr = disable_path->transition(this);
const RiseFall *disable_rf = disable_path->transition(this);
VertexInEdgeIterator edge_iter(data_vertex, graph_);
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
@ -415,8 +415,8 @@ Latches::latchSetupMargin(Vertex *data_vertex,
TimingArcSetArcIterator arc_iter(arc_set);
while (arc_iter.hasNext()) {
TimingArc *check_arc = arc_iter.next();
if (check_arc->toTrans()->asRiseFall() == data_tr
&& check_arc->fromTrans()->asRiseFall() == disable_tr)
if (check_arc->toTrans()->asRiseFall() == data_rf
&& check_arc->fromTrans()->asRiseFall() == disable_rf)
return search_->deratedDelay(from_vertex, check_arc, edge,
false, path_ap);
}
@ -458,7 +458,7 @@ Latches::latchDtoQEnable(Edge *d_q_edge,
const Instance *inst,
// Return values.
Vertex *&enable_vertex,
TransRiseFall *&enable_tr,
RiseFall *&enable_rf,
LatchEnableState &state) const
{
enable_vertex = nullptr;
@ -468,7 +468,7 @@ Latches::latchDtoQEnable(Edge *d_q_edge,
TimingArcSet *d_q_set = d_q_edge->timingArcSet();
LibertyPort *enable_port;
FuncExpr *enable_func;
cell->latchEnable(d_q_set, enable_port, enable_func, enable_tr);
cell->latchEnable(d_q_set, enable_port, enable_func, enable_rf);
if (enable_port) {
Pin *enable_pin = network_->findPin(inst, enable_port);
if (enable_pin) {
@ -507,9 +507,9 @@ Latches::latchDtoQState(Edge *edge) const
const Pin *from_pin = from_vertex->pin();
const Instance *inst = network_->instance(from_pin);
Vertex *enable_vertex;
TransRiseFall *enable_tr;
RiseFall *enable_rf;
LatchEnableState state;
latchDtoQEnable(edge, inst, enable_vertex, enable_tr, state);
latchDtoQEnable(edge, inst, enable_vertex, enable_rf, state);
return state;
}

4
search/Latches.hh
View File

@ -76,7 +76,7 @@ public:
const Instance *inst,
// Return values.
Vertex *&enable_vertex,
TransRiseFall *&enable_tr,
RiseFall *&enable_rf,
LatchEnableState &state) const;
LatchEnableState latchDtoQState(Edge *d_q_edge) const;
void latchEnableOtherPath(Path *path,
@ -96,7 +96,7 @@ public:
protected:
ArcDelay latchSetupMargin(Vertex *data_vertex,
const TransRiseFall *data_tr,
const RiseFall *data_rf,
const Path *disable_path,
const PathAnalysisPt *path_ap);
ExceptionPath *exceptionTo(Path *data_path,

6
search/Path.cc
View File

@ -110,7 +110,7 @@ Path::slew(const StaState *sta) const
}
int
Path::trIndex(const StaState *sta) const
Path::rfIndex(const StaState *sta) const
{
return transition(sta)->index();
}
@ -194,8 +194,8 @@ Path::cmpPinTrClk(const Path *path1,
const Pin *pin2 = path2->pin(sta);
const Network *network = sta->network();
if (pin1 == pin2) {
int tr_index1 = path1->trIndex(sta);
int tr_index2 = path2->trIndex(sta);
int tr_index1 = path1->rfIndex(sta);
int tr_index2 = path2->rfIndex(sta);
if (tr_index1 == tr_index2)
return cmpClk(path1, path2, sta);
else if (tr_index1 < tr_index2)

4
search/Path.hh
View File

@ -52,8 +52,8 @@ public:
virtual ClockEdge *clkEdge(const StaState *sta) const;
virtual Clock *clock(const StaState *sta) const;
virtual bool isClock(const StaState *sta) const;
virtual const TransRiseFall *transition(const StaState *sta) const = 0;
virtual int trIndex(const StaState *sta) const;
virtual const RiseFall *transition(const StaState *sta) const = 0;
virtual int rfIndex(const StaState *sta) const;
virtual const MinMax *minMax(const StaState *sta) const;
virtual PathAnalysisPt *pathAnalysisPt(const StaState *sta) const = 0;
virtual PathAPIndex pathAnalysisPtIndex(const StaState *sta) const;

26
search/PathEnd.cc
View File

@ -80,7 +80,7 @@ PathEnd::clkEarlyLate(const StaState *sta) const
return checkRole(sta)->tgtClkEarlyLate();
}
const TransRiseFall *
const RiseFall *
PathEnd::transition(const StaState *sta) const
{
return path_.transition(sta);
@ -122,7 +122,7 @@ PathEnd::requiredTimeOffset(const StaState *sta) const
return requiredTime(sta) + sourceClkOffset(sta);
}
const TransRiseFall *
const RiseFall *
PathEnd::targetClkEndTrans(const StaState *sta) const
{
const PathVertex *clk_path = targetClkPath();
@ -354,14 +354,14 @@ PathEnd::checkTgtClkDelay(const PathVertex *tgt_clk_path,
ClkInfo *clk_info = tgt_clk_path->clkInfo(sta);
const Pin *tgt_src_pin = clk_info->clkSrc();
const Clock *tgt_clk = tgt_clk_edge->clock();
const TransRiseFall *tgt_clk_tr = tgt_clk_edge->transition();
insertion = search->clockInsertion(tgt_clk, tgt_src_pin, tgt_clk_tr,
const RiseFall *tgt_clk_rf = tgt_clk_edge->transition();
insertion = search->clockInsertion(tgt_clk, tgt_src_pin, tgt_clk_rf,
min_max, early_late, tgt_path_ap);
if (clk_info->isPropagated()) {
// Propagated clock. Propagated arrival is seeded with
// early_late==path_min_max insertion delay.
Arrival path_insertion = search->clockInsertion(tgt_clk, tgt_src_pin,
tgt_clk_tr, min_max,
tgt_clk_rf, min_max,
min_max, tgt_path_ap);
latency=tgt_clk_path->arrival(sta)-tgt_clk_edge->time()-path_insertion;
}
@ -913,7 +913,7 @@ PathEndClkConstrainedMcp::findHoldMcps(const ClockEdge *tgt_clk_edge,
{
Pin *pin = path_.pin(sta);
const TransRiseFall *tr = path_.transition(sta);
const RiseFall *rf = path_.transition(sta);
// Mcp may be setup, hold or setup_hold, since all match min paths.
const MinMaxAll *mcp_min_max = mcp_->minMax();
Search *search = sta->search();
@ -921,7 +921,7 @@ PathEndClkConstrainedMcp::findHoldMcps(const ClockEdge *tgt_clk_edge,
hold_mcp = mcp_;
setup_mcp =
dynamic_cast<MultiCyclePath*>(search->exceptionTo(ExceptionPathType::multi_cycle,
path_.path(), pin, tr,
path_.path(), pin, rf,
tgt_clk_edge,
MinMax::max(), true,
false));
@ -930,7 +930,7 @@ PathEndClkConstrainedMcp::findHoldMcps(const ClockEdge *tgt_clk_edge,
setup_mcp = mcp_;
hold_mcp =
dynamic_cast<MultiCyclePath*>(search->exceptionTo(ExceptionPathType::multi_cycle,
path_.path(), pin, tr,
path_.path(), pin, rf,
tgt_clk_edge,
MinMax::min(), true,
false));
@ -1340,9 +1340,9 @@ PathEnd::outputDelayMargin(OutputDelay *output_delay,
const Path *path,
const StaState *sta)
{
const TransRiseFall *tr = path->transition(sta);
const RiseFall *rf = path->transition(sta);
const MinMax *min_max = path->minMax(sta);
float margin = output_delay->delays()->value(tr, min_max);
float margin = output_delay->delays()->value(rf, min_max);
if (min_max == MinMax::max())
return margin;
else
@ -1428,11 +1428,11 @@ PathEndOutputDelay::tgtClkDelay(const ClockEdge *tgt_clk_edge,
const PathAnalysisPt *path_ap = path_.pathAnalysisPt(sta);
const MinMax *latency_min_max = path_ap->tgtClkAnalysisPt()->pathMinMax();
Clock *tgt_clk = tgt_clk_edge->clock();
TransRiseFall *tgt_clk_tr = tgt_clk_edge->transition();
RiseFall *tgt_clk_rf = tgt_clk_edge->transition();
if (!output_delay_->sourceLatencyIncluded())
insertion = sta->search()->clockInsertion(tgt_clk,
tgt_clk->defaultPin(),
tgt_clk_tr,
tgt_clk_rf,
latency_min_max,
early_late, path_ap);
else
@ -1440,7 +1440,7 @@ PathEndOutputDelay::tgtClkDelay(const ClockEdge *tgt_clk_edge,
const Sdc *sdc = sta->sdc();
if (!tgt_clk->isPropagated()
&& !output_delay_->networkLatencyIncluded())
latency = sdc->clockLatency(tgt_clk, tgt_clk_tr, latency_min_max);
latency = sdc->clockLatency(tgt_clk, tgt_clk_rf, latency_min_max);
else
latency = 0.0;
}

6
search/PathEnd.hh
View File

@ -30,7 +30,7 @@
namespace sta {
class StaState;
class TransRiseFall;
class RiseFall;
class MinMax;
class ReportPath;
@ -77,7 +77,7 @@ public:
// Synonym for minMax().
const EarlyLate *pathEarlyLate(const StaState *sta) const;
virtual const EarlyLate *clkEarlyLate(const StaState *sta) const;
const TransRiseFall *transition(const StaState *sta) const;
const RiseFall *transition(const StaState *sta) const;
PathAnalysisPt *pathAnalysisPt(const StaState *sta) const;
PathAPIndex pathIndex(const StaState *sta) const;
virtual void reportShort(ReportPath *report,
@ -118,7 +118,7 @@ public:
virtual const PathVertex *targetClkPath() const;
virtual Clock *targetClk(const StaState *sta) const;
virtual ClockEdge *targetClkEdge(const StaState *sta) const;
const TransRiseFall *targetClkEndTrans(const StaState *sta) const;
const RiseFall *targetClkEndTrans(const StaState *sta) const;
// Target clock with cycle accounting and source clock offsets.
virtual float targetClkTime(const StaState *sta) const;
// Time offset for the target clock.

Some files were not shown because too many files have changed in this diff Show More