2018/12/24 all_fanout from input port
This commit is contained in:
James Cherry
parent
0a693f3236
commit
4f381f6669
7
INSTALL
7
INSTALL
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@ -34,7 +34,7 @@ tcl 8.2 8.6 8.6.6
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These packages are optional:
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libz 1.1.4 1.2.5 1.2.8
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cudd 2.4.1 2.5.0
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cudd 2.4.1 3.0.0
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Use the following commands to unpack the dist file and compile it.
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@ -60,9 +60,10 @@ configure options:
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--with-visualstudio use Microcruft Visual Studio C++ compiler
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CUDD is a BDD package that is used to improve conditional timing arc
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handling. It is available from the following url:
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handling. It is available here:
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ftp://vlsi.colorado.edu/pub/cudd-2.5.0.tar.gz
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https://www.davidkebo.com/source/cudd_versions/cudd-3.0.0.tar.gz
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https://sourceforge.net/projects/cudd-mirror/
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The Zlib library is an optional. If the configure script finds libz,
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OpenSTA can read Verilog, SDF, SPF, and SPEF files compressed with
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15
configure.ac
15
configure.ac
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@ -16,7 +16,7 @@
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# Process this file with autoconf to produce a configure script.
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AC_INIT(sta, 2.0)
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AC_INIT(sta, 2.0.1)
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AM_INIT_AUTOMAKE
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AC_CONFIG_MACRO_DIR([m4])
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AC_CONFIG_HEADERS(config.h)
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@ -173,7 +173,7 @@ AC_ARG_WITH(tcl,
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[])
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AC_ARG_WITH(cudd,
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[AS_HELP_STRING([--with-cudd=path],[use Cudd BDD package, defaults to $CUDD])],
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[AS_HELP_STRING([--with-cudd=path],[use CUDD BDD package, defaults to $CUDD])],
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[CUDD_ARG="${withval}"],
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[CUDD_ARG=$CUDD])
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@ -352,23 +352,24 @@ AC_SUBST(ZLIB_LIB)
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CUDD_INCLUDE=""
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CUDD_LIBS=""
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if test "$CUDD_ARG"; then
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AC_MSG_CHECKING(for Cudd header file)
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AC_MSG_RESULT($CUDD_ARG)
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AC_MSG_CHECKING(for CUDD header file)
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CUDD_INCLUDE_DIR="$CUDD_ARG/include"
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CUDD_HEADER="$CUDD_INCLUDE_DIR/cudd.h"
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if test -r "$CUDD_HEADER"; then
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AC_MSG_RESULT($CUDD_HEADER)
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CUDD_INCLUDE=$CUDD_INCLUDE_DIR
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AC_DEFINE(CUDD, 1, "Cudd bdd package")
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AC_DEFINE(CUDD, 1, "CUDD bdd package")
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else
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AC_MSG_RESULT(not found)
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fi
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AC_MSG_CHECKING(for Cudd library)
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AC_MSG_CHECKING(for CUDD library)
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CUDD_LIB_EXT="a"
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CUDD_LIB="$CUDD_ARG/cudd/libcudd.$CUDD_LIB_EXT"
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CUDD_LIB="$CUDD_ARG/lib/libcudd.$CUDD_LIB_EXT"
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if test -r $CUDD_LIB; then
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AC_MSG_RESULT($CUDD_LIB)
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CUDD_LIBS="$CUDD_ARG/cudd/libcudd.$CUDD_LIB_EXT $CUDD_ARG/mtr/libmtr.$CUDD_LIB_EXT $CUDD_ARG/st/libst.$CUDD_LIB_EXT $CUDD_ARG/util/libutil.$CUDD_LIB_EXT $CUDD_ARG/epd/libepd.$CUDD_LIB_EXT"
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CUDD_LIBS="$CUDD_ARG/lib/libcudd.$CUDD_LIB_EXT"
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else
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AC_MSG_RESULT(not found)
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fi
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@ -405,7 +405,7 @@ close $in_stream
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# Disable emacs syntax highlighting.
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puts $out_stream "// Local Variables:"
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puts $out_stream "// font-lock-auto-fontify: nil"
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puts $out_stream "// mode:c++"
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puts $out_stream "// End:"
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close $out_stream
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@ -895,6 +895,8 @@ LibertyCell::~LibertyCell()
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delete test_cell_;
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ocv_derate_map_.deleteContents();
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pg_port_map_.deleteContents();
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}
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// Multiple timing arc sets (buses bits or a related_ports list)
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@ -944,6 +946,18 @@ LibertyCell::setHasInternalPorts(bool has_internal)
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has_internal_ports_ = has_internal;
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}
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void
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LibertyCell::addPgPort(LibertyPgPort *pg_port)
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{
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pg_port_map_[pg_port->name()] = pg_port;
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}
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LibertyPgPort *
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LibertyCell::findPgPort(const char *name)
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{
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return pg_port_map_.findKey(name);
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}
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ModeDef *
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LibertyCell::makeModeDef(const char *name)
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{
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@ -1752,6 +1766,7 @@ LibertyPort::LibertyPort(LibertyCell *cell,
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min_period_(0.0),
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pulse_clk_trigger_(NULL),
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pulse_clk_sense_(NULL),
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related_ground_pin_(NULL),
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related_power_pin_(NULL),
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min_pulse_width_exists_(false),
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min_period_exists_(false),
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@ -1775,6 +1790,7 @@ LibertyPort::~LibertyPort()
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if (tristate_enable_)
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tristate_enable_->deleteSubexprs();
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delete scaled_ports_;
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stringDelete(related_ground_pin_);
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stringDelete(related_power_pin_);
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}
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@ -2134,6 +2150,12 @@ LibertyPort::setCornerPort(LibertyPort *corner_port,
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corner_ports_[ap_index] = corner_port;
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}
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void
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LibertyPort::setRelatedGroundPin(const char *related_ground_pin)
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{
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related_ground_pin_ = stringCopy(related_ground_pin);
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}
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void
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LibertyPort::setRelatedPowerPin(const char *related_power_pin)
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{
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@ -2690,4 +2712,31 @@ OcvDerate::setDerateTable(const TransRiseFall *tr,
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derate_[tr->index()][early_late->index()][path_type] = derate;
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}
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////////////////////////////////////////////////////////////////
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LibertyPgPort::LibertyPgPort(const char *name) :
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name_(stringCopy(name)),
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pg_type_(unknown),
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voltage_name_(NULL)
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{
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}
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LibertyPgPort::~LibertyPgPort()
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{
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stringDelete(name_);
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stringDelete(voltage_name_);
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}
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void
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LibertyPgPort::setPgType(PgType type)
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{
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pg_type_ = type;
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}
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void
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LibertyPgPort::setVoltageName(const char *voltage_name)
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{
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voltage_name_ = stringCopy(voltage_name);
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}
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} // namespace
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@ -43,6 +43,7 @@ class LibertyReader;
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class OcvDerate;
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class TimingArcAttrs;
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class InternalPowerAttrs;
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class LibertyPgPort;
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typedef Set<Library*> LibrarySet;
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typedef Map<const char*, TableTemplate*, CharPtrLess> TableTemplateMap;
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@ -69,6 +70,7 @@ typedef Map<const char *, OcvDerate*, CharPtrLess> OcvDerateMap;
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typedef Vector<TimingArcAttrs*> TimingArcAttrsSeq;
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typedef Vector<InternalPowerAttrs*> InternalPowerAttrsSeq;
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typedef Map<const char *, float, CharPtrLess> SupplyVoltageMap;
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typedef Map<const char *, LibertyPgPort*, CharPtrLess> LibertyPgPortMap;
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typedef enum {
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clock_gate_none,
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@ -388,6 +390,7 @@ public:
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void findLibertyPortsMatching(PatternMatch *pattern,
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LibertyPortSeq *ports) const;
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bool hasInternalPorts() const { return has_internal_ports_; }
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LibertyPgPort *findPgPort(const char *name);
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ScaleFactors *scaleFactors() const { return scale_factors_; }
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void setScaleFactors(ScaleFactors *scale_factors);
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ModeDef *makeModeDef(const char *name);
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@ -475,6 +478,8 @@ public:
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OcvDerate *findOcvDerate(const char *derate_name);
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void addOcvDerate(OcvDerate *derate);
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void addPgPort(LibertyPgPort *pg_port);
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protected:
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virtual void addPort(ConcretePort *port);
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void setHasInternalPorts(bool has_internal);
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@ -534,6 +539,7 @@ protected:
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bool is_disabled_constraint_;
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Vector<LibertyCell*> corner_cells_;
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float leakage_power_;
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LibertyPgPortMap pg_port_map_;
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private:
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DISALLOW_COPY_AND_ASSIGN(LibertyCell);
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@ -699,6 +705,8 @@ public:
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LibertyPort *cornerPort(int ap_index);
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void setCornerPort(LibertyPort *corner_port,
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int ap_index);
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const char *relatedGroundPin() const { return related_ground_pin_; }
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void setRelatedGroundPin(const char *related_ground_pin);
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const char *relatedPowerPin() const { return related_power_pin_; }
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void setRelatedPowerPin(const char *related_power_pin);
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@ -734,6 +742,7 @@ protected:
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float min_pulse_width_[TransRiseFall::index_count];
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TransRiseFall *pulse_clk_trigger_;
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TransRiseFall *pulse_clk_sense_;
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const char *related_ground_pin_;
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const char *related_power_pin_;
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Vector<LibertyPort*> corner_ports_;
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@ -1002,5 +1011,24 @@ private:
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Table *derate_[TransRiseFall::index_count][EarlyLate::index_count][path_type_count];
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};
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// Power/ground port.
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class LibertyPgPort
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{
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public:
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enum PgType { unknown, power, ground };
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LibertyPgPort(const char *name);
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~LibertyPgPort();
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const char *name() { return name_; }
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PgType pgType() const { return pg_type_; }
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void setPgType(PgType type);
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const char *voltageName() const { return voltage_name_; }
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void setVoltageName(const char *voltage_name);
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private:
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const char *name_;
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PgType pg_type_;
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const char *voltage_name_;
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};
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} // namespace
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#endif
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@ -131,6 +131,7 @@ LibertyReader::readLibertyFile(const char *filename,
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mode_def_ = NULL;
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mode_value_ = NULL;
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ocv_derate_ = NULL;
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pg_port_ = NULL;
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have_resistance_unit_ = false;
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TransRiseFallIterator tr_iter;
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@ -404,6 +405,7 @@ LibertyReader::defineVisitors()
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&LibertyReader::endRiseFallPower);
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defineGroupVisitor("rise_power", &LibertyReader::beginRisePower,
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&LibertyReader::endRiseFallPower);
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defineAttrVisitor("related_ground_pin",&LibertyReader::visitRelatedGroundPin);
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defineAttrVisitor("related_power_pin", &LibertyReader::visitRelatedPowerPin);
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defineAttrVisitor("related_pg_pin", &LibertyReader::visitRelatedPgPin);
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@ -438,6 +440,11 @@ LibertyReader::defineVisitors()
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&LibertyReader::endOcvSigmaTransition);
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defineAttrVisitor("sigma_type", &LibertyReader::visitSigmaType);
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defineAttrVisitor("cell_leakage_power", &LibertyReader::visitCellLeakagePower);
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defineGroupVisitor("pg_pin", &LibertyReader::beginPgPin,
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&LibertyReader::endPgPin);
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defineAttrVisitor("pg_type", &LibertyReader::visitPgType);
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defineAttrVisitor("voltage_name", &LibertyReader::visitVoltageName);
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}
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void
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@ -4476,6 +4483,19 @@ LibertyReader::endRiseFallPower(LibertyGroup *)
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endTableModel();
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}
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void
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LibertyReader::visitRelatedGroundPin(LibertyAttr *attr)
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{
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if (ports_) {
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const char *related_ground_pin = getAttrString(attr);
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LibertyPortSeq::Iterator port_iter(ports_);
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while (port_iter.hasNext()) {
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LibertyPort *port = port_iter.next();
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port->setRelatedGroundPin(related_ground_pin);
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}
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}
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}
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void
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LibertyReader::visitRelatedPowerPin(LibertyAttr *attr)
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{
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@ -4704,6 +4724,47 @@ LibertyReader::visitCellLeakagePower(LibertyAttr *attr)
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}
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}
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void
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LibertyReader::beginPgPin(LibertyGroup *group)
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{
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if (cell_) {
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const char *name = group->firstName();
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pg_port_ = new LibertyPgPort(name);
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cell_->addPgPort(pg_port_);
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}
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}
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void
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LibertyReader::endPgPin(LibertyGroup *)
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{
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pg_port_ = NULL;
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}
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void
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LibertyReader::visitPgType(LibertyAttr *attr)
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{
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if (pg_port_) {
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const char *type_name = getAttrString(attr);
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LibertyPgPort::PgType type = LibertyPgPort::PgType::unknown;
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if (stringEqual(type_name, "primary_ground"))
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type = LibertyPgPort::PgType::ground;
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else if (stringEqual(type_name, "primary_power"))
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type = LibertyPgPort::PgType::power;
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else
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libError(attr, "unknown pg_type.\n");
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pg_port_->setPgType(type);
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}
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}
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void
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LibertyReader::visitVoltageName(LibertyAttr *attr)
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{
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if (pg_port_) {
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const char *voltage_name = getAttrString(attr);
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pg_port_->setVoltageName(voltage_name);
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}
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}
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////////////////////////////////////////////////////////////////
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LibertyFunc::LibertyFunc(const char *expr,
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@ -359,6 +359,7 @@ public:
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virtual void beginFallPower(LibertyGroup *group);
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virtual void beginRisePower(LibertyGroup *group);
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virtual void endRiseFallPower(LibertyGroup *group);
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virtual void visitRelatedGroundPin(LibertyAttr *attr);
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virtual void visitRelatedPowerPin(LibertyAttr *attr);
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virtual void visitRelatedPgPin(LibertyAttr *attr);
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virtual void makeInternalPowers(LibertyPort *port,
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@ -389,6 +390,12 @@ public:
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virtual void endOcvSigmaTransition(LibertyGroup *group);
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virtual void visitSigmaType(LibertyAttr *attr);
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// PgPin group.
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virtual void beginPgPin(LibertyGroup *group);
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virtual void endPgPin(LibertyGroup *group);
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virtual void visitPgType(LibertyAttr *attr);
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virtual void visitVoltageName(LibertyAttr *attr);
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// Visitors for derived classes to overload.
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virtual void beginGroup1(LibertyGroup *) {}
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virtual void beginGroup2(LibertyGroup *) {}
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@ -533,6 +540,7 @@ protected:
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EarlyLateAll *derate_type_;
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EarlyLateAll *sigma_type_;
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PathType path_type_;
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LibertyPgPort *pg_port_;
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ScaleFactorType scale_factor_type_;
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TableAxis *axis_[3];
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bool own_axis_[3];
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|
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@ -888,6 +888,7 @@ ConcreteParasitics::clear()
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}
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}
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delete lumped_elmore_maps_;
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lumped_elmore_maps_ = NULL;
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}
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if (pi_elmore_maps_) {
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@ -902,6 +903,7 @@ ConcreteParasitics::clear()
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}
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}
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delete pi_elmore_maps_;
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pi_elmore_maps_ = NULL;
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}
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if (pi_pole_residue_maps_) {
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@ -916,6 +918,7 @@ ConcreteParasitics::clear()
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}
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}
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delete pi_pole_residue_maps_;
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pi_pole_residue_maps_ = NULL;
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}
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if (parasitic_network_maps_) {
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@ -930,6 +933,7 @@ ConcreteParasitics::clear()
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}
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}
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delete parasitic_network_maps_;
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parasitic_network_maps_ = NULL;
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}
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}
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@ -25,8 +25,6 @@
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namespace sta {
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typedef Vector<PathRef> PathRefSeq;
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class PathExpanded
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{
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public:
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|
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@ -112,6 +112,7 @@ typedef UnorderedMap<Tag*, int, TagMatchHash, TagMatchEqual> ArrivalMap;
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typedef Vector<PathVertex> PathVertexSeq;
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typedef Vector<Slack> SlackSeq;
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typedef Delay Crpr;
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typedef Vector<PathRef> PathRefSeq;
|
||||
|
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typedef enum {
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report_path_full,
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|
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|
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@ -119,9 +119,9 @@ DdNode *
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Sim::funcBdd(const FuncExpr *expr,
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||||
const Instance *inst) const
|
||||
{
|
||||
DdNode *left = 0;
|
||||
DdNode *right = 0;
|
||||
DdNode *result = 0;
|
||||
DdNode *left = NULL;
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DdNode *right = NULL;
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||||
DdNode *result = NULL;
|
||||
switch (expr->op()) {
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||||
case FuncExpr::op_port: {
|
||||
LibertyPort *port = expr->port();
|
||||
|
|
|
|||
|
|
@ -4622,9 +4622,20 @@ Sta::crossesHierarchy(Edge *edge) const
|
|||
{
|
||||
Vertex *from = edge->from(graph_);
|
||||
Vertex *to = edge->to(graph_);
|
||||
Instance *from_inst = network_->instance(from->pin());
|
||||
const Pin *from_pin = from->pin();
|
||||
Instance *from_inst = network_->instance(from_pin);
|
||||
Instance *to_inst = network_->instance(to->pin());
|
||||
return network_->parent(from_inst) != network_->parent(to_inst);
|
||||
Instance *from_parent, *to_parent;
|
||||
// Treat input/output port pins as "inside".
|
||||
if (network_->isTopInstance(from_inst))
|
||||
from_parent = from_inst;
|
||||
else
|
||||
from_parent = network_->parent(from_inst);
|
||||
if (network_->isTopInstance(to_inst))
|
||||
to_parent = to_inst;
|
||||
else
|
||||
to_parent = network_->parent(to_inst);
|
||||
return from_parent != to_parent;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
|
|
|||
28
tcl/StaTcl.i
28
tcl/StaTcl.i
|
|
@ -1797,17 +1797,6 @@ using namespace sta;
|
|||
Tcl_SetObjResult(interp, obj);
|
||||
}
|
||||
|
||||
%typemap(in) Path* {
|
||||
void *obj;
|
||||
SWIG_ConvertPtr($input, &obj, $1_descriptor, false);
|
||||
$1 = reinterpret_cast<Path*>(obj);
|
||||
}
|
||||
|
||||
%typemap(out) Path* {
|
||||
Tcl_Obj *obj = SWIG_NewInstanceObj($1, $1_descriptor, false);
|
||||
Tcl_SetObjResult(interp, obj);
|
||||
}
|
||||
|
||||
%typemap(out) PathRefSeq* {
|
||||
Tcl_Obj *obj = SWIG_NewInstanceObj($1, $1_descriptor, false);
|
||||
Tcl_SetObjResult(interp, obj);
|
||||
|
|
@ -1817,7 +1806,8 @@ using namespace sta;
|
|||
PathRefSeq::Iterator path_iter(paths);
|
||||
while (path_iter.hasNext()) {
|
||||
PathRef *path = &path_iter.next();
|
||||
Tcl_Obj *obj = SWIG_NewInstanceObj(path, SWIGTYPE_p_PathRef, false);
|
||||
PathRef *copy = new PathRef(path);
|
||||
Tcl_Obj *obj = SWIG_NewInstanceObj(copy, SWIGTYPE_p_PathRef, false);
|
||||
Tcl_ListObjAppendElement(interp, list, obj);
|
||||
}
|
||||
delete paths;
|
||||
|
|
@ -4509,7 +4499,7 @@ remove_constraints()
|
|||
}
|
||||
|
||||
void
|
||||
report_path_cmd(Path *path)
|
||||
report_path_cmd(PathRef *path)
|
||||
{
|
||||
Sta::sta()->reportPath(path);
|
||||
}
|
||||
|
|
@ -6311,10 +6301,9 @@ points()
|
|||
Sta *sta = Sta::sta();
|
||||
PathExpanded expanded(self->path(), sta);
|
||||
PathRefSeq *paths = new PathRefSeq;
|
||||
for (int i = expanded.startIndex(); i < expanded.size(); i++) {
|
||||
for (auto i = expanded.startIndex(); i < expanded.size(); i++) {
|
||||
PathRef *path = expanded.path(i);
|
||||
PathRef *copy = new PathRef(path);
|
||||
paths->push_back(copy);
|
||||
paths->push_back(*path);
|
||||
}
|
||||
return paths;
|
||||
}
|
||||
|
|
@ -6371,6 +6360,13 @@ pins()
|
|||
return pins;
|
||||
}
|
||||
|
||||
const char *
|
||||
tag()
|
||||
{
|
||||
Sta *sta = Sta::sta();
|
||||
return self->tag(sta)->asString(sta);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
%extend VertexPathIterator {
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@ proc proc_redirect { proc_name body } {
|
|||
"set redirect \[parse_redirect_args args\];" \
|
||||
"set code \[catch {" $body "} ret \];" \
|
||||
"if {\$redirect} { redirect_file_end };" \
|
||||
"if {\$code != 0} {return -code error -errorcode \$errorCode -errorinfo \$errorInfo} else {return \$ret} }" ]
|
||||
"if {\$code == 1} {return -code \$code -errorcode \$errorCode -errorinfo \$errorInfo \$ret} else {return \$ret} }" ]
|
||||
eval $proc_body
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue