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OpenSTA
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This commit is contained in:
James Cherry 2019-06-04 08:12:22 -07:00
parent 7e0cdcc895
commit 61b1ac4d12
10 changed files with 93 additions and 21 deletions
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6
CMakeLists.txt
View File

@ -430,7 +430,7 @@ set(STA_SWIG_FILES
# Zlib
include(FindZLIB)
# translate cmake bool to ifdef bool
# Translate cmake bool to StaConfig.h ifdef bool
if (ZLIB_FOUND)
set(ZLIB 1)
else()
@ -686,7 +686,7 @@ target_compile_options(OpenSTAnoCmds PUBLIC ${STA_COMPILE_OPTIONS})
# Library
###########################################################
add_library(OpenSTA ${STA_CMD_SOURCE})
add_library(OpenSTA ${STA_SOURCE} ${STA_CMD_SOURCE})
target_include_directories(OpenSTA PUBLIC ${STA_INCLUDE_DIRS})
@ -694,8 +694,6 @@ target_compile_features(OpenSTA
PUBLIC cxx_auto_type
)
target_link_libraries(OpenSTA OpenSTAnoCmds)
target_compile_options(OpenSTA PUBLIC ${STA_COMPILE_OPTIONS})
###########################################################

2
dcalc/LumpedCapDelayCalc.cc
View File

@ -263,7 +263,7 @@ LumpedCapDelayCalc::checkDelay(const LibertyCell *cell,
float from_slew1 = delayAsFloat(from_slew);
float to_slew1 = delayAsFloat(to_slew);
model->checkDelay(cell, pvt, from_slew1, to_slew1, related_out_cap,
false, margin);
pocv_enabled_, margin);
}
else
margin = delay_zero;

6
liberty/Liberty.cc
View File

@ -885,11 +885,13 @@ LibertyCell::~LibertyCell()
timing_arc_set_to_map_.deleteContents();
if (equiv_cells_) {
// Carefull because loop below nulls equiv_cells_.
auto equiv_cells = equiv_cells_;
// equiv_cells_ is shared by all of the equivalent cells, so
// delete it once for all of them and null them.
// delete it once for all of them and null the others.
for (auto equiv : *equiv_cells_)
equiv->setEquivCells(nullptr);
delete equiv_cells_;
delete equiv_cells;
}
deleteInternalPowerAttrs();

53
liberty/LibertyReader.cc
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@ -438,6 +438,12 @@ LibertyReader::defineVisitors()
defineGroupVisitor("ocv_sigma_fall_transition",
&LibertyReader::beginOcvSigmaFallTransition,
&LibertyReader::endOcvSigmaTransition);
defineGroupVisitor("ocv_sigma_rise_constraint",
&LibertyReader::beginOcvSigmaRiseConstraint,
&LibertyReader::endOcvSigmaConstraint);
defineGroupVisitor("ocv_sigma_fall_constraint",
&LibertyReader::beginOcvSigmaFallConstraint,
&LibertyReader::endOcvSigmaConstraint);
defineAttrVisitor("sigma_type", &LibertyReader::visitSigmaType);
defineAttrVisitor("cell_leakage_power", &LibertyReader::visitCellLeakagePower);
@ -2234,7 +2240,8 @@ TimingGroup::makeTableModels(LibertyReader *visitor)
}
}
if (constraint)
models_[tr_index] = new CheckTableModel(constraint);
models_[tr_index] = new CheckTableModel(constraint,
constraint_sigma_[tr_index]);
}
}
@ -4730,6 +4737,39 @@ LibertyReader::endOcvSigmaTransition(LibertyGroup *group)
endTableModel();
}
void
LibertyReader::beginOcvSigmaRiseConstraint(LibertyGroup *group)
{
beginTimingTableModel(group, TransRiseFall::rise(), ScaleFactorType::unknown);
}
void
LibertyReader::beginOcvSigmaFallConstraint(LibertyGroup *group)
{
beginTimingTableModel(group, TransRiseFall::fall(), ScaleFactorType::unknown);
}
void
LibertyReader::endOcvSigmaConstraint(LibertyGroup *group)
{
if (table_) {
if (CheckTableModel::checkAxes(table_)) {
TableModel *table_model = new TableModel(table_, scale_factor_type_, tr_);
if (sigma_type_ == EarlyLateAll::all()) {
timing_->setConstraintSigma(tr_, EarlyLate::min(), table_model);
timing_->setConstraintSigma(tr_, EarlyLate::max(), table_model);
}
else
timing_->setConstraintSigma(tr_, sigma_type_->asMinMax(), table_model);
}
else {
libWarn(group, "unsupported model axis.\n");
delete table_;
}
}
endTableModel();
}
void
LibertyReader::visitSigmaType(LibertyAttr *attr)
{
@ -4983,6 +5023,7 @@ TimingGroup::TimingGroup(int line) :
int el_index = early_late->index();
delay_sigma_[tr_index][el_index] = nullptr;
slew_sigma_[tr_index][el_index] = nullptr;
constraint_sigma_[tr_index][el_index] = nullptr;
}
}
}
@ -5096,7 +5137,15 @@ TimingGroup::setSlewSigma(TransRiseFall *tr,
slew_sigma_[tr->index()][early_late->index()] = model;
}
////////////////////////////////////////////////////////////////
void
TimingGroup::setConstraintSigma(TransRiseFall *tr,
EarlyLate *early_late,
TableModel *model)
{
constraint_sigma_[tr->index()][early_late->index()] = model;
}
////////////////////////////////////////////////////////////////
InternalPowerGroup::InternalPowerGroup(int line) :
InternalPowerAttrs(),

7
liberty/LibertyReaderPvt.hh
View File

@ -395,6 +395,9 @@ public:
virtual void beginOcvSigmaRiseTransition(LibertyGroup *group);
virtual void beginOcvSigmaFallTransition(LibertyGroup *group);
virtual void endOcvSigmaTransition(LibertyGroup *group);
virtual void beginOcvSigmaRiseConstraint(LibertyGroup *group);
virtual void beginOcvSigmaFallConstraint(LibertyGroup *group);
virtual void endOcvSigmaConstraint(LibertyGroup *group);
virtual void visitSigmaType(LibertyAttr *attr);
// PgPin group.
@ -730,6 +733,9 @@ public:
void setSlewSigma(TransRiseFall *tr,
EarlyLate *early_late,
TableModel *model);
void setConstraintSigma(TransRiseFall *tr,
EarlyLate *early_late,
TableModel *model);
protected:
void makeLinearModels(LibertyLibrary *library);
@ -742,6 +748,7 @@ protected:
bool resistance_exists_[TransRiseFall::index_count];
TableModel *cell_[TransRiseFall::index_count];
TableModel *constraint_[TransRiseFall::index_count];
TableModel *constraint_sigma_[TransRiseFall::index_count][EarlyLate::index_count];
TableModel *transition_[TransRiseFall::index_count];
TableModel *delay_sigma_[TransRiseFall::index_count][EarlyLate::index_count];
TableModel *slew_sigma_[TransRiseFall::index_count][EarlyLate::index_count];

16
liberty/TableModel.cc
View File

@ -24,6 +24,8 @@
namespace sta {
static void
deleteSigmaModels(TableModel *models[EarlyLate::index_count]);
static void
reportPvt(const LibertyLibrary *library,
const Pvt *pvt,
@ -57,8 +59,8 @@ GateTableModel::~GateTableModel()
deleteSigmaModels(delay_sigma_models_);
}
void
GateTableModel::deleteSigmaModels(TableModel *models[EarlyLate::index_count])
static void
deleteSigmaModels(TableModel *models[EarlyLate::index_count])
{
TableModel *early_model = models[EarlyLate::earlyIndex()];
TableModel *late_model = models[EarlyLate::lateIndex()];
@ -342,14 +344,22 @@ GateTableModel::checkAxis(TableAxis *axis)
////////////////////////////////////////////////////////////////
CheckTableModel::CheckTableModel(TableModel *model) :
CheckTableModel::CheckTableModel(TableModel *model,
TableModel *sigma_models[EarlyLate::index_count]) :
model_(model)
{
MinMaxIterator el_iter;
while (el_iter.hasNext()) {
EarlyLate *early_late = el_iter.next();
int el_index = early_late->index();
sigma_models_[el_index] = sigma_models[el_index];
}
}
CheckTableModel::~CheckTableModel()
{
delete model_;
deleteSigmaModels(sigma_models_);
}
void

4
liberty/TableModel.hh
View File

@ -112,7 +112,6 @@ protected:
float &axis_value1,
float &axis_value2,
float &axis_value3) const;
void deleteSigmaModels(TableModel *models[EarlyLate::index_count]);
static bool checkAxis(TableAxis *axis);
TableModel *delay_model_;
@ -127,7 +126,8 @@ private:
class CheckTableModel : public CheckTimingModel
{
public:
explicit CheckTableModel(TableModel *model);
explicit CheckTableModel(TableModel *model,
TableModel *sigma_models[EarlyLate::index_count]);
virtual ~CheckTableModel();
virtual void checkDelay(const LibertyCell *cell,
const Pvt *pvt,

2
parasitics/Parasitics.hh
View File

@ -149,7 +149,7 @@ public:
virtual Parasitic *findParasiticNetwork(const Pin *pin,
const ParasiticAnalysisPt *ap) const = 0;
virtual Parasitic *makeParasiticNetwork(const Net *net,
bool pin_cap_included,
bool includes_pin_caps,
const ParasiticAnalysisPt *ap) = 0;
virtual ParasiticDeviceIterator *deviceIterator(Parasitic *parasitic) = 0;
virtual ParasiticNodeIterator *nodeIterator(Parasitic *parasitic) = 0;

12
parasitics/ReduceParasitics.cc
View File

@ -38,7 +38,7 @@ public:
ReduceToPi(StaState *sta);
void reduceToPi(const Pin *drvr_pin,
ParasiticNode *drvr_node,
bool pin_cap_included,
bool includes_pin_caps,
float coupling_cap_factor,
const TransRiseFall *tr,
const OperatingConditions *op_cond,
@ -69,7 +69,7 @@ protected:
bool isLoopResistor(ParasiticDevice *device);
void markLoopResistor(ParasiticDevice *device);
bool pin_cap_included_;
bool includes_pin_caps_;
float coupling_cap_multiplier_;
const TransRiseFall *tr_;
const OperatingConditions *op_cond_;
@ -99,7 +99,7 @@ ReduceToPi::ReduceToPi(StaState *sta) :
void
ReduceToPi::reduceToPi(const Pin *drvr_pin,
ParasiticNode *drvr_node,
bool pin_cap_included,
bool includes_pin_caps,
float coupling_cap_factor,
const TransRiseFall *tr,
const OperatingConditions *op_cond,
@ -110,7 +110,7 @@ ReduceToPi::reduceToPi(const Pin *drvr_pin,
float &rpi,
float &c1)
{
pin_cap_included_ = pin_cap_included;
includes_pin_caps_ = includes_pin_caps;
coupling_cap_multiplier_ = coupling_cap_factor;
tr_ = tr;
op_cond_ = op_cond;
@ -211,8 +211,8 @@ ReduceToPi::pinCapacitance(ParasiticNode *node)
Port *port = network_->port(pin);
LibertyPort *lib_port = network_->libertyPort(port);
if (lib_port) {
if (!pin_cap_included_) {
pin_cap = sdc_->pinCapacitance(pin,tr_, op_cond_, corner_,
if (!includes_pin_caps_) {
pin_cap = sdc_->pinCapacitance(pin, tr_, op_cond_, corner_,
cnst_min_max_);
pin_caps_one_value_ &= lib_port->capacitanceIsOneValue();
}

6
tcl/StaTcl.i
View File

@ -2960,6 +2960,12 @@ set_wire_load_mode_cmd(const char *mode_name)
Sta::sta()->setWireloadMode(mode);
}
Wireload *
wireload_defaulted(MinMax *min_max)
{
return Sta::sta()->sdc()->wireloadDefaulted(min_max);
}
void
set_net_resistance(Net *net,
const MinMaxAll *min_max,