James Cherry
|
2bc6e8f68c
|
update copyright
Signed-off-by: James Cherry <cherry@parallaxsw.com>
|
2022-01-04 10:17:08 -07:00 |
|
James Cherry
|
85f437bc59
|
verilog black box ports unknown/loads
Signed-off-by: James Cherry <cherry@parallaxsw.com>
|
2021-09-17 08:35:45 -07:00 |
|
James Cherry
|
8c23d8ef83
|
read_verilog/link_design support redirection
|
2021-07-09 11:25:05 -07:00 |
|
James Cherry
|
b9116bd56d
|
read_verilog no warn on pg_pin connections
|
2021-07-07 16:57:34 -07:00 |
|
James Cherry
|
2e8f0035dc
|
update copyright
|
2021-06-25 10:25:49 -07:00 |
|
James Cherry
|
6359bd6fc5
|
leaks
|
2021-02-07 17:22:59 +00:00 |
|
James Cherry
|
54dbbf625e
|
mv debug_on into Debug
|
2021-01-04 20:47:37 -08:00 |
|
James Cherry
|
9b1dc880f5
|
rm Debug::print
|
2020-12-29 10:33:22 -08:00 |
|
James Cherry
|
ee86a30338
|
error/warn
|
2020-12-25 14:00:11 -08:00 |
|
James Cherry
|
78d29c8f90
|
error/warn IDs
|
2020-12-13 18:21:35 -07:00 |
|
James Cherry
|
a862935b38
|
verilog port input tri -> input
|
2020-05-04 17:13:48 -07:00 |
|
James Cherry
|
ec856896c7
|
verilog read/write to public includes
|
2020-04-05 16:56:38 -07:00 |
|
James Cherry
|
ee326f165c
|
public headers in include/sta
|
2020-04-05 14:53:44 -07:00 |
|
James Cherry
|
804953e317
|
mv public headers to include/sta
|
2020-04-05 11:35:51 -07:00 |
|
James Cherry
|
4a017e86eb
|
update copyright
|
2020-03-06 18:50:37 -08:00 |
|
James Cherry
|
7fdeb0d3b7
|
use range iter
|
2020-02-01 18:13:41 -07:00 |
|
James Cherry
|
26c76cd075
|
verilog reader make instances with liberty cell
|
2020-02-01 10:55:27 -07:00 |
|
James Cherry
|
74e287a7eb
|
write_verilog escaped bus port name "input [7:0] \in[0] ;"
|
2019-07-03 21:18:38 -07:00 |
|
James Cherry
|
eb9fdd1be0
|
write verilog match liberty bus bit order
|
2019-07-02 07:07:34 -07:00 |
|
James Cherry
|
344394de29
|
link_design use verilog library to lookup top
|
2019-06-26 16:01:58 -07:00 |
|
James Cherry
|
1a84830895
|
sta::worst_slack args, sta to verilog name args
|
2019-06-18 15:52:12 -07:00 |
|
James Cherry
|
49b2c3cea7
|
rm redundant StaState args
|
2019-06-17 08:32:28 -07:00 |
|
James Cherry
|
96fcf1d8b2
|
ConcreteCell/Port pointers to corresponding liberty
|
2019-06-15 22:20:54 -07:00 |
|
James Cherry
|
a988588dac
|
sync
|
2019-05-19 17:06:06 -06:00 |
|
James Cherry
|
2d519b4740
|
ucsd 20190410 seg fault accessing/setting power_default_signal_toggle_rate
|
2019-04-10 20:36:48 -07:00 |
|
James Cherry
|
e5c9bc43fd
|
2.0.10
|
2019-03-12 17:25:53 -07:00 |
|
James Cherry
|
92f4968feb
|
write_path_spice bug fixes
|
2019-01-20 09:44:24 -08:00 |
|
James Cherry
|
316742202f
|
sync
|
2019-01-16 15:37:31 -08:00 |
|
James Cherry
|
b075ccc783
|
update copyright
|
2019-01-01 12:26:11 -08:00 |
|
James Cherry
|
f49dc75d32
|
sync
|
2018-12-05 14:18:41 -08:00 |
|
James Cherry
|
2af22d9331
|
2018/10/23 read_verilog mod inst with no ports seg fault
|
2018-10-23 16:24:22 -07:00 |
|
James Cherry
|
1154fb89fd
|
and then there was light...
|
2018-09-28 08:54:21 -07:00 |