- Add diff_files_sorted to test/helpers.tcl for hash-order-independent
SDC comparison (fixes non-deterministic write_sdc output ordering)
- Use diff_files_sorted in sdc_derate_disable_deep and
sdc_port_delay_advanced tests
- Remove stale coverage percentages from test comments (Comment 1)
- Remove unnecessary catch blocks in search property tests (Comment 3)
- Strengthen load-only tests with actual data verification (Comment 8)
- Remove orphan .ok files for deleted monolithic tests (Comment 9)
- Add golden .sdcok/.libok/.vok/.sdfok files for SDC/liberty/verilog
write-and-diff tests
- Add -B (clean rebuild) option to make_coverage_report.sh
- Replace (void) casts and EXPECT_TRUE(true) with real assertions in
TestSdc.cc and TestVerilog.cc
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Add meaningful verification to liberty ECSM, sky130 corners, writer,
and roundtrip tests. Expand verilog specify, escaped-write, remove-cells,
write, and writer tests with content checks, roundtrip validation, and
error guards. Update corresponding .ok golden files.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Negate conditions in empty if-body assertions so the FAIL message
is printed directly (e.g. `if { $x != 0 } { } else { puts FAIL }`
becomes `if { $x == 0 } { puts FAIL }`). Remove dead if/else blocks
where both branches were empty, strip meaningless status-only puts
from Tcl tests and their .ok golden files, and wrap a long line in
search_report_gated_datacheck.tcl to stay within 80 columns.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Strengthen C++ test assertions in TestSdc and TestSearch with actual
value checks. Stabilize verilog_multimodule_write by using clear_sta
for isolated roundtrips. Add report_checks to wireload model tests.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Replace empty-body checks and trivial file-existence assertions with
actual content verification and state validation in C++ unit tests.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Remove useless empty-body if-blocks that check file size/existence without
doing anything, replacing them with meaningful puts output where appropriate.
Split monolithic verilog test files into individual per-test files with
their own .ok golden files. Update .ok files to match actual output.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Remove dead code blocks that reference non-exposed Tcl commands (e.g.,
sta::find_pi_pole_residue) and delete all write_gate_spice catch blocks
from spice tests since write_gate_spice_cmd SWIG binding is missing,
making all write_gate_spice calls always fail. Added bug report for the
missing binding. All 6531 tests pass.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Remove bare catch blocks that silently swallowed errors instead of
properly testing them. Fix underlying issues revealed by catch removal
including wrong API calls ([$role name] on strings, invalid properties
like cell_leakage_power/is_register, nonexistent Tcl bindings) and
incorrect library names. Update golden .ok files to match new output.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Document why each catch block is needed across 48 test files,
covering liberty, search, sdc, spice, network, parasitics, util,
and verilog modules.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Remove unnecessary catch blocks in network, parasitics, sdc, spice,
and util test modules. Add report_checks after set_wire_load_model
in parasitics_wireload.tcl to verify timing changes per wireload.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Remove unnecessary catch blocks across all test modules (graph,
liberty, network, parasitics, power, sdc, sdf, search, spice,
verilog), expand C++ tests (TestSearchIncremental 8→36 tests,
TestPower 71→96, TestSpice 98→126), add report_checks after each
set_wire_load_model in liberty_wireload.tcl, and rewrite
liberty_sky130_corners.tcl with actual multi-corner timing analysis.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Remove unnecessary catch blocks from Tcl test files across all modules,
add report_checks after each set_wire_load_model in liberty_wireload,
rewrite liberty_sky130_corners for actual multi-corner timing analysis
with define_corners, and expand C++ tests (TestSearchIncremental 8→36,
TestPower 71→96, TestSpice 98→126 tests).
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
- Remove stale line-number coverage comments (# Targets: line NNN, hit=0)
- Remove useless file-existence checks from verilog/sdf tests
- Delete 21 orphaned dcalc Tcl tests (C++ tests already cover them)
- Rename liberty_ccsn_ecsm -> liberty_ccsn (no ECSM libs available)
- Fix liberty_sky130_corners to use define_corners/-corner for real multi-corner testing
- Add report_checks per wireload model in liberty_wireload
- Fix test/regression to work from test/ directory (label mismatch)
- Refactor all module CMakeLists.txt with sta_module_tests() macro
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Jaehyun Kim
Matt Liberty
James Cherry
Akash Levy
Mike Inouye
nataliakokoromyti