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test: Fix wrong API calls in Tcl tests and remove unnecessary catches 

Replace wrong/non-existent command calls with correct OpenSTA APIs:
- sta::pin_slack → get_property $pin slack_max_rise
- sta::slow_drivers_cmd → sta::slow_drivers
- set_latch_borrow_limit → set_max_time_borrow
- remove_data_check → unset_data_check
- remove_clock → delete_clock
- reset_path → unset_path_exceptions
- sta::report_path_end 3-arg → sta::report_path_end2
- sta::design_power "NULL" → sta::design_power [sta::cmd_corner]
- report_path $path → sta::report_path_cmd $path
- connect_pin 3-arg → connect_pin net inst/port
- set_power_activity positional → -input_ports flag
- sta::is_clock [get_ports] → sta::is_clock [sta::get_port_pin]
- get_property $inst lib_name → liberty_cell/liberty_library
- get_property $pin net_name → [$pin net] + get_full_name
- get_property $net is_power → $net is_power method
- Removed unnecessary catch around sta::write_liberty

23 catch blocks removed. Tests now execute real API calls instead
of silently failing.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This commit is contained in:
Jaehyun Kim 2026-02-20 15:32:08 +09:00
parent 812d26f14c
commit ce45133c84
33 changed files with 594 additions and 203 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
liberty/test/liberty_clkgate_lvlshift.tcl
View File

@ -219,9 +219,7 @@ foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2
# Write liberty for sky130 (exercises writer for pg_pin, level_shifter)
############################################################
set outfile [make_result_file liberty_clkgate_lvlshift_write.lib]
catch {
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile
}
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile
############################################################
# Read IHP library for more voltage_map / pg_pin coverage

4
liberty/test/liberty_seq_scan_bus.tcl
View File

@ -246,6 +246,4 @@ report_power
# Write liberty roundtrip
############################################################
set outfile [make_result_file liberty_seq_scan_bus_write.lib]
catch {
sta::write_liberty NangateOpenCellLibrary $outfile
}
sta::write_liberty NangateOpenCellLibrary $outfile

26
network/test/network_properties.ok
View File

@ -10,20 +10,20 @@ Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 1480
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
--- cell property queries ---
total cells: 5
(u1: Error: instance objects do not have a lib_name property.)
(u2: Error: instance objects do not have a lib_name property.)
(r1: Error: instance objects do not have a lib_name property.)
(r2: Error: instance objects do not have a lib_name property.)
(r3: Error: instance objects do not have a lib_name property.)
u1: ref=BUFx2_ASAP7_75t_R lib=asap7sc7p5t_INVBUF_RVT_FF_nldm_211120 full=u1
u2: ref=AND2x2_ASAP7_75t_R lib=asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120 full=u2
r1: ref=DFFHQx4_ASAP7_75t_R lib=asap7sc7p5t_SEQ_RVT_FF_nldm_220123 full=r1
r2: ref=DFFHQx4_ASAP7_75t_R lib=asap7sc7p5t_SEQ_RVT_FF_nldm_220123 full=r2
r3: ref=DFFHQx4_ASAP7_75t_R lib=asap7sc7p5t_SEQ_RVT_FF_nldm_220123 full=r3
--- pin direction / connectivity ---
(u1/A: Error: pin objects do not have a net_name property.)
(u1/Y: Error: pin objects do not have a net_name property.)
(u2/A: Error: pin objects do not have a net_name property.)
(u2/B: Error: pin objects do not have a net_name property.)
(u2/Y: Error: pin objects do not have a net_name property.)
(r1/CLK: Error: pin objects do not have a net_name property.)
(r1/D: Error: pin objects do not have a net_name property.)
(r1/Q: Error: pin objects do not have a net_name property.)
u1/A: dir=input net=r2q
u1/Y: dir=output net=u1z
u2/A: dir=input net=r1q
u2/B: dir=input net=u1z
u2/Y: dir=output net=u2z
r1/CLK: dir=input net=clk1
r1/D: dir=input net=in1
r1/Q: dir=output net=r1q
--- net queries ---
total nets: 10
net r1q: r1q

33
network/test/network_properties.tcl
View File

@ -24,16 +24,16 @@ set all_cells [get_cells *]
puts "total cells: [llength $all_cells]"
foreach cell_name {u1 u2 r1 r2 r3} {
catch {
set inst [get_cells $cell_name]
set ref [get_property $inst ref_name]
set lib [get_property $inst lib_name]
set full [get_full_name $inst]
puts "$cell_name: ref=$ref lib=$lib full=$full"
} msg
if {$msg ne ""} {
puts " ($cell_name: $msg)"
set inst [get_cells $cell_name]
set ref [get_property $inst ref_name]
set lib_cell [get_property $inst liberty_cell]
if { $lib_cell != "NULL" && $lib_cell ne "" } {
set lib [get_name [$lib_cell liberty_library]]
} else {
set lib ""
}
set full [get_full_name $inst]
puts "$cell_name: ref=$ref lib=$lib full=$full"
}
#---------------------------------------------------------------
@ -41,16 +41,15 @@ foreach cell_name {u1 u2 r1 r2 r3} {
#---------------------------------------------------------------
puts "--- pin direction / connectivity ---"
foreach pin_path {u1/A u1/Y u2/A u2/B u2/Y r1/CLK r1/D r1/Q} {
catch {
set pin [get_pins $pin_path]
set dir [get_property $pin direction]
set pin [get_pins $pin_path]
set dir [get_property $pin direction]
set net [$pin net]
if { $net != "NULL" && $net ne "" } {
set net_name [get_full_name $net]
} else {
set net_name ""
set net_name [get_property $pin net_name]
puts "$pin_path: dir=$dir net=$net_name"
} msg
if {$msg ne ""} {
puts " ($pin_path: $msg)"
}
puts "$pin_path: dir=$dir net=$net_name"
}
#---------------------------------------------------------------

83
sdc/test/sdc_clock_operations.ok
View File

@ -1017,13 +1017,92 @@ Path Type: max
--- write_sdc ---
--- write_sdc compatible ---
--- remove_clock ---
--- delete_clock ---
Startpoint: reg2/Q (clock source 'gclk_edge')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gclk_edge (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.10 10.10 clock network delay (propagated)
-0.20 9.90 clock uncertainty
0.00 9.90 clock reconvergence pessimism
-3.00 6.90 output external delay
6.90 data required time
---------------------------------------------------------
6.90 data required time
-5.00 data arrival time
---------------------------------------------------------
1.90 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_alt)
Path Group: clk1_alt
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk2 (rise edge)
0.40 5.40 clock network delay (ideal)
2.00 7.40 v input external delay
0.00 7.40 v in3 (in)
0.05 7.45 v or1/ZN (OR2_X1)
0.03 7.47 ^ nor1/ZN (NOR2_X1)
0.00 7.47 ^ reg2/D (DFF_X1)
7.47 data arrival time
10.00 10.00 clock clk1_alt (rise edge)
0.00 10.00 clock network delay (propagated)
-0.25 9.75 clock uncertainty
0.00 9.75 clock reconvergence pessimism
9.75 ^ reg2/CK (DFF_X1)
-0.03 9.72 library setup time
9.72 data required time
---------------------------------------------------------
9.72 data required time
-7.47 data arrival time
---------------------------------------------------------
2.24 slack (MET)
Startpoint: reg3/Q (clock source 'gclk_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
1.67 1.67 clock gclk_mul3 (rise edge)
0.00 1.67 clock network delay
1.67 ^ out2 (out)
1.67 data arrival time
5.00 5.00 clock clk2 (rise edge)
0.20 5.20 clock network delay (ideal)
-0.15 5.05 clock uncertainty
0.00 5.05 clock reconvergence pessimism
-3.00 2.05 output external delay
2.05 data required time
---------------------------------------------------------
2.05 data required time
-1.67 data arrival time
---------------------------------------------------------
0.38 slack (MET)
--- report_clock_properties ---
Clock Period Waveform
----------------------------------------------------
clk1 10.00 0.00 5.00
clk2 20.00 5.00 15.00
vclk1 8.00 0.00 3.00
clk1_alt 5.00 0.00 2.50
gclk_div2 10.00 0.00 5.00 (generated)
gclk_mul3 6.67 1.67 5.00 (generated)

8
sdc/test/sdc_clock_operations.tcl
View File

@ -150,11 +150,9 @@ write_sdc -no_timestamp -compatible $sdc2
############################################################
# Remove clock and re-create
############################################################
puts "--- remove_clock ---"
catch {
remove_clock vclk1
report_checks
}
puts "--- delete_clock ---"
delete_clock [get_clocks vclk1]
report_checks
############################################################
# Clock properties reporting

36
sdc/test/sdc_disable_case.ok
View File

@ -212,34 +212,30 @@ Path Type: max
Warning: sdc_disable_case.tcl line 1, object 'sdc_test2' not found.
Warning: sdc_disable_case.tcl line 1, object 'sdc_test2' not found.
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered data to data check clocked by clk1)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
2.00 2.00 v input external delay
0.00 2.00 v in3 (in)
0.05 2.05 v or1/ZN (OR2_X1)
0.03 2.07 ^ nor1/ZN (NOR2_X1)
0.00 2.07 ^ reg2/D (DFF_X1)
2.07 data arrival time
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (propagated)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 ^ reg1/Q (DFF_X1)
-0.60 -0.52 data check setup time
-0.52 data required time
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
-0.52 data required time
-2.07 data arrival time
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
-2.59 slack (VIOLATED)
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)

8
sdc/test/sdc_disable_case.tcl
View File

@ -141,13 +141,9 @@ set sdc_file5 [make_result_file sdc_datacheck1.sdc]
write_sdc -no_timestamp $sdc_file5
# Remove data checks
catch {
remove_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup
}
unset_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup
catch {
remove_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold
}
unset_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold
############################################################
# Clock gating check (exercises clockGatingMargin paths)

30
sdc/test/sdc_leaf_pin_filter_removal.ok
View File

@ -1,6 +1,36 @@
--- net properties ---
net clk1: is_power=0 is_ground=0
net clk2: is_power=0 is_ground=0
net in1: is_power=0 is_ground=0
net in2: is_power=0 is_ground=0
net in3: is_power=0 is_ground=0
net n1: is_power=0 is_ground=0
net n2: is_power=0 is_ground=0
net n3: is_power=0 is_ground=0
net n4: is_power=0 is_ground=0
net n5: is_power=0 is_ground=0
net n6: is_power=0 is_ground=0
net n7: is_power=0 is_ground=0
net out1: is_power=0 is_ground=0
net out2: is_power=0 is_ground=0
--- port properties ---
port clk1: direction=input is_clock=1
port clk2: direction=input is_clock=1
port in1: direction=input is_clock=0
port in2: direction=input is_clock=0
port in3: direction=input is_clock=0
port out1: direction=output is_clock=0
port out2: direction=output is_clock=0
--- instance properties ---
inst and1: ref=AND2_X1 lib=NangateOpenCellLibrary
inst buf1: ref=BUF_X1 lib=NangateOpenCellLibrary
inst inv1: ref=INV_X1 lib=NangateOpenCellLibrary
inst nand1: ref=NAND2_X1 lib=NangateOpenCellLibrary
inst nor1: ref=NOR2_X1 lib=NangateOpenCellLibrary
inst or1: ref=OR2_X1 lib=NangateOpenCellLibrary
inst reg1: ref=DFF_X1 lib=NangateOpenCellLibrary
inst reg2: ref=DFF_X1 lib=NangateOpenCellLibrary
inst reg3: ref=DFF_X1 lib=NangateOpenCellLibrary
--- pin properties ---
pin buf1/A: direction=input is_clock=0
pin buf1/Z: direction=output is_clock=0

28
sdc/test/sdc_leaf_pin_filter_removal.tcl
View File

@ -30,11 +30,9 @@ puts "--- net properties ---"
set nets [get_nets *]
foreach n $nets {
set name [get_full_name $n]
catch {
set is_pwr [get_property $n is_power]
set is_gnd [get_property $n is_ground]
puts " net $name: is_power=$is_pwr is_ground=$is_gnd"
}
set is_pwr [$n is_power]
set is_gnd [$n is_ground]
puts " net $name: is_power=$is_pwr is_ground=$is_gnd"
}
############################################################
@ -44,11 +42,10 @@ puts "--- port properties ---"
set ports [get_ports *]
foreach p $ports {
set name [get_full_name $p]
catch {
set dir [get_property $p direction]
set is_clk [get_property $p is_clock]
puts " port $name: direction=$dir is_clock=$is_clk"
}
set dir [get_property $p direction]
set pin [sta::get_port_pin $p]
set is_clk [sta::is_clock $pin]
puts " port $name: direction=$dir is_clock=$is_clk"
}
############################################################
@ -58,11 +55,14 @@ puts "--- instance properties ---"
set insts [get_cells *]
foreach i $insts {
set name [get_full_name $i]
catch {
set ref [get_property $i ref_name]
set lib_name [get_property $i liberty_cell_name]
puts " inst $name: ref=$ref lib=$lib_name"
set ref [get_property $i ref_name]
set lib_cell [get_property $i liberty_cell]
if { $lib_cell != "NULL" && $lib_cell ne "" } {
set lib_name [get_name [$lib_cell liberty_library]]
} else {
set lib_name ""
}
puts " inst $name: ref=$ref lib=$lib_name"
}
############################################################

14
search/test/search_fanin_fanout_deep.ok
View File

@ -153,6 +153,8 @@ Fanout 2 inst levels of and2/ZN: 5
(clk ^) r 1.12:8.83 f 1.13:8.80
(clk ^) r 2.10:7.90 f 2.10:7.90
--- Pin slack various ---
and1/ZN max rise slack: 8.831884
inv2/ZN min fall slack: 1.130790
=== PATH QUERY ===
--- find_timing_paths and path details ---
Found 10 paths
@ -171,25 +173,25 @@ Found 10 paths
endpoint: out2
slack: 7.918512068272321e-9
arrival: 8.148756669434931e-11
required: 0.0
required: 7.999999773744548e-9
path_pins: 4
start_pin: reg2/Q
endpoint: out3
slack: 7.918512068272321e-9
arrival: 8.148756669434931e-11
required: 0.0
required: 7.999999773744548e-9
path_pins: 4
start_pin: reg3/Q
endpoint: out2
slack: 7.924581879592552e-9
arrival: 7.541753332951373e-11
required: 0.0
required: 7.999999773744548e-9
path_pins: 4
start_pin: reg2/Q
endpoint: out3
slack: 7.924581879592552e-9
arrival: 7.541753332951373e-11
required: 0.0
required: 7.999999773744548e-9
path_pins: 4
start_pin: reg3/Q
endpoint: reg1/D
@ -201,13 +203,13 @@ Found 10 paths
endpoint: reg2/D
slack: 8.803825224390494e-9
arrival: 1.1573944025400351e-9
required: 0.0
required: 9.961219404885924e-9
path_pins: 16
start_pin: in4
endpoint: reg3/D
slack: 8.803825224390494e-9
arrival: 1.1573944025400351e-9
required: 0.0
required: 9.961219404885924e-9
path_pins: 16
start_pin: in4
endpoint: reg1/D

12
search/test/search_fanin_fanout_deep.tcl
View File

@ -102,14 +102,10 @@ report_slack [get_pins reg1/D]
report_slack [get_ports out1]
puts "--- Pin slack various ---"
catch {
set ps1 [sta::pin_slack [get_pins and1/ZN] max rise]
puts "and1/ZN max rise slack: $ps1"
}
catch {
set ps2 [sta::pin_slack [get_pins inv2/ZN] min fall]
puts "inv2/ZN min fall slack: $ps2"
}
set ps1 [get_property [get_pins and1/ZN] slack_max_rise]
puts "and1/ZN max rise slack: $ps1"
set ps2 [get_property [get_pins inv2/ZN] slack_min_fall]
puts "inv2/ZN min fall slack: $ps2"
puts "=== PATH QUERY ==="

8
search/test/search_json_unconstrained.ok
View File

@ -1194,6 +1194,14 @@ clk 7.90
}
--- reportPathFull on a single path ---
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 ^ reg1/Q (DFF_X1)
0.02 0.10 ^ buf2/Z (BUF_X1)
0.00 0.10 ^ out1 (out)
--- json report with full_clock format (for source clock paths) ---
{"checks": [
{

2
search/test/search_json_unconstrained.tcl
View File

@ -58,7 +58,7 @@ puts "--- reportPathFull on a single path ---"
set paths_f [find_timing_paths -path_delay max]
foreach pe $paths_f {
set p [$pe path]
catch { report_path $p }
sta::report_path_cmd $p
break
}

110
search/test/search_latch_timing.ok
View File

@ -548,7 +548,115 @@ Fanout Cap Slew Delay Time Description
0.05 slack (MET)
--- set_latch_borrow_limit ---
--- set_max_time_borrow ---
Startpoint: latch1 (positive level-sensitive latch clocked by clk)
Endpoint: latch2 (positive level-sensitive latch clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.05 1.05 time given to startpoint
0.00 1.05 v latch1/D (DLH_X1)
0.06 1.11 v latch1/Q (DLH_X1)
0.00 1.11 v latch2/D (DLH_X1)
1.11 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ latch2/G (DLH_X1)
1.11 1.11 time borrowed from endpoint
1.11 data required time
---------------------------------------------------------
1.11 data required time
-1.11 data arrival time
---------------------------------------------------------
0.00 slack (MET)
Time Borrowing Information
--------------------------------------------
clk pulse width 5.00
library setup time -0.05
--------------------------------------------
max time borrow 4.95
actual time borrow 1.11
--------------------------------------------
Startpoint: latch1 (positive level-sensitive latch clocked by clk)
Endpoint: latch2 (positive level-sensitive latch clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.05 1.05 time given to startpoint
0.00 1.05 v latch1/D (DLH_X1)
0.06 1.11 v latch1/Q (DLH_X1)
0.00 1.11 v latch2/D (DLH_X1)
1.11 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ latch2/G (DLH_X1)
1.11 1.11 time borrowed from endpoint
1.11 data required time
---------------------------------------------------------
1.11 data required time
-1.11 data arrival time
---------------------------------------------------------
0.00 slack (MET)
Time Borrowing Information
--------------------------------------------
clk pulse width 5.00
library setup time -0.05
--------------------------------------------
max time borrow 4.95
actual time borrow 1.11
--------------------------------------------
Startpoint: latch1 (positive level-sensitive latch clocked by clk)
Endpoint: latch2 (positive level-sensitive latch clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.05 1.05 time given to startpoint
0.00 1.05 v latch1/D (DLH_X1)
0.06 1.11 v latch1/Q (DLH_X1)
0.00 1.11 v latch2/D (DLH_X1)
1.11 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ latch2/G (DLH_X1)
1.11 1.11 time borrowed from endpoint
1.11 data required time
---------------------------------------------------------
1.11 data required time
-1.11 data arrival time
---------------------------------------------------------
0.00 slack (MET)
Time Borrowing Information
--------------------------------------------
user max time borrow 4.00
actual time borrow 1.11
--------------------------------------------
--- report_clock_properties ---
Clock Period Waveform
----------------------------------------------------

20
search/test/search_latch_timing.tcl
View File

@ -70,21 +70,15 @@ puts "--- Latch path reports with fields ---"
report_checks -path_delay max -fields {capacitance slew fanout input_pin net}
report_checks -path_delay min -fields {capacitance slew fanout input_pin net}
puts "--- set_latch_borrow_limit ---"
catch {
set_latch_borrow_limit 2.0 [get_pins latch1/G]
report_checks -path_delay max -format full_clock_expanded
}
puts "--- set_max_time_borrow ---"
set_max_time_borrow 2.0 [get_pins latch1/G]
report_checks -path_delay max -format full_clock_expanded
catch {
set_latch_borrow_limit 3.0 [get_cells latch1]
report_checks -path_delay max -format full_clock_expanded
}
set_max_time_borrow 3.0 [get_cells latch1]
report_checks -path_delay max -format full_clock_expanded
catch {
set_latch_borrow_limit 4.0 [get_clocks clk]
report_checks -path_delay max -format full_clock_expanded
}
set_max_time_borrow 4.0 [get_clocks clk]
report_checks -path_delay max -format full_clock_expanded
puts "--- report_clock_properties ---"
report_clock_properties

6
search/test/search_path_delay_output.tcl
View File

@ -97,7 +97,7 @@ foreach pe $paths_pd_min {
# Remove path delay constraints
############################################################
puts "--- Remove path delay ---"
catch { reset_path -from [get_ports in1] -to [get_ports out1] }
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
report_checks -path_delay max
############################################################
@ -108,7 +108,7 @@ set_false_path -from [get_ports in1] -to [get_ports out1]
report_checks -path_delay max
report_checks -path_delay max -unconstrained
catch { reset_path -from [get_ports in1] -to [get_ports out1] }
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
report_checks -path_delay max
############################################################
@ -121,7 +121,7 @@ report_checks -path_delay max -format full_clock_expanded
set_multicycle_path 1 -hold -from [get_ports in1] -to [get_ports out1]
report_checks -path_delay min -format full_clock_expanded
catch { reset_path -from [get_ports in1] -to [get_ports out1] }
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
############################################################
# Propagated clock with output delay

11
search/test/search_power_activity.ok
View File

@ -32,6 +32,17 @@ Total 1.669393e-06 3.195729e-07 4.083089e-07 2.397274e-06 100.0%
69.6% 13.3% 17.0%
--- Pin activity ---
--- set_power_activity on pins ---
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 2.28e-06 2.07e-07 1.58e-07 2.65e-06 48.1%
Combinational 1.64e-06 3.38e-07 2.39e-07 2.22e-06 40.3%
Clock 3.96e-07 2.30e-07 1.12e-08 6.37e-07 11.6%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 4.32e-06 7.74e-07 4.08e-07 5.50e-06 100.0%
78.5% 14.1% 7.4%
--- set_power_activity on global ---
Group Internal Switching Leakage Total
Power Power Power Power (Watts)

10
search/test/search_power_activity.tcl
View File

@ -41,12 +41,10 @@ catch {
}
puts "--- set_power_activity on pins ---"
catch {
set_power_activity -activity 0.5 -duty 0.5 [get_ports in1]
set_power_activity -activity 0.3 -duty 0.4 [get_ports in2]
set_power_activity -activity 0.8 -duty 0.6 [get_ports in3]
report_power
}
set_power_activity -input_ports [get_ports in1] -activity 0.5 -duty 0.5
set_power_activity -input_ports [get_ports in2] -activity 0.3 -duty 0.4
set_power_activity -input_ports [get_ports in3] -activity 0.8 -duty 0.6
report_power
puts "--- set_power_activity on global ---"
set_power_activity -global -activity 0.2 -duty 0.5

49
search/test/search_register_deep.ok
View File

@ -153,7 +153,7 @@ Path Type: max
-6.54 slack (VIOLATED)
--- remove_data_check ---
--- unset_data_check ---
--- set_clock_gating_check ---
Startpoint: rst (input port clocked by clk)
Endpoint: reg1 (recovery check against rising-edge clock clk)
@ -209,34 +209,31 @@ Path Type: max
8.50 slack (MET)
Startpoint: in2 (input port clocked by clk)
Endpoint: reg1 (falling edge-triggered data to data check clocked by clk)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFFR_X1)
0.10 0.10 ^ reg1/Q (DFFR_X1)
0.02 0.12 ^ buf2/Z (BUF_X1)
0.00 0.12 ^ out1 (out)
0.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
1.00 11.00 v input external delay
0.00 11.00 v in2 (in)
0.02 11.02 v and1/ZN (AND2_X1)
0.02 11.05 v buf1/Z (BUF_X1)
0.01 11.06 ^ inv1/ZN (INV_X1)
0.00 11.06 ^ reg1/D (DFFR_X1)
11.06 data arrival time
5.00 5.00 clock clk (fall edge)
0.02 5.02 clock network delay (propagated)
0.00 5.02 clock reconvergence pessimism
5.02 v reg1/CK (DFFR_X1)
-0.50 4.52 data check setup time
4.52 data required time
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
4.52 data required time
-11.06 data arrival time
8.00 data required time
-0.12 data arrival time
---------------------------------------------------------
-6.54 slack (VIOLATED)
7.88 slack (MET)
--- write_sdc ---
@ -264,14 +261,14 @@ paths rise_through: 1
paths fall_through: 1
--- check_setup individual flags ---
--- report_tns ---
tns max -6.54
tns max 0.00
tns min -4.00
tns max -6.536289
tns max 0.000000
--- report_wns ---
wns max -6.54
wns max 0.00
wns min -4.00
wns max -6.536289
wns max 0.000000
--- report_worst_slack ---
worst slack max -6.54
worst slack max 7.88
worst slack min -4.00
worst slack max -6.536289
worst slack max 7.881455

6
search/test/search_register_deep.tcl
View File

@ -153,10 +153,8 @@ puts "--- set_data_check ---"
set_data_check -from [get_pins reg1/CK] -to [get_pins reg1/D] -setup 0.5
report_checks -path_delay max
puts "--- remove_data_check ---"
catch {
remove_data_check -from [get_pins reg1/CK] -to [get_pins reg1/D] -setup
}
puts "--- unset_data_check ---"
unset_data_check -from [get_pins reg1/CK] -to [get_pins reg1/D] -setup
############################################################
# set_clock_gating_check

1
search/test/search_register_latch_sim.ok
View File

@ -330,6 +330,7 @@ VSS X
A 0
Z 0
--- slow_drivers ---
slow drivers: 5
--- latch timing ---
No paths found.
Startpoint: latch1 (positive level-sensitive latch clocked by clk)

6
search/test/search_register_latch_sim.tcl
View File

@ -168,10 +168,8 @@ report_constant [get_cells buf1]
# Slow driver analysis
############################################################
puts "--- slow_drivers ---"
catch {
set slow [sta::slow_drivers_cmd 5]
puts "slow drivers: [llength $slow]"
}
set slow [sta::slow_drivers 5]
puts "slow drivers: [llength $slow]"
############################################################
# Latch timing paths

59
search/test/search_report_path_latch_expanded.ok
View File

@ -1138,7 +1138,44 @@ Group Slack
--------------------------------------------
clk 0.05
--- set_latch_borrow_limit and report ---
--- set_max_time_borrow and report ---
Startpoint: latch1 (positive level-sensitive latch clocked by clk)
Endpoint: latch2 (positive level-sensitive latch clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.05 1.05 time given to startpoint
0.00 0.00 1.05 v latch1/D (DLH_X1)
2 1.93 0.01 0.06 1.11 v latch1/Q (DLH_X1)
0.01 0.00 1.11 v latch2/D (DLH_X1)
1.11 data arrival time
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ latch2/G (DLH_X1)
1.11 1.11 time borrowed from endpoint
1.11 data required time
-----------------------------------------------------------------------------
1.11 data required time
-1.11 data arrival time
-----------------------------------------------------------------------------
0.00 slack (MET)
Time Borrowing Information
--------------------------------------------
clk pulse width 5.00
library setup time -0.05
--------------------------------------------
max time borrow 4.95
actual time borrow 1.11
--------------------------------------------
--- Latch min_max ---
Startpoint: latch1 (positive level-sensitive latch clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
@ -1317,10 +1354,7 @@ Path Type: max
Time Borrowing Information
--------------------------------------------
clk pulse width 5.00
library setup time -0.05
--------------------------------------------
max time borrow 4.95
user max time borrow 2.50
actual time borrow 1.05
--------------------------------------------
@ -1355,10 +1389,7 @@ Path Type: max
Time Borrowing Information
--------------------------------------------
clk pulse width 5.00
library setup time -0.05
--------------------------------------------
max time borrow 4.95
user max time borrow 2.50
actual time borrow 1.05
--------------------------------------------
@ -1393,10 +1424,7 @@ Path Type: max
Time Borrowing Information
--------------------------------------------
clk pulse width 5.00
library setup time -0.02
--------------------------------------------
max time borrow 4.98
user max time borrow 2.50
actual time borrow 1.04
--------------------------------------------
@ -1431,10 +1459,7 @@ Path Type: max
Time Borrowing Information
--------------------------------------------
clk pulse width 5.00
library setup time -0.02
--------------------------------------------
max time borrow 4.98
user max time borrow 2.50
actual time borrow 1.04
--------------------------------------------

8
search/test/search_report_path_latch_expanded.tcl
View File

@ -99,11 +99,9 @@ report_checks -path_delay min -format slack_only
############################################################
# set_latch_borrow_limit and report with fields
############################################################
puts "--- set_latch_borrow_limit and report ---"
catch {
set_latch_borrow_limit 2.5 [get_pins latch1/G]
report_checks -path_delay max -format full_clock_expanded -fields {capacitance slew fanout input_pin}
}
puts "--- set_max_time_borrow and report ---"
set_max_time_borrow 2.5 [get_pins latch1/G]
report_checks -path_delay max -format full_clock_expanded -fields {capacitance slew fanout input_pin}
############################################################
# report_checks min_max for latch

4
search/test/search_sim_logic_clk_network.ok
View File

@ -1,5 +1,9 @@
--- isClock queries ---
clk port is_clock: 1
in1 port is_clock: 0
--- ideal/propagated clock queries ---
clk isIdealClock: 1
after propagate - clk isIdealClock: 1
--- sim logic values ---
en=X clk_gate_a1=X gated=X buf1=X reg1/D=X
--- case analysis 0 on en ---

23
search/test/search_sim_logic_clk_network.tcl
View File

@ -29,28 +29,19 @@ report_checks -path_delay max > /dev/null
# isClock queries
############################################################
puts "--- isClock queries ---"
catch {
set clk_pin_is_clk [sta::is_clock [get_ports clk]]
puts "clk port is_clock: $clk_pin_is_clk"
}
catch {
set in1_is_clk [sta::is_clock [get_ports in1]]
puts "in1 port is_clock: $in1_is_clk"
}
set clk_pin_is_clk [sta::is_clock [sta::get_port_pin [get_ports clk]]]
puts "clk port is_clock: $clk_pin_is_clk"
set in1_is_clk [sta::is_clock [sta::get_port_pin [get_ports in1]]]
puts "in1 port is_clock: $in1_is_clk"
############################################################
# isIdealClock / isPropagatedClock
############################################################
puts "--- ideal/propagated clock queries ---"
catch {
puts "clk isIdealClock: [sta::is_ideal_clock [get_ports clk]]"
puts "clk isPropagatedClock: [sta::is_propagated_clock [get_ports clk]]"
}
set clk_pin [sta::get_port_pin [get_ports clk]]
puts "clk isIdealClock: [sta::is_ideal_clock $clk_pin]"
set_propagated_clock [get_clocks clk]
catch {
puts "after propagate - clk isIdealClock: [sta::is_ideal_clock [get_ports clk]]"
puts "after propagate - clk isPropagatedClock: [sta::is_propagated_clock [get_ports clk]]"
}
puts "after propagate - clk isIdealClock: [sta::is_ideal_clock $clk_pin]"
unset_propagated_clock [get_clocks clk]
############################################################

56
search/test/search_sta_extra.ok
View File

@ -440,6 +440,62 @@ worst_arrival_path pin: out1
--- vertex_worst_slack_path ---
worst_slack_path pin: out1
--- report_path_end with prev_end ---
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 v reg1/Q (DFF_X1)
0.02 0.10 v buf2/Z (BUF_X1)
0.00 0.10 v out1 (out)
0.10 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.10 data arrival time
---------------------------------------------------------
7.90 slack (MET)
Startpoint: in2 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v in2 (in)
0.02 1.02 v and1/ZN (AND2_X1)
0.02 1.05 v buf1/Z (BUF_X1)
0.00 1.05 v reg1/D (DFF_X1)
1.05 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.04 9.96 library setup time
9.96 data required time
---------------------------------------------------------
9.96 data required time
-1.05 data arrival time
---------------------------------------------------------
8.91 slack (MET)
--- make_instance ---
make_instance: done
--- pocv_enabled ---

2
search/test/search_sta_extra.tcl
View File

@ -151,7 +151,7 @@ set paths3 [find_timing_paths -path_delay max -endpoint_path_count 3]
set prev_end ""
foreach pe $paths3 {
if { $prev_end != "" } {
catch { sta::report_path_end $pe $prev_end 0 }
sta::report_path_end2 $pe $prev_end 0
}
set prev_end $pe
}

115
search/test/search_worst_slack_sta.ok
View File

@ -466,6 +466,120 @@ Path Type: max
--- report_path_end with prev_end ---
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 v reg1/Q (DFF_X1)
0.02 0.10 v buf2/Z (BUF_X1)
0.00 0.10 v out1 (out)
0.10 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.10 data arrival time
---------------------------------------------------------
7.90 slack (MET)
Startpoint: in2 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v in2 (in)
0.02 1.02 v and1/ZN (AND2_X1)
0.02 1.05 v buf1/Z (BUF_X1)
0.00 1.05 v reg1/D (DFF_X1)
1.05 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.04 9.96 library setup time
9.96 data required time
---------------------------------------------------------
9.96 data required time
-1.05 data arrival time
---------------------------------------------------------
8.91 slack (MET)
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v in1 (in)
0.02 1.02 v and1/ZN (AND2_X1)
0.02 1.05 v buf1/Z (BUF_X1)
0.00 1.05 v reg1/D (DFF_X1)
1.05 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.04 9.96 library setup time
9.96 data required time
---------------------------------------------------------
9.96 data required time
-1.05 data arrival time
---------------------------------------------------------
8.92 slack (MET)
Startpoint: in2 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ in2 (in)
0.03 1.03 ^ and1/ZN (AND2_X1)
0.02 1.05 ^ buf1/Z (BUF_X1)
0.00 1.05 ^ reg1/D (DFF_X1)
1.05 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.05 data arrival time
---------------------------------------------------------
8.92 slack (MET)
--- path group names ---
path groups: clk asynchronous {path delay} {gated clock} unconstrained
--- report_checks with -corner ---
@ -526,6 +640,7 @@ Path Type: min
--- design_power ---
design_power: 6.081859851292393e-7 1.8692128733732716e-8 1.4891682553752617e-7 7.757948878861498e-7 5.41103304385615e-7 5.8966871385734976e-9 7.881983066226894e-8 6.258198368414014e-7 6.708269495447894e-8 1.2795442039248428e-8 7.009699487525722e-8 1.499751363098767e-7 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
--- set_report_path_field_properties ---
Warning: unknown report path field delay
Warning: unknown report path field delay

8
search/test/search_worst_slack_sta.tcl
View File

@ -122,7 +122,7 @@ set paths [find_timing_paths -path_delay max -endpoint_path_count 5]
set prev_end ""
foreach pe $paths {
if { $prev_end != "" } {
catch { sta::report_path_end $pe $prev_end 0 }
sta::report_path_end2 $pe $prev_end 0
}
set prev_end $pe
}
@ -137,10 +137,8 @@ report_checks -path_delay max -corner [$corner name]
report_checks -path_delay min -corner [$corner name]
puts "--- design_power ---"
catch {
set pwr [sta::design_power "NULL" "NULL"]
puts "design_power: $pwr"
}
set pwr [sta::design_power [sta::cmd_corner]]
puts "design_power: $pwr"
puts "--- set_report_path_field_properties ---"
sta::set_report_path_field_properties "delay" "Dly" 10 0

1
search/test/search_write_sdf_model.ok
View File

@ -10,6 +10,7 @@ make_instance new_buf1 done
--- Network edit: make_net ---
make_net new_net1 done
--- Network edit: connect_pin ---
connect_pin done
--- Network edit: disconnect_pin ---
Warning: search_write_sdf_model.tcl line 1, net 'new_buf1' not found.
disconnect_pin done

6
search/test/search_write_sdf_model.tcl
View File

@ -52,10 +52,8 @@ make_net new_net1
puts "make_net new_net1 done"
puts "--- Network edit: connect_pin ---"
catch {
connect_pin new_buf1 A [get_nets n1]
puts "connect_pin done"
}
connect_pin n1 new_buf1/A
puts "connect_pin done"
puts "--- Network edit: disconnect_pin ---"
disconnect_pin new_buf1 A