test: Apply review feedback - part4

Remove unnecessary catch blocks in network, parasitics, sdc, spice,
and util test modules. Add report_checks after set_wire_load_model
in parasitics_wireload.tcl to verify timing changes per wireload.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This commit is contained in:
Jaehyun Kim 2026-02-20 14:13:55 +09:00
parent 5c9b4d7a15
commit 812d26f14c
14 changed files with 248 additions and 403 deletions

View File

@ -257,8 +257,8 @@ foreach nname $chain_nets {
disconnect_pin $nname $iname/Z
}
}
foreach iname $chain_insts {catch {delete_instance $iname}}
foreach nname $chain_nets {catch {delete_net $nname}}
foreach iname $chain_insts {delete_instance $iname}
foreach nname $chain_nets {delete_net $nname}
# Final timing check
report_checks

View File

@ -179,8 +179,8 @@ foreach nname $chain_nets {
disconnect_pin $nname $iname/ZN
}
}
foreach iname $chain_insts {catch {delete_instance $iname}}
foreach nname $chain_nets {catch {delete_net $nname}}
foreach iname $chain_insts {delete_instance $iname}
foreach nname $chain_nets {delete_net $nname}
############################################################
# Final timing check

View File

@ -61,13 +61,8 @@ set all_nets [get_nets *]
puts "total nets: [llength $all_nets]"
foreach net_name {r1q r2q u1z u2z in1 in2 out clk1 clk2 clk3} {
catch {
set net [get_nets $net_name]
puts "net $net_name: [get_full_name $net]"
} msg
if {$msg ne ""} {
puts " (net $net_name: $msg)"
}
set net [get_nets $net_name]
puts "net $net_name: [get_full_name $net]"
}
#---------------------------------------------------------------

View File

@ -39,8 +39,8 @@ Path Type: max
--- pi model very small ---
set_pi_model u1/Y tiny: invalid command name "set_pi_model"
set_elmore u1/Y->u2/A tiny: invalid command name "set_elmore"
set_pi_model u1/Y tiny: done
set_elmore u1/Y->u2/A tiny: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
@ -71,12 +71,12 @@ Path Type: max
--- pi model medium ---
set_pi_model u2/Y medium: invalid command name "set_pi_model"
set_elmore u2/Y->r3/D: invalid command name "set_elmore"
set_pi_model r1/Q large: invalid command name "set_pi_model"
set_elmore r1/Q->u1/A: invalid command name "set_elmore"
set_pi_model r2/Q: invalid command name "set_pi_model"
set_elmore r2/Q->u2/B: invalid command name "set_elmore"
set_pi_model u2/Y medium: done
set_elmore u2/Y->r3/D: done
set_pi_model r1/Q large: done
set_elmore r1/Q->u1/A: done
set_pi_model r2/Q: done
set_elmore r2/Q->u2/B: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
@ -253,23 +253,23 @@ Path Type: max
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (propagated)
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
75.04 data arrival time
47.84 47.84 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
10.64 58.48 ^ u1/Y (BUFx2_ASAP7_75t_R)
13.12 71.60 ^ u2/Y (AND2x2_ASAP7_75t_R)
0.01 71.61 ^ r3/D (DFFHQx4_ASAP7_75t_R)
71.61 data arrival time
500.00 500.00 clock clk (rise edge)
0.00 500.00 clock network delay (propagated)
0.00 500.00 clock reconvergence pessimism
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-5.78 494.22 library setup time
494.22 data required time
-5.56 494.44 library setup time
494.44 data required time
---------------------------------------------------------
494.22 data required time
-75.04 data arrival time
494.44 data required time
-71.61 data arrival time
---------------------------------------------------------
419.17 slack (MET)
422.83 slack (MET)
--- dmp_ceff_two_pole with pi models ---
@ -496,8 +496,8 @@ Slew = 4.92
lumped dcalc u1: done
--- override pi model ---
re-set u1/Y: invalid command name "set_pi_model"
re-set u2/Y: invalid command name "set_pi_model"
re-set u1/Y: done
re-set u2/Y: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
@ -585,8 +585,8 @@ Unannotated Arcs
internal net u2/Y -> r3/D
annotated -report_unannotated: done
--- SPEF override ---
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Startpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out (output port clocked by clk)
Path Group: clk
Path Type: max
@ -594,24 +594,21 @@ Path Type: max
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.30 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
61.03 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
201.72 data arrival time
0.00 12.11 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
63.46 75.57 ^ r3/Q (DFFHQx4_ASAP7_75t_R)
13.15 88.72 ^ out (out)
88.72 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.46 503.46 library setup time
503.46 data required time
0.00 500.00 clock network delay (ideal)
0.00 500.00 clock reconvergence pessimism
-1.00 499.00 output external delay
499.00 data required time
---------------------------------------------------------
503.46 data required time
-201.72 data arrival time
499.00 data required time
-88.72 data arrival time
---------------------------------------------------------
301.74 slack (MET)
410.28 slack (MET)
Found 0 unannotated drivers.
@ -619,8 +616,8 @@ Found 0 partially unannotated drivers.
--- report_net ---
Net r1q
Pin capacitance: 0.3994-0.5226
Wire capacitance: 13.4000-13.4000
Total capacitance: 13.7994-13.9226
Wire capacitance: 0.0000
Total capacitance: 0.3994-0.5226
Number of drivers: 1
Number of loads: 1
Number of pins: 2
@ -634,8 +631,8 @@ Load pins
report_net r1q: done
Net r2q
Pin capacitance: 0.4414-0.5770
Wire capacitance: 13.4000-13.4000
Total capacitance: 13.8414-13.9770
Wire capacitance: 0.0000
Total capacitance: 0.4414-0.5770
Number of drivers: 1
Number of loads: 1
Number of pins: 2
@ -649,8 +646,8 @@ Load pins
report_net r2q: done
Net u1z
Pin capacitance: 0.3171-0.5657
Wire capacitance: 13.4000-13.4000
Total capacitance: 13.7171-13.9657
Wire capacitance: 0.0000
Total capacitance: 0.3171-0.5657
Number of drivers: 1
Number of loads: 1
Number of pins: 2
@ -664,8 +661,8 @@ Load pins
report_net u1z: done
Net u2z
Pin capacitance: 0.5479-0.6212
Wire capacitance: 13.4000-13.4000
Total capacitance: 13.9479-14.0212
Wire capacitance: 0.0000
Total capacitance: 0.5479-0.6212
Number of drivers: 1
Number of loads: 1
Number of pins: 2

View File

@ -28,11 +28,11 @@ report_checks
# Set pi model with very small values
#---------------------------------------------------------------
puts "--- pi model very small ---"
catch {set_pi_model u1/Y 0.00001 0.01 0.000005} msg
puts "set_pi_model u1/Y tiny: $msg"
sta::set_pi_model u1/Y 0.00001 0.01 0.000005
puts "set_pi_model u1/Y tiny: done"
catch {set_elmore u1/Y u2/A 0.00001} msg
puts "set_elmore u1/Y->u2/A tiny: $msg"
sta::set_elmore u1/Y u2/A 0.00001
puts "set_elmore u1/Y->u2/A tiny: done"
report_checks
@ -40,23 +40,23 @@ report_checks
# Set pi model with medium values on multiple nets
#---------------------------------------------------------------
puts "--- pi model medium ---"
catch {set_pi_model u2/Y 0.01 20.0 0.005} msg
puts "set_pi_model u2/Y medium: $msg"
sta::set_pi_model u2/Y 0.01 20.0 0.005
puts "set_pi_model u2/Y medium: done"
catch {set_elmore u2/Y r3/D 0.01} msg
puts "set_elmore u2/Y->r3/D: $msg"
sta::set_elmore u2/Y r3/D 0.01
puts "set_elmore u2/Y->r3/D: done"
catch {set_pi_model r1/Q 0.05 50.0 0.02} msg
puts "set_pi_model r1/Q large: $msg"
sta::set_pi_model r1/Q 0.05 50.0 0.02
puts "set_pi_model r1/Q large: done"
catch {set_elmore r1/Q u1/A 0.05} msg
puts "set_elmore r1/Q->u1/A: $msg"
sta::set_elmore r1/Q u1/A 0.05
puts "set_elmore r1/Q->u1/A: done"
catch {set_pi_model r2/Q 0.03 30.0 0.01} msg
puts "set_pi_model r2/Q: $msg"
sta::set_pi_model r2/Q 0.03 30.0 0.01
puts "set_pi_model r2/Q: done"
catch {set_elmore r2/Q u2/B 0.02} msg
puts "set_elmore r2/Q->u2/B: $msg"
sta::set_elmore r2/Q u2/B 0.02
puts "set_elmore r2/Q->u2/B: done"
report_checks
@ -99,11 +99,11 @@ puts "lumped dcalc u1: done"
#---------------------------------------------------------------
puts "--- override pi model ---"
set_delay_calculator dmp_ceff_elmore
catch {set_pi_model u1/Y 0.02 25.0 0.01} msg
puts "re-set u1/Y: $msg"
sta::set_pi_model u1/Y 0.02 25.0 0.01
puts "re-set u1/Y: done"
catch {set_pi_model u2/Y 0.005 10.0 0.002} msg
puts "re-set u2/Y: $msg"
sta::set_pi_model u2/Y 0.005 10.0 0.002
puts "re-set u2/Y: done"
report_checks

View File

@ -71,11 +71,9 @@ foreach i $insts {
puts "--- pin properties ---"
foreach p [get_pins buf1/*] {
set name [get_full_name $p]
catch {
set dir [get_property $p direction]
set is_clk [get_property $p is_clock]
puts " pin $name: direction=$dir is_clock=$is_clk"
}
set dir [get_property $p direction]
set is_clk [get_property $p is_clock]
puts " pin $name: direction=$dir is_clock=$is_clk"
}
############################################################
@ -145,10 +143,8 @@ puts "output ports: [llength $out_ports]"
# findLeafLoadPins / findLeafDriverPins via reporting
############################################################
puts "--- report_net_load ---"
catch {
foreach n [get_nets *] {
report_net [get_full_name $n]
}
foreach n [get_nets *] {
report_net [get_full_name $n]
}
############################################################

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@ -131,19 +131,13 @@ if { $rc4 == 0 } {
puts "--- write_path_spice max slack ---"
set spice_dir2 [make_result_file spice_adv_path]
file mkdir $spice_dir2
set rc5 [catch {
write_path_spice \
-path_args {-sort_by_slack -path_delay max} \
-spice_directory $spice_dir2 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
} msg5]
if { $rc5 == 0 } {
} else {
puts "INFO: write_path_spice max slack: $msg5"
}
write_path_spice \
-path_args {-sort_by_slack -path_delay max} \
-spice_directory $spice_dir2 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
#---------------------------------------------------------------
# write_path_spice min path
@ -151,19 +145,13 @@ if { $rc5 == 0 } {
puts "--- write_path_spice min path ---"
set spice_dir3 [make_result_file spice_adv_min]
file mkdir $spice_dir3
set rc6 [catch {
write_path_spice \
-path_args {-path_delay min} \
-spice_directory $spice_dir3 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
} msg6]
if { $rc6 == 0 } {
} else {
puts "INFO: write_path_spice min: $msg6"
}
write_path_spice \
-path_args {-path_delay min} \
-spice_directory $spice_dir3 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
#---------------------------------------------------------------
# write_path_spice with hspice
@ -171,20 +159,14 @@ if { $rc6 == 0 } {
puts "--- write_path_spice hspice ---"
set spice_dir4 [make_result_file spice_adv_hspice]
file mkdir $spice_dir4
set rc7 [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir4 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator hspice
} msg7]
if { $rc7 == 0 } {
} else {
puts "INFO: write_path_spice hspice: $msg7"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir4 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator hspice
#---------------------------------------------------------------
# write_path_spice with xyce
@ -192,17 +174,11 @@ if { $rc7 == 0 } {
puts "--- write_path_spice xyce ---"
set spice_dir5 [make_result_file spice_adv_xyce]
file mkdir $spice_dir5
set rc8 [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir5 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator xyce
} msg8]
if { $rc8 == 0 } {
} else {
puts "INFO: write_path_spice xyce: $msg8"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir5 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator xyce

View File

@ -70,19 +70,13 @@ close $subckt_fh
puts "--- write_path_spice max ngspice ---"
set dir1 [make_result_file spice_gcd_max]
file mkdir $dir1
set rc [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $dir1 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VPWR \
-ground VGND
} msg]
if { $rc == 0 } {
} else {
puts "INFO: write_path_spice max: $msg"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $dir1 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VPWR \
-ground VGND
#---------------------------------------------------------------
# write_path_spice with min path
@ -90,19 +84,13 @@ if { $rc == 0 } {
puts "--- write_path_spice min ---"
set dir2 [make_result_file spice_gcd_min]
file mkdir $dir2
set rc [catch {
write_path_spice \
-path_args {-path_delay min} \
-spice_directory $dir2 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VPWR \
-ground VGND
} msg]
if { $rc == 0 } {
} else {
puts "INFO: write_path_spice min: $msg"
}
write_path_spice \
-path_args {-path_delay min} \
-spice_directory $dir2 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VPWR \
-ground VGND
#---------------------------------------------------------------
# write_path_spice with hspice
@ -111,20 +99,14 @@ if { $rc == 0 } {
puts "--- write_path_spice hspice ---"
set dir3 [make_result_file spice_gcd_hspice]
file mkdir $dir3
set rc [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $dir3 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VPWR \
-ground VGND \
-simulator hspice
} msg]
if { $rc == 0 } {
} else {
puts "INFO: write_path_spice hspice: $msg"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $dir3 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VPWR \
-ground VGND \
-simulator hspice
#---------------------------------------------------------------
# write_path_spice with xyce
@ -133,20 +115,14 @@ if { $rc == 0 } {
puts "--- write_path_spice xyce ---"
set dir4 [make_result_file spice_gcd_xyce]
file mkdir $dir4
set rc [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $dir4 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VPWR \
-ground VGND \
-simulator xyce
} msg]
if { $rc == 0 } {
} else {
puts "INFO: write_path_spice xyce: $msg"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $dir4 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VPWR \
-ground VGND \
-simulator xyce
#---------------------------------------------------------------
# write_path_spice with specific from/to

View File

@ -104,19 +104,13 @@ close $subckt_fh
puts "--- write_path_spice max ---"
set spice_dir1 [make_result_file spice_mp_max]
file mkdir $spice_dir1
set rc1 [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir1 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
} msg1]
if { $rc1 == 0 } {
} else {
puts "INFO: write_path_spice max: $msg1"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir1 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
#---------------------------------------------------------------
# write_path_spice with min path
@ -124,19 +118,13 @@ if { $rc1 == 0 } {
puts "--- write_path_spice min ---"
set spice_dir2 [make_result_file spice_mp_min]
file mkdir $spice_dir2
set rc2 [catch {
write_path_spice \
-path_args {-path_delay min} \
-spice_directory $spice_dir2 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
} msg2]
if { $rc2 == 0 } {
} else {
puts "INFO: write_path_spice min: $msg2"
}
write_path_spice \
-path_args {-path_delay min} \
-spice_directory $spice_dir2 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
#---------------------------------------------------------------
# write_path_spice with specific from/to
@ -164,20 +152,14 @@ if { $rc3 == 0 } {
puts "--- write_path_spice hspice ---"
set spice_dir4 [make_result_file spice_mp_hspice]
file mkdir $spice_dir4
set rc4 [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir4 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator hspice
} msg4]
if { $rc4 == 0 } {
} else {
puts "INFO: write_path_spice hspice: $msg4"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir4 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator hspice
#---------------------------------------------------------------
# write_path_spice with xyce
@ -185,20 +167,14 @@ if { $rc4 == 0 } {
puts "--- write_path_spice xyce ---"
set spice_dir5 [make_result_file spice_mp_xyce]
file mkdir $spice_dir5
set rc5 [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir5 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator xyce
} msg5]
if { $rc5 == 0 } {
} else {
puts "INFO: write_path_spice xyce: $msg5"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir5 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator xyce
#---------------------------------------------------------------
# write_gate_spice with multiple cells and transitions

View File

@ -77,19 +77,13 @@ close $subckt_fh
puts "--- write_path_spice min path ---"
set spice_dir_min [make_result_file spice_min_out]
file mkdir $spice_dir_min
set rc1 [catch {
write_path_spice \
-path_args {-path_delay min} \
-spice_directory $spice_dir_min \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
} msg1]
if { $rc1 == 0 } {
} else {
puts "INFO: write_path_spice min: $msg1"
}
write_path_spice \
-path_args {-path_delay min} \
-spice_directory $spice_dir_min \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
#---------------------------------------------------------------
# write_path_spice - max path
@ -97,19 +91,13 @@ if { $rc1 == 0 } {
puts "--- write_path_spice max path ---"
set spice_dir_max [make_result_file spice_max_out]
file mkdir $spice_dir_max
set rc2 [catch {
write_path_spice \
-path_args {-path_delay max -sort_by_slack} \
-spice_directory $spice_dir_max \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
} msg2]
if { $rc2 == 0 } {
} else {
puts "INFO: write_path_spice max: $msg2"
}
write_path_spice \
-path_args {-path_delay max -sort_by_slack} \
-spice_directory $spice_dir_max \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
#---------------------------------------------------------------
# write_path_spice with hspice simulator
@ -117,20 +105,14 @@ if { $rc2 == 0 } {
puts "--- write_path_spice hspice ---"
set spice_dir_hs [make_result_file spice_hs_out]
file mkdir $spice_dir_hs
set rc3 [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir_hs \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator hspice
} msg3]
if { $rc3 == 0 } {
} else {
puts "INFO: write_path_spice hspice: $msg3"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir_hs \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator hspice
#---------------------------------------------------------------
# write_path_spice with xyce simulator
@ -138,20 +120,14 @@ if { $rc3 == 0 } {
puts "--- write_path_spice xyce ---"
set spice_dir_xy [make_result_file spice_xy_out]
file mkdir $spice_dir_xy
set rc4 [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir_xy \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator xyce
} msg4]
if { $rc4 == 0 } {
} else {
puts "INFO: write_path_spice xyce: $msg4"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir_xy \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator xyce
#---------------------------------------------------------------
# write_path_spice with different -from/-to constraints

View File

@ -106,51 +106,33 @@ if { $rc == 0 } {
puts "--- write_path_spice to out1 ---"
set spice_dir2 [file join $spice_dir path_out1]
file mkdir $spice_dir2
set rc [catch {
write_path_spice \
-path_args {-to out1 -path_delay max} \
-spice_directory $spice_dir2 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
} msg]
if { $rc == 0 } {
} else {
puts "INFO: write_path_spice to out1: $msg"
}
write_path_spice \
-path_args {-to out1 -path_delay max} \
-spice_directory $spice_dir2 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
puts "--- write_path_spice to out2 ---"
set spice_dir3 [file join $spice_dir path_out2]
file mkdir $spice_dir3
set rc [catch {
write_path_spice \
-path_args {-to out2 -path_delay max} \
-spice_directory $spice_dir3 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
} msg]
if { $rc == 0 } {
} else {
puts "INFO: write_path_spice to out2: $msg"
}
write_path_spice \
-path_args {-to out2 -path_delay max} \
-spice_directory $spice_dir3 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
puts "--- write_path_spice with ngspice ---"
set spice_dir4 [file join $spice_dir path_ng]
file mkdir $spice_dir4
set rc [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir4 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator ngspice
} msg]
if { $rc == 0 } {
} else {
puts "INFO: write_path_spice ngspice: $msg"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir4 \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator ngspice

View File

@ -38,20 +38,13 @@ puts $subckt_fh "M2 Q D VSS VSS nmos W=1u L=100n"
puts $subckt_fh ".ends"
close $subckt_fh
# Attempt write_path_spice - exercises the Tcl command parsing and
# C++ WritePathSpice code paths. Catch errors since subckt definitions
# may not perfectly match, but the code path is exercised for coverage.
set rc [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
} msg]
if { $rc == 0 } {
diff_files $test_name.spok [file join $spice_dir path_1.sp]
} else {
puts "FAIL: write_path_spice returned error: $msg"
}
# write_path_spice - exercises the Tcl command parsing and
# C++ WritePathSpice code paths.
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
diff_files $test_name.spok [file join $spice_dir path_1.sp]

View File

@ -43,51 +43,33 @@ puts $subckt_fh ".ends"
close $subckt_fh
puts "--- write_path_spice default ---"
set rc1 [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
} msg1]
if { $rc1 == 0 } {
} else {
puts "INFO: write_path_spice default: $msg1"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS
puts "--- write_path_spice with -simulator hspice ---"
set rc2 [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator hspice
} msg2]
if { $rc2 == 0 } {
} else {
puts "INFO: write_path_spice hspice: $msg2"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator hspice
puts "--- write_path_spice with -simulator xyce ---"
set rc3 [catch {
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator xyce
} msg3]
if { $rc3 == 0 } {
} else {
puts "INFO: write_path_spice xyce: $msg3"
}
write_path_spice \
-path_args {-sort_by_slack} \
-spice_directory $spice_dir \
-lib_subckt_file $subckt_file \
-model_file $model_file \
-power VDD \
-ground VSS \
-simulator xyce
puts "--- write_gate_spice ---"
set gate_spice_file [file join $spice_dir gate_test.sp]

View File

@ -54,11 +54,7 @@ if { [file exists $log_file] } {
# gzstream: Read/write gzipped liberty
#---------------------------------------------------------------
puts "--- gzipped liberty read ---"
set rc [catch { read_liberty ../../test/nangate45/nangate45_typ.lib.gz } msg]
if { $rc == 0 } {
} else {
puts "INFO: gzipped liberty read: $msg"
}
read_liberty ../../test/nangate45/nangate45_typ.lib.gz
#---------------------------------------------------------------
# Report warn path (triggered by warnings in design analysis)