test: Delete dead code from Tcl tests and remove broken write_gate_spice tests

Remove dead code blocks that reference non-exposed Tcl commands (e.g.,
sta::find_pi_pole_residue) and delete all write_gate_spice catch blocks
from spice tests since write_gate_spice_cmd SWIG binding is missing,
making all write_gate_spice calls always fail. Added bug report for the
missing binding. All 6531 tests pass.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

bug_report_missing_write_gate_spice_cmd.md

@@ -0,0 +1,36 @@
+# Bug Report: Missing SWIG binding for `write_gate_spice_cmd`
+
+## Summary
+
+`write_gate_spice` Tcl command always fails with `invalid command name "write_gate_spice_cmd"` because the underlying C++ SWIG binding is not registered.
+
+## Details
+
+- **`write_gate_spice`** is defined as a Tcl proc in `spice/WriteSpice.tcl:138`
+- It calls `write_gate_spice_cmd` at line 198 to invoke the C++ implementation
+- **`write_gate_spice_cmd` is not registered** in any Tcl namespace (neither global nor `::sta::`)
+- In contrast, `write_path_spice_cmd` IS correctly registered as `::sta::write_path_spice_cmd`
+
+## Reproduction
+
+```tcl
+sta::sta -no_init -no_splash -exit /dev/stdin <<'EOF'
+puts [info commands ::sta::write_path_spice_cmd]  ;# returns ::sta::write_path_spice_cmd
+puts [info commands ::sta::write_gate_spice_cmd]  ;# returns empty
+EOF
+```
+
+## Impact
+
+All `write_gate_spice` calls silently fail when wrapped in `catch`, or crash `sta` when called directly. The C++ implementation likely exists in `WriteSpice.cc` but the SWIG `.i` file is missing the binding declaration for `write_gate_spice_cmd`.
+
+## Affected Test Files
+
+The following test files had `write_gate_spice` catch blocks that always produced error output:
+- `spice/test/spice_gate_advanced.tcl`
+- `spice/test/spice_gate_cells.tcl`
+- `spice/test/spice_gcd_gate.tcl`
+- `spice/test/spice_gcd_path.tcl`
+- `spice/test/spice_multipath.tcl`
+- `spice/test/spice_subckt_file.tcl`
+- `spice/test/spice_write_options.tcl`

parasitics/test/parasitics_pi_pole_residue.ok

@@ -99,12 +99,6 @@ Fanout     Cap    Slew   Delay    Time   Description
                                 302.89   slack (MET)
 
 
---- Test 2: query pi_pole_residue ---
-find_pi_pole_residue u1/Y rise max: done (invalid command name "sta::find_pi_pole_residue")
-find_pi_pole_residue u1/Y fall max: done (invalid command name "sta::find_pi_pole_residue")
-find_pi_pole_residue u2/Y rise max: done (invalid command name "sta::find_pi_pole_residue")
-find_pi_pole_residue r1/Q rise max: done (invalid command name "sta::find_pi_pole_residue")
-find_pi_pole_residue r2/Q fall min: done (invalid command name "sta::find_pi_pole_residue")
 --- Test 3: dcalc with two-pole ---
 Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
 Cell: BUFx2_ASAP7_75t_R

parasitics/test/parasitics_pi_pole_residue.tcl

@@ -37,47 +37,6 @@ report_checks -from [get_ports in2] -to [get_ports out]
 
 report_checks -fields {slew cap input_pins nets fanout}
 
-#---------------------------------------------------------------
-# Test 2: Query pi_pole_residue model values
-# Exercises: findPiPoleResidue, poleResidueCount, poleResidue
-#---------------------------------------------------------------
-puts "--- Test 2: query pi_pole_residue ---"
-
-# catch: sta::find_pi_pole_residue is not exposed as Tcl command
-catch {
-  set ppr [sta::find_pi_pole_residue [get_pins u1/Y] "rise" "max"]
-  puts "u1/Y rise max pi_pole_residue: $ppr"
-} msg
-puts "find_pi_pole_residue u1/Y rise max: done ($msg)"
-
-# catch: sta::find_pi_pole_residue is not exposed as Tcl command
-catch {
-  set ppr [sta::find_pi_pole_residue [get_pins u1/Y] "fall" "max"]
-  puts "u1/Y fall max pi_pole_residue: $ppr"
-} msg
-puts "find_pi_pole_residue u1/Y fall max: done ($msg)"
-
-# catch: sta::find_pi_pole_residue is not exposed as Tcl command
-catch {
-  set ppr [sta::find_pi_pole_residue [get_pins u2/Y] "rise" "max"]
-  puts "u2/Y rise max pi_pole_residue: $ppr"
-} msg
-puts "find_pi_pole_residue u2/Y rise max: done ($msg)"
-
-# catch: sta::find_pi_pole_residue is not exposed as Tcl command
-catch {
-  set ppr [sta::find_pi_pole_residue [get_pins r1/Q] "rise" "max"]
-  puts "r1/Q rise max pi_pole_residue: $ppr"
-} msg
-puts "find_pi_pole_residue r1/Q rise max: done ($msg)"
-
-# catch: sta::find_pi_pole_residue is not exposed as Tcl command
-catch {
-  set ppr [sta::find_pi_pole_residue [get_pins r2/Q] "fall" "min"]
-  puts "r2/Q fall min pi_pole_residue: $ppr"
-} msg
-puts "find_pi_pole_residue r2/Q fall min: done ($msg)"
-
 #---------------------------------------------------------------
 # Test 3: Delay calc reports with two-pole model
 # Exercises: parasitic access through dcalc for pole/residue

sdc/test/sdc_clock_operations.ok

@@ -380,7 +380,6 @@ Path Type: max
            0.33   slack (MET)
 
 
---- generated clock invert ---
 --- set_propagated_clock ---
 Startpoint: reg2/Q (clock source 'gclk_edge')
 Endpoint: out1 (output port clocked by clk1)

sdc/test/sdc_clock_operations.tcl

@@ -54,12 +54,6 @@ puts "--- generated clock edges ---"
 create_generated_clock -name gclk_edge -source [get_ports clk1] -edges {1 3 5} [get_pins reg2/Q]
 report_checks
 
-puts "--- generated clock invert ---"
-# -invert with -divide_by 1 and -add on a pin that already has a generated clock
-# Commented out: -add requires -master_clock when multiple clocks drive this pin
-# create_generated_clock -name gclk_inv -source [get_ports clk1] -divide_by 1 -invert [get_pins reg1/Q] -add
-# report_checks
-
 ############################################################
 # Propagated clock
 ############################################################

sdc/test/sdc_delay_borrow_group.tcl

@@ -156,12 +156,6 @@ set_max_delay -from [get_ports in3] -to [get_ports out2] -ignore_clock_latency 7
 
 set_min_delay -from [get_ports in3] -to [get_ports out2] 0.5
 
-############################################################
-# Min fanout limit (covers setMinFanout through set_min_fanout if available)
-############################################################
-# set_min_fanout is not a valid SDC command in OpenSTA
-# set_min_fanout 2 [current_design]
-
 ############################################################
 # Write SDC
 ############################################################

sdc/test/sdc_design_rules_limits.tcl

@@ -68,10 +68,6 @@ set_max_fanout 20 [current_design]
 set_max_fanout 10 [get_ports in1]
 set_max_fanout 15 [get_ports in2]
 
-# Cell-level fanout limit
-# set_max_fanout on a liberty cell object is not supported in OpenSTA
-# set_max_fanout 8 [get_lib_cells NangateOpenCellLibrary/INV_X1]
-
 ############################################################
 # Max area
 ############################################################

sdc/test/sdc_genclk_advanced.tcl

@@ -46,17 +46,6 @@ create_generated_clock -name gclk_mul2 -source [get_ports clk1] -multiply_by 2 [
 # Generated clocks - edges
 ############################################################
 
-# Edge-based generated clock
-# Commented out: -add requires -master_clock when multiple clocks drive this pin
-# create_generated_clock -name gclk_edge -source [get_ports clk1] -edges {1 3 5} [get_pins reg1/Q] -add
-
-############################################################
-# Generated clock - edge shift
-############################################################
-
-# Commented out: -add requires -master_clock when multiple clocks drive this pin
-# create_generated_clock -name gclk_shift -source [get_ports clk2] -edges {1 3 5} -edge_shift {0.0 0.5 1.0} [get_pins reg3/Q] -add
-
 ############################################################
 # Report clock properties after generated clocks
 ############################################################

sdc/test/sdc_port_delay_advanced.tcl

@@ -134,9 +134,6 @@ set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.5
 
 set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold 0.3
 
-# -clock_fall is not a valid option for set_data_check
-# set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.6 -clock_fall
-
 ############################################################
 # Case analysis and logic values (Constants)
 ############################################################

sdc/test/sdc_variables.tcl

@@ -140,16 +140,6 @@ set ::sta_propagate_gated_clock_enable 0
 
 set val $::sta_propagate_gated_clock_enable
 
-############################################################
-# POCV enabled (may require SSTA compilation, use catch)
-############################################################
-
-# POCV variables may not exist if SSTA is not compiled in
-# Commented out: POCV support requires compilation with SSTA=1
-# set ::sta_pocv_enabled 1
-# set ::sta_pocv_enabled 0
-# set val $::sta_pocv_enabled
-
 ############################################################
 # Report default digits
 ############################################################

search/test/search_limits_verbose.ok

@@ -516,7 +516,6 @@ clk                                     1.12
 --- check_setup -multiple_clock ---
 --- check_setup -unconstrained_endpoints ---
 --- check_setup -loops ---
---- slack/limit ratios ---
 --- endpoint_violation_count ---
 max violations: 0
 min violations: 0

search/test/search_limits_verbose.tcl

@@ -207,14 +207,6 @@ check_setup -verbose -unconstrained_endpoints
 puts "--- check_setup -loops ---"
 check_setup -verbose -loops
 
-############################################################
-# max_slew_check_slack_limit / max_cap_check_slack_limit / etc.
-############################################################
-puts "--- slack/limit ratios ---"
-# max_slew_check_slack_limit is not exposed as Tcl command; removed
-# max_capacitance_check_slack_limit is not exposed as Tcl command; removed
-# max_fanout_check_slack_limit is not exposed as Tcl command; removed
-
 ############################################################
 # Endpoint violation counts
 ############################################################

search/test/search_path_enum_groups.ok

@@ -158,7 +158,6 @@ Path group names: clk input_paths output_paths reg2reg_paths asynchronous {path
 clk is group: 1
 input_paths is group: 1
 nonexistent is group: 0
---- group_path -default ---
 --- report_path_ends ---
 Startpoint: in2 (input port clocked by clk)
 Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)

search/test/search_path_enum_groups.tcl

@@ -78,9 +78,6 @@ puts "clk is group: [sta::is_path_group_name clk]"
 puts "input_paths is group: [sta::is_path_group_name input_paths]"
 puts "nonexistent is group: [sta::is_path_group_name nonexistent_group]"
 
-puts "--- group_path -default ---"
-# group_path -name and -default are mutually exclusive; removed
-
 puts "--- report_path_ends ---"
 set pe_list [find_timing_paths -path_delay max -endpoint_path_count 5]
 sta::report_path_end_header

spice/test/spice_gate_advanced.ok

@@ -27,14 +27,6 @@ Path Type: max
            8.90   slack (MET)
 
 
---- write_gate_spice ngspice ---
-INFO: write_gate_spice ngspice: invalid command name "write_gate_spice_cmd"
---- write_gate_spice fall ---
-INFO: write_gate_spice fall: invalid command name "write_gate_spice_cmd"
---- write_gate_spice xyce ---
-INFO: write_gate_spice xyce: invalid command name "write_gate_spice_cmd"
---- write_gate_spice hspice ---
-INFO: write_gate_spice hspice: invalid command name "write_gate_spice_cmd"
 --- write_path_spice max slack ---
 --- write_path_spice min path ---
 --- write_path_spice hspice ---

spice/test/spice_gate_advanced.tcl

@@ -1,6 +1,7 @@
-# Test advanced SPICE writing: write_gate_spice with various options,
-# multiple simulators, min/max paths, write_path_spice with -path_args options.
-# Targets uncovered WriteSpice.cc and WritePathSpice.cc paths.
+# Test advanced SPICE writing: write_path_spice with -path_args options
+# and various simulators.
+# NOTE: write_gate_spice tests removed - write_gate_spice_cmd SWIG binding
+# is missing. See bug_report_missing_write_gate_spice_cmd.md.
 
 source ../../test/helpers.tcl
 
@@ -46,89 +47,6 @@ puts $subckt_fh "M2 Q D VSS VSS nmos W=1u L=100n"
 puts $subckt_fh ".ends"
 close $subckt_fh
 
-#---------------------------------------------------------------
-# write_gate_spice - ngspice (default)
-#---------------------------------------------------------------
-puts "--- write_gate_spice ngspice ---"
-set gate_file1 [file join $spice_dir gate_ng.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc1 [catch {
-  write_gate_spice \
-    -gates {{buf1 A Z rise}} \
-    -spice_filename $gate_file1 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS
-} msg1]
-if { $rc1 == 0 } {
-} else {
-  puts "INFO: write_gate_spice ngspice: $msg1"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice - fall transition
-#---------------------------------------------------------------
-puts "--- write_gate_spice fall ---"
-set gate_file2 [file join $spice_dir gate_fall.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc2 [catch {
-  write_gate_spice \
-    -gates {{buf1 A Z fall}} \
-    -spice_filename $gate_file2 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS \
-    -simulator ngspice
-} msg2]
-if { $rc2 == 0 } {
-} else {
-  puts "INFO: write_gate_spice fall: $msg2"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice - xyce simulator
-#---------------------------------------------------------------
-puts "--- write_gate_spice xyce ---"
-set gate_file3 [file join $spice_dir gate_xyce.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc3 [catch {
-  write_gate_spice \
-    -gates {{buf1 A Z rise}} \
-    -spice_filename $gate_file3 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS \
-    -simulator xyce
-} msg3]
-if { $rc3 == 0 } {
-} else {
-  puts "INFO: write_gate_spice xyce: $msg3"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice - hspice simulator
-#---------------------------------------------------------------
-puts "--- write_gate_spice hspice ---"
-set gate_file4 [file join $spice_dir gate_hspice.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc4 [catch {
-  write_gate_spice \
-    -gates {{buf1 A Z rise}} \
-    -spice_filename $gate_file4 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS \
-    -simulator hspice
-} msg4]
-if { $rc4 == 0 } {
-} else {
-  puts "INFO: write_gate_spice hspice: $msg4"
-}
-
 #---------------------------------------------------------------
 # write_path_spice with -path_args max slack
 #---------------------------------------------------------------

spice/test/spice_gate_cells.ok

@@ -28,25 +28,3 @@ Path Type: max
            8.86   slack (MET)
 
 
---- write_gate_spice BUF_X1 rise ngspice ---
-INFO: write_gate_spice BUF rise: invalid command name "write_gate_spice_cmd"
---- write_gate_spice BUF_X1 fall ---
-INFO: write_gate_spice BUF fall: invalid command name "write_gate_spice_cmd"
---- write_gate_spice INV_X1 rise ---
-INFO: write_gate_spice INV rise: invalid command name "write_gate_spice_cmd"
---- write_gate_spice INV_X1 fall ---
-INFO: write_gate_spice INV fall: invalid command name "write_gate_spice_cmd"
---- write_gate_spice AND2_X1 rise ---
-INFO: write_gate_spice AND rise: invalid command name "write_gate_spice_cmd"
---- write_gate_spice AND2_X1 A2 ---
-INFO: write_gate_spice AND A2: invalid command name "write_gate_spice_cmd"
---- write_gate_spice OR2_X1 rise ---
-INFO: write_gate_spice OR rise: invalid command name "write_gate_spice_cmd"
---- write_gate_spice hspice ---
-INFO: write_gate_spice hspice: invalid command name "write_gate_spice_cmd"
---- write_gate_spice xyce ---
-INFO: write_gate_spice xyce: invalid command name "write_gate_spice_cmd"
---- write_gate_spice xyce INV ---
-INFO: write_gate_spice xyce INV: invalid command name "write_gate_spice_cmd"
---- write_gate_spice hspice AND ---
-INFO: write_gate_spice hspice AND: invalid command name "write_gate_spice_cmd"

spice/test/spice_gate_cells.tcl

@@ -1,8 +1,8 @@
 # Test write_gate_spice with different cell types, rise/fall transitions,
 # and multiple simulators.
-# Targets: WriteSpice.cc (subckt file parsing, multiple cell types,
-#   rise/fall pin handling, Xyce/HSpice specific output)
-#   WritePathSpice.cc (cell-level spice generation)
+# NOTE: All write_gate_spice tests removed - write_gate_spice_cmd SWIG binding
+# is missing. See bug_report_missing_write_gate_spice_cmd.md.
+# Only baseline timing check remains.
 
 source ../../test/helpers.tcl
 
@@ -19,267 +19,3 @@ set_input_transition 0.1 [get_ports {in1 in2}]
 
 puts "--- report_checks baseline ---"
 report_checks
-
-# Create mock SPICE files
-set spice_dir [make_result_file spice_gate_cells]
-file mkdir $spice_dir
-
-set model_file [file join $spice_dir mock_model.sp]
-set model_fh [open $model_file w]
-puts $model_fh "* Mock SPICE model file"
-puts $model_fh ".model nmos nmos level=1"
-puts $model_fh ".model pmos pmos level=1"
-close $model_fh
-
-set subckt_file [file join $spice_dir mock_subckt.sp]
-set subckt_fh [open $subckt_file w]
-puts $subckt_fh "* Mock SPICE subckt file"
-puts $subckt_fh ".subckt BUF_X1 A Z VDD VSS"
-puts $subckt_fh "M1 Z A VDD VDD pmos W=1u L=100n"
-puts $subckt_fh "M2 Z A VSS VSS nmos W=1u L=100n"
-puts $subckt_fh ".ends"
-puts $subckt_fh ""
-puts $subckt_fh ".subckt INV_X1 A ZN VDD VSS"
-puts $subckt_fh "M1 ZN A VDD VDD pmos W=1u L=100n"
-puts $subckt_fh "M2 ZN A VSS VSS nmos W=1u L=100n"
-puts $subckt_fh ".ends"
-puts $subckt_fh ""
-puts $subckt_fh ".subckt AND2_X1 A1 A2 ZN VDD VSS"
-puts $subckt_fh "M1 ZN A1 VDD VDD pmos W=1u L=100n"
-puts $subckt_fh "M2 ZN A2 VSS VSS nmos W=1u L=100n"
-puts $subckt_fh ".ends"
-puts $subckt_fh ""
-puts $subckt_fh ".subckt OR2_X1 A1 A2 ZN VDD VSS"
-puts $subckt_fh "M1 ZN A1 VDD VDD pmos W=1u L=100n"
-puts $subckt_fh "M2 ZN A2 VSS VSS nmos W=1u L=100n"
-puts $subckt_fh ".ends"
-puts $subckt_fh ""
-puts $subckt_fh ".subckt DFF_X1 D CK Q QN VDD VSS"
-puts $subckt_fh "M1 Q D VDD VDD pmos W=1u L=100n"
-puts $subckt_fh "M2 Q D VSS VSS nmos W=1u L=100n"
-puts $subckt_fh ".ends"
-close $subckt_fh
-
-#---------------------------------------------------------------
-# write_gate_spice - BUF_X1 rise (ngspice)
-#---------------------------------------------------------------
-puts "--- write_gate_spice BUF_X1 rise ngspice ---"
-set gate_f1 [file join $spice_dir gate_buf_rise.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc1 [catch {
-  write_gate_spice \
-    -gates {{buf1 A Z rise}} \
-    -spice_filename $gate_f1 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS
-} msg1]
-if { $rc1 == 0 } {
-} else {
-  puts "INFO: write_gate_spice BUF rise: $msg1"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice - BUF_X1 fall
-#---------------------------------------------------------------
-puts "--- write_gate_spice BUF_X1 fall ---"
-set gate_f2 [file join $spice_dir gate_buf_fall.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc2 [catch {
-  write_gate_spice \
-    -gates {{buf1 A Z fall}} \
-    -spice_filename $gate_f2 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS
-} msg2]
-if { $rc2 == 0 } {
-} else {
-  puts "INFO: write_gate_spice BUF fall: $msg2"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice - INV_X1 rise
-#---------------------------------------------------------------
-puts "--- write_gate_spice INV_X1 rise ---"
-set gate_f3 [file join $spice_dir gate_inv_rise.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc3 [catch {
-  write_gate_spice \
-    -gates {{inv1 A ZN rise}} \
-    -spice_filename $gate_f3 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS
-} msg3]
-if { $rc3 == 0 } {
-} else {
-  puts "INFO: write_gate_spice INV rise: $msg3"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice - INV_X1 fall
-#---------------------------------------------------------------
-puts "--- write_gate_spice INV_X1 fall ---"
-set gate_f4 [file join $spice_dir gate_inv_fall.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc4 [catch {
-  write_gate_spice \
-    -gates {{inv1 A ZN fall}} \
-    -spice_filename $gate_f4 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS
-} msg4]
-if { $rc4 == 0 } {
-} else {
-  puts "INFO: write_gate_spice INV fall: $msg4"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice - AND2_X1 rise (multi-input)
-#---------------------------------------------------------------
-puts "--- write_gate_spice AND2_X1 rise ---"
-set gate_f5 [file join $spice_dir gate_and_rise.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc5 [catch {
-  write_gate_spice \
-    -gates {{and1 A1 ZN rise}} \
-    -spice_filename $gate_f5 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS
-} msg5]
-if { $rc5 == 0 } {
-} else {
-  puts "INFO: write_gate_spice AND rise: $msg5"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice - AND2_X1 from A2 input
-#---------------------------------------------------------------
-puts "--- write_gate_spice AND2_X1 A2 ---"
-set gate_f5b [file join $spice_dir gate_and_a2.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc5b [catch {
-  write_gate_spice \
-    -gates {{and1 A2 ZN rise}} \
-    -spice_filename $gate_f5b \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS
-} msg5b]
-if { $rc5b == 0 } {
-} else {
-  puts "INFO: write_gate_spice AND A2: $msg5b"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice - OR2_X1 rise
-#---------------------------------------------------------------
-puts "--- write_gate_spice OR2_X1 rise ---"
-set gate_f6 [file join $spice_dir gate_or_rise.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc6 [catch {
-  write_gate_spice \
-    -gates {{or1 A1 ZN rise}} \
-    -spice_filename $gate_f6 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS
-} msg6]
-if { $rc6 == 0 } {
-} else {
-  puts "INFO: write_gate_spice OR rise: $msg6"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice with hspice simulator
-#---------------------------------------------------------------
-puts "--- write_gate_spice hspice ---"
-set gate_f7 [file join $spice_dir gate_hspice.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc7 [catch {
-  write_gate_spice \
-    -gates {{buf1 A Z rise}} \
-    -spice_filename $gate_f7 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS \
-    -simulator hspice
-} msg7]
-if { $rc7 == 0 } {
-} else {
-  puts "INFO: write_gate_spice hspice: $msg7"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice with xyce simulator
-#---------------------------------------------------------------
-puts "--- write_gate_spice xyce ---"
-set gate_f8 [file join $spice_dir gate_xyce.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc8 [catch {
-  write_gate_spice \
-    -gates {{buf1 A Z rise}} \
-    -spice_filename $gate_f8 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS \
-    -simulator xyce
-} msg8]
-if { $rc8 == 0 } {
-} else {
-  puts "INFO: write_gate_spice xyce: $msg8"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice with xyce for INV cell (different topology)
-#---------------------------------------------------------------
-puts "--- write_gate_spice xyce INV ---"
-set gate_f9 [file join $spice_dir gate_xyce_inv.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc9 [catch {
-  write_gate_spice \
-    -gates {{inv1 A ZN fall}} \
-    -spice_filename $gate_f9 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS \
-    -simulator xyce
-} msg9]
-if { $rc9 == 0 } {
-} else {
-  puts "INFO: write_gate_spice xyce INV: $msg9"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice with hspice for AND cell
-#---------------------------------------------------------------
-puts "--- write_gate_spice hspice AND ---"
-set gate_f10 [file join $spice_dir gate_hspice_and.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc10 [catch {
-  write_gate_spice \
-    -gates {{and1 A1 ZN fall}} \
-    -spice_filename $gate_f10 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS \
-    -simulator hspice
-} msg10]
-if { $rc10 == 0 } {
-} else {
-  puts "INFO: write_gate_spice hspice AND: $msg10"
-}

spice/test/spice_gcd_gate.ok

@@ -39,15 +39,6 @@ Path Type: max
            0.75   slack (MET)
 
 
-total cells: 1292
---- write_gate_spice ngspice buf ---
-INFO: write_gate_spice ngspice buf: invalid command name "write_gate_spice_cmd"
---- write_gate_spice ngspice buf fall ---
-INFO: write_gate_spice ngspice buf fall: invalid command name "write_gate_spice_cmd"
---- write_gate_spice hspice buf ---
-INFO: write_gate_spice hspice buf: invalid command name "write_gate_spice_cmd"
---- write_gate_spice xyce buf ---
-INFO: write_gate_spice xyce buf: invalid command name "write_gate_spice_cmd"
 --- write_path_spice tests ---
 INFO: write_path_spice ngspice max: Error: The subkct file /workspace/sta/OpenSTA/spice/test/results/spice_gcd_gate_out/sky130_subckt.sp is missing definitions for 
 sky130_fd_sc_hd__a21boi_2

spice/test/spice_gcd_gate.tcl

@@ -1,6 +1,8 @@
-# Test write_gate_spice and write_path_spice with GCD sky130 design.
+# Test write_path_spice with GCD sky130 design.
 # Uses a larger design to exercise different cell type handling,
 # multi-input gates, and varied simulator outputs.
+# NOTE: write_gate_spice tests removed - write_gate_spice_cmd SWIG binding
+# is missing. See bug_report_missing_write_gate_spice_cmd.md.
 source ../../test/helpers.tcl
 
 read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib
@@ -58,52 +60,6 @@ foreach cell_def {
 }
 close $sfh
 
-#---------------------------------------------------------------
-# write_gate_spice with different gate types and simulators
-#---------------------------------------------------------------
-
-# Helper proc to test write_gate_spice
-proc test_gate_spice {label gates filename subckt model sim} {
-  puts "--- write_gate_spice $label ---"
-  # catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-  set rc [catch {
-    write_gate_spice \
-      -gates $gates \
-      -spice_filename $filename \
-      -lib_subckt_file $subckt \
-      -model_file $model \
-      -power VPWR \
-      -ground VGND \
-      -simulator $sim
-  } msg]
-  if { $rc == 0 } {
-    if { [file exists $filename] } {
-      puts "  file size: [file size $filename]"
-    }
-  } else {
-    puts "INFO: write_gate_spice $label: $msg"
-  }
-}
-
-# Get cell instance names from the design
-set all_cells [get_cells *]
-puts "total cells: [llength $all_cells]"
-
-# Test various cell types with ngspice (default)
-set f1 [file join $spice_dir gate_ngspice.sp]
-test_gate_spice "ngspice buf" {{_340_ A X rise}} $f1 $subckt_file $model_file ngspice
-
-set f2 [file join $spice_dir gate_ngspice_fall.sp]
-test_gate_spice "ngspice buf fall" {{_340_ A X fall}} $f2 $subckt_file $model_file ngspice
-
-# hspice simulator - exercises ".options nomod" path
-set f3 [file join $spice_dir gate_hspice.sp]
-test_gate_spice "hspice buf" {{_340_ A X rise}} $f3 $subckt_file $model_file hspice
-
-# xyce simulator - exercises CSV/gnuplot file generation
-set f4 [file join $spice_dir gate_xyce.sp]
-test_gate_spice "xyce buf" {{_340_ A X rise}} $f4 $subckt_file $model_file xyce
-
 #---------------------------------------------------------------
 # write_path_spice with different simulators and path options
 #---------------------------------------------------------------

spice/test/spice_gcd_path.ok

@@ -76,8 +76,3 @@ Warning: spice_gcd_path.tcl line 1, port '*' not found.
 --- write_path_spice xyce ---
 --- write_path_spice specific endpoints ---
 INFO: write_path_spice specific: Error: spice_gcd_path.tcl line 1, No paths found for -path_args -from req_msg[0] -to resp_msg[0].
---- write_gate_spice sky130hd cells ---
-Warning: spice_gcd_path.tcl line 1, instance '_300_' not found.
-INFO: gate sky130_fd_sc_hd__xnor2_1 (_197_): invalid command name "write_gate_spice_cmd"
-INFO: gate sky130_fd_sc_hd__inv_1 (_205_): invalid command name "write_gate_spice_cmd"
-INFO: gate sky130_fd_sc_hd__nand2_2 (_206_): invalid command name "write_gate_spice_cmd"

spice/test/spice_gcd_path.tcl

@@ -145,62 +145,3 @@ if { $rc == 0 } {
 } else {
   puts "INFO: write_path_spice specific: $msg"
 }
-
-#---------------------------------------------------------------
-# write_gate_spice for various sky130hd cells
-# Exercises: WriteGateSpice code paths for different cell topologies
-#---------------------------------------------------------------
-puts "--- write_gate_spice sky130hd cells ---"
-
-# Find some instances for gate spice using known patterns
-set gate_test_insts [list]
-foreach pat {_197_ _205_ _206_ _300_} {
-  # catch: cell pattern may not match any instances
-  set rc [catch { set c [get_cells $pat] } msg]
-  if { $rc == 0 && [llength $c] > 0 } {
-    lappend gate_test_insts [lindex $c 0]
-    if { [llength $gate_test_insts] >= 4 } { break }
-  }
-}
-set tested 0
-foreach inst $gate_test_insts {
-  set cell_ref [get_property $inst ref_name]
-  set inst_name [get_property $inst name]
-
-  # Get input/output pins from the lib cell
-  set in_pin ""
-  set out_pin ""
-  # catch: get_lib_pins may fail for some cell types
-  set rc [catch {
-    set cell_pins [get_lib_pins */${cell_ref}/*]
-    foreach lp $cell_pins {
-      set dir [get_property $lp direction]
-      set pname [get_property $lp name]
-      if { $dir eq "input" && $in_pin eq "" } {
-        set in_pin $pname
-      }
-      if { $dir eq "output" && $out_pin eq "" } {
-        set out_pin $pname
-      }
-    }
-  } msg]
-
-  if { $in_pin ne "" && $out_pin ne "" } {
-    set gf [file join $spice_dir "gate_${inst_name}.sp"]
-    # catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-    set rc [catch {
-      write_gate_spice \
-        -gates [list [list $inst_name $in_pin $out_pin rise]] \
-        -spice_filename $gf \
-        -lib_subckt_file $subckt_file \
-        -model_file $model_file \
-        -power VPWR \
-        -ground VGND
-    } msg]
-    if { $rc == 0 } {
-    } else {
-      puts "INFO: gate $cell_ref ($inst_name): $msg"
-    }
-    incr tested
-  }
-}

spice/test/spice_multipath.ok

@@ -65,12 +65,3 @@ No paths found.
 INFO: write_path_spice specific: Error: spice_multipath.tcl line 1, No paths found for -path_args -from in1 -to out1.
 --- write_path_spice hspice ---
 --- write_path_spice xyce ---
---- write_gate_spice multiple cells ---
-INFO: gate BUF rise: invalid command name "write_gate_spice_cmd"
-INFO: gate BUF fall: invalid command name "write_gate_spice_cmd"
-INFO: gate INV rise: invalid command name "write_gate_spice_cmd"
-INFO: gate AND A1 rise: invalid command name "write_gate_spice_cmd"
-INFO: gate AND A2 fall: invalid command name "write_gate_spice_cmd"
-INFO: gate OR rise: invalid command name "write_gate_spice_cmd"
-INFO: gate INV hspice: invalid command name "write_gate_spice_cmd"
-INFO: gate OR xyce: invalid command name "write_gate_spice_cmd"

spice/test/spice_multipath.tcl

@@ -176,88 +176,3 @@ write_path_spice \
   -power VDD \
   -ground VSS \
   -simulator xyce
-
-#---------------------------------------------------------------
-# write_gate_spice with multiple cells and transitions
-#---------------------------------------------------------------
-puts "--- write_gate_spice multiple cells ---"
-
-# BUF rise
-set gf1 [file join $spice_dir gate_buf_rise.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc [catch {
-  write_gate_spice -gates {{buf1 A Z rise}} -spice_filename $gf1 \
-    -lib_subckt_file $subckt_file -model_file $model_file \
-    -power VDD -ground VSS
-} msg]
-if { $rc == 0 } { puts "gate BUF rise" } else { puts "INFO: gate BUF rise: $msg" }
-
-# BUF fall
-set gf2 [file join $spice_dir gate_buf_fall.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc [catch {
-  write_gate_spice -gates {{buf1 A Z fall}} -spice_filename $gf2 \
-    -lib_subckt_file $subckt_file -model_file $model_file \
-    -power VDD -ground VSS
-} msg]
-if { $rc == 0 } { puts "gate BUF fall" } else { puts "INFO: gate BUF fall: $msg" }
-
-# INV rise
-set gf3 [file join $spice_dir gate_inv_rise.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc [catch {
-  write_gate_spice -gates {{inv1 A ZN rise}} -spice_filename $gf3 \
-    -lib_subckt_file $subckt_file -model_file $model_file \
-    -power VDD -ground VSS
-} msg]
-if { $rc == 0 } { puts "gate INV rise" } else { puts "INFO: gate INV rise: $msg" }
-
-# AND rise from A1
-set gf4 [file join $spice_dir gate_and_a1_rise.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc [catch {
-  write_gate_spice -gates {{and1 A1 ZN rise}} -spice_filename $gf4 \
-    -lib_subckt_file $subckt_file -model_file $model_file \
-    -power VDD -ground VSS
-} msg]
-if { $rc == 0 } { puts "gate AND A1 rise" } else { puts "INFO: gate AND A1 rise: $msg" }
-
-# AND fall from A2
-set gf5 [file join $spice_dir gate_and_a2_fall.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc [catch {
-  write_gate_spice -gates {{and1 A2 ZN fall}} -spice_filename $gf5 \
-    -lib_subckt_file $subckt_file -model_file $model_file \
-    -power VDD -ground VSS
-} msg]
-if { $rc == 0 } { puts "gate AND A2 fall" } else { puts "INFO: gate AND A2 fall: $msg" }
-
-# OR rise
-set gf6 [file join $spice_dir gate_or_rise.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc [catch {
-  write_gate_spice -gates {{or1 A1 ZN rise}} -spice_filename $gf6 \
-    -lib_subckt_file $subckt_file -model_file $model_file \
-    -power VDD -ground VSS
-} msg]
-if { $rc == 0 } { puts "gate OR rise" } else { puts "INFO: gate OR rise: $msg" }
-
-# Hspice simulator variants
-set gf7 [file join $spice_dir gate_inv_hspice.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc [catch {
-  write_gate_spice -gates {{inv1 A ZN fall}} -spice_filename $gf7 \
-    -lib_subckt_file $subckt_file -model_file $model_file \
-    -power VDD -ground VSS -simulator hspice
-} msg]
-if { $rc == 0 } { puts "gate INV hspice" } else { puts "INFO: gate INV hspice: $msg" }
-
-# Xyce simulator variants
-set gf8 [file join $spice_dir gate_or_xyce.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc [catch {
-  write_gate_spice -gates {{or1 A2 ZN rise}} -spice_filename $gf8 \
-    -lib_subckt_file $subckt_file -model_file $model_file \
-    -power VDD -ground VSS -simulator xyce
-} msg]
-if { $rc == 0 } { puts "gate OR xyce" } else { puts "INFO: gate OR xyce: $msg" }

spice/test/spice_subckt_file.ok

@@ -28,10 +28,6 @@ Path Type: max
            8.86   slack (MET)
 
 
---- write_gate_spice multiple gates ---
-INFO: write_gate_spice multiple gates: invalid command name "write_gate_spice_cmd"
---- write_gate_spice AND gate ---
-INFO: write_gate_spice AND: invalid command name "write_gate_spice_cmd"
 --- write_path_spice to out1 ---
 --- write_path_spice to out2 ---
 --- write_path_spice with ngspice ---

spice/test/spice_subckt_file.tcl

@@ -1,12 +1,12 @@
-# Test write_path_spice and write_gate_spice with -subcircuit_file option
+# Test write_path_spice with -subcircuit_file option
 # and various path configurations to exercise uncovered WriteSpice.cc paths:
 #   WriteSpice constructor paths
 #   writeSubckt, findSubckt paths
-#   gatePortValues, inputStimulus paths
 #   simulator-specific code paths (ngspice, hspice, xyce)
-#   writeGateSpice error handling
 # Also targets WritePathSpice.cc:
 #   writePathSpice with different -path_args options
+# NOTE: write_gate_spice tests removed - write_gate_spice_cmd SWIG binding
+# is missing. See bug_report_missing_write_gate_spice_cmd.md.
 
 source ../../test/helpers.tcl
 
@@ -62,46 +62,6 @@ puts $subckt_fh "M2 Q D VSS VSS nmos W=1u L=100n"
 puts $subckt_fh ".ends"
 close $subckt_fh
 
-#---------------------------------------------------------------
-# write_gate_spice with multiple gates in one call
-#---------------------------------------------------------------
-puts "--- write_gate_spice multiple gates ---"
-set gate_file [file join $spice_dir gates_multi.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc [catch {
-  write_gate_spice \
-    -gates {{buf1 A Z rise} {inv1 A ZN fall}} \
-    -spice_filename $gate_file \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS
-} msg]
-if { $rc == 0 } {
-} else {
-  puts "INFO: write_gate_spice multiple gates: $msg"
-}
-
-#---------------------------------------------------------------
-# write_gate_spice with AND gate
-#---------------------------------------------------------------
-puts "--- write_gate_spice AND gate ---"
-set gate_file2 [file join $spice_dir gate_and.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc [catch {
-  write_gate_spice \
-    -gates {{and1 A1 ZN rise}} \
-    -spice_filename $gate_file2 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS
-} msg]
-if { $rc == 0 } {
-} else {
-  puts "INFO: write_gate_spice AND: $msg"
-}
-
 #---------------------------------------------------------------
 # write_path_spice with various options
 #---------------------------------------------------------------

spice/test/spice_write_options.ok

@@ -28,7 +28,3 @@ Path Type: max
 --- write_path_spice default ---
 --- write_path_spice with -simulator hspice ---
 --- write_path_spice with -simulator xyce ---
---- write_gate_spice ---
-INFO: write_gate_spice: invalid command name "write_gate_spice_cmd"
---- write_gate_spice with -simulator hspice ---
-INFO: write_gate_spice hspice: invalid command name "write_gate_spice_cmd"

spice/test/spice_write_options.tcl

@@ -70,38 +70,3 @@ write_path_spice \
   -power VDD \
   -ground VSS \
   -simulator xyce
-
-puts "--- write_gate_spice ---"
-set gate_spice_file [file join $spice_dir gate_test.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc4 [catch {
-  write_gate_spice \
-    -gates {{buf1 A Z rise}} \
-    -spice_filename $gate_spice_file \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS
-} msg4]
-if { $rc4 == 0 } {
-} else {
-  puts "INFO: write_gate_spice: $msg4"
-}
-
-puts "--- write_gate_spice with -simulator hspice ---"
-set gate_spice_file2 [file join $spice_dir gate_test2.sp]
-# catch: write_gate_spice may fail if subckt pin mapping doesn't match liberty cell
-set rc5 [catch {
-  write_gate_spice \
-    -gates {{buf1 A Z rise}} \
-    -spice_filename $gate_spice_file2 \
-    -lib_subckt_file $subckt_file \
-    -model_file $model_file \
-    -power VDD \
-    -ground VSS \
-    -simulator hspice
-} msg5]
-if { $rc5 == 0 } {
-} else {
-  puts "INFO: write_gate_spice hspice: $msg5"
-}