Michael Timothy Grimes e4a94e8597 Merging changes to bank. Bank has been altered to accommodate multiport. Single port still passes unit test, though some control signal names have been changed to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can accurately generate a spice netlist.

2018-08-15 04:00:48 -07:00

..

bank_select.py

bank_sel_bar only used for clk now

2018-08-13 15:14:52 -07:00

bank.py

Merging changes to bank. Bank has been altered to accommodate multiport. Single port still passes unit test, though some control signal names have been changed to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can accurately generate a spice netlist.

2018-08-15 04:00:48 -07:00

bitcell_array.py

Remove carriage returns form python files

2018-08-07 09:44:01 -07:00

bitcell.py

altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions

2018-08-05 19:43:59 -07:00

control_logic.py

Connect data and column DFF clocks in 1 bank.

2018-08-14 10:09:41 -07:00

delay_chain.py

Fix s_en stages to be even per Kevin's bug report. Assert minimum fanout to ensure vdd/gnd connections.

2018-07-19 10:51:20 -07:00

dff_array.py

Connect data and column DFF clocks in 1 bank.

2018-08-14 10:09:41 -07:00

dff_buf_array.py

Fix routing clk connections of dff arrays

2018-07-18 11:38:58 -07:00

dff_buf.py

Limit sizes for dff_buf too. Add comments about restriction.

2018-07-27 08:17:50 -07:00

dff_inv_array.py

Fix routing clk connections of dff arrays

2018-07-18 11:38:58 -07:00

dff_inv.py

Limit sizes for dff_buf too. Add comments about restriction.

2018-07-27 08:17:50 -07:00

dff.py

Add dff_buf for buffered flop arrays.

2018-03-04 16:13:10 -08:00

hierarchical_decoder.py

Use lower case names except for leaf cells and top level

2018-07-18 15:10:57 -07:00

hierarchical_predecode2x4.py

First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.

2018-02-26 16:32:28 -08:00

hierarchical_predecode3x8.py

First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.

2018-02-26 16:32:28 -08:00

hierarchical_predecode.py

Fix spacing between adjacent decoders

2018-07-17 15:01:16 -07:00

ms_flop_array.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

ms_flop.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

precharge_array.py

editted naming convention on precharge to accommodate multiport

2018-08-15 02:14:45 -07:00

replica_bitcell.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00

replica_bitline.py

Connect data and column DFF clocks in 1 bank.

2018-08-14 10:09:41 -07:00

sense_amp_array.py

Fix sense amp spacing after modifying index to be increment by one.

2018-06-29 15:30:17 -07:00

sense_amp.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

single_level_column_mux_array.py

Consolidate metal pitch rules to new design class

2018-07-09 15:42:46 -07:00

tri_gate_array.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

tri_gate.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

wordline_driver.py

Modified pinvbuf to have a stage effort of 4 for driving the

2018-07-26 11:28:48 -07:00

write_driver_array.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

write_driver.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00