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base
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Remove carriage returns form python files
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2018-08-07 09:44:01 -07:00 |
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characterizer
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Remove OEB signal since we split DIN/DOUT ports
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2018-08-13 14:09:49 -07:00 |
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gdsMill
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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modules
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Merging changes to bank. Bank has been altered to accommodate multiport. Single port still passes unit test, though some control signal names have been changed to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can accurately generate a spice netlist.
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2018-08-15 04:00:48 -07:00 |
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pgates
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called bitcell function before reading the height of the bitcell because pbitcell's dynamic height can only be determined after the module is called
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2018-08-15 02:19:36 -07:00 |
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router
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Fix unit tests to be DRC clean.
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2017-06-07 10:29:53 -07:00 |
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tests
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Merging changes to bank. Bank has been altered to accommodate multiport. Single port still passes unit test, though some control signal names have been changed to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can accurately generate a spice netlist.
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2018-08-15 04:00:48 -07:00 |
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verify
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Add temporary options to LVS to allow name merging
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2018-07-18 15:10:29 -07:00 |
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Makefile
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Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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debug.py
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Output debug warnings and errors to stderr. Clean up regress script a bit.
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2018-07-11 09:51:28 -07:00 |
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example_config_freepdk45.py
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Fix num words in example.
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2018-02-23 12:17:43 -08:00 |
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example_config_scn3me_subm.py
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Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library.
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2018-02-12 11:22:47 -08:00 |
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gen_stimulus.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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globals.py
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Only print LVS/DRC stats when it is enabled
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2018-07-25 13:44:34 -07:00 |
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openram.py
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Improve openram output. Fix save output function name.
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2018-07-12 10:35:38 -07:00 |
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options.py
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Fix options so it is in /tmp in RAM drive
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2018-07-05 16:33:26 -07:00 |
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sram.py
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Add verilog_write to sram wrapper for verilog unit test
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2018-07-19 10:05:30 -07:00 |
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sram_1bank.py
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Finalize single bank clock routing.
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2018-08-14 10:36:35 -07:00 |
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sram_2bank.py
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Add LVS correspondence points to each bank type
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2018-07-18 14:29:04 -07:00 |
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sram_4bank.py
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Add LVS correspondence points to each bank type
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2018-07-18 14:29:04 -07:00 |
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sram_base.py
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Finalize single bank clock routing.
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2018-08-14 10:36:35 -07:00 |
e4a94e8597