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bank.py
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Move rbl route away from bitcell array
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2020-03-06 09:48:20 -08:00 |
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bank_select.py
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Cleanup and rename vias.
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2020-01-30 01:45:33 +00:00 |
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bitcell_array.py
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Cleanup and rename vias.
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2020-01-30 01:45:33 +00:00 |
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bitcell_base_array.py
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Vdd/gnd via stacks now use perferred directions, added cell property to override
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2020-03-04 17:05:19 -08:00 |
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control_logic.py
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Changed layout input names of s_en AND gate to match the schematic
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2020-02-19 23:32:11 -08:00 |
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delay_chain.py
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Clean up and generalize layer rules.
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2019-12-17 11:03:36 -08:00 |
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dff.py
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merge custom cell and module properties
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2020-02-12 04:09:40 +00:00 |
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dff_array.py
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add custom module file, make dff clk pin dynamic
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2020-02-04 23:35:06 -08:00 |
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dff_buf.py
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remove whitespace
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2020-04-05 03:58:26 -07:00 |
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dff_buf_array.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev
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2020-02-12 06:54:03 +00:00 |
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dff_inv.py
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Clean up and generalize layer rules.
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2019-12-17 11:03:36 -08:00 |
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dff_inv_array.py
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Clean up and generalize layer rules.
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2019-12-17 11:03:36 -08:00 |
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dummy_array.py
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Fix base bitcell syntax error. Remove some unused imports.
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2020-01-30 01:58:30 +00:00 |
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hierarchical_decoder.py
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Dynamically try and DRC decoder for height
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2020-04-08 16:45:28 -07:00 |
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hierarchical_predecode.py
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Convert pnand+pinv to pand in decoders.
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2020-03-06 13:26:40 -08:00 |
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hierarchical_predecode2x4.py
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Convert pnand+pinv to pand in decoders.
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2020-03-06 13:26:40 -08:00 |
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hierarchical_predecode3x8.py
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Convert pnand+pinv to pand in decoders.
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2020-03-06 13:26:40 -08:00 |
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module_type.py
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Cleanup and rename vias.
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2020-01-30 01:45:33 +00:00 |
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multibank.py
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Cleanup and rename vias.
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2020-01-30 01:45:33 +00:00 |
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port_address.py
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Add separate well design rules.
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2020-01-23 19:43:41 +00:00 |
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port_data.py
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PEP8 Formatting
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2020-03-05 10:21:18 -08:00 |
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precharge_array.py
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Add licon option to precharge
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2020-04-01 11:26:45 -07:00 |
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replica_bitcell_array.py
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replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names
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2020-02-12 15:37:47 +01:00 |
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replica_column.py
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Bitcell arrays: Allow mirroring on the y axis
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2020-01-28 15:51:21 +01:00 |
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sense_amp.py
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sense_amp: Allow custom pin names
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2020-02-17 15:20:12 +01:00 |
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sense_amp_array.py
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PEP8 updates
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2020-03-31 10:15:46 -07:00 |
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single_level_column_mux_array.py
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modules/port_data: Add get_bl/br_name method
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2020-02-17 14:18:32 +01:00 |
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tri_gate.py
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Made all cin function relate to farads and all input_load relate to relative units.
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2019-08-08 01:57:04 -07:00 |
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tri_gate_array.py
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Clean up and generalize layer rules.
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2019-12-17 11:03:36 -08:00 |
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wordline_driver.py
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Rotate via and PEP8 formatting
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2020-03-06 13:39:46 -08:00 |
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write_driver.py
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write_driver: Allow custom pin names
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2020-02-17 14:25:00 +01:00 |
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write_driver_array.py
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PEP8 updates
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2020-03-31 10:15:46 -07:00 |
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write_mask_and_array.py
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Move write mask vias to center to avoid data pins.
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2019-12-20 11:48:27 -08:00 |
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