mirror of https://github.com/VLSIDA/OpenRAM.git
67 lines
2.6 KiB
Python
67 lines
2.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from tech import drc
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import debug
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import design
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from vector import vector
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from hierarchical_predecode import hierarchical_predecode
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from globals import OPTS
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class hierarchical_predecode3x8(hierarchical_predecode):
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"""
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Pre 3x8 decoder used in hierarchical_decoder.
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"""
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def __init__(self, name, height=None):
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hierarchical_predecode.__init__(self, name, 3, height)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.add_modules()
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self.create_input_inverters()
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connections=[["inbar_0", "inbar_1", "inbar_2", "out_0", "vdd", "gnd"],
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["in_0", "inbar_1", "inbar_2", "out_1", "vdd", "gnd"],
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["inbar_0", "in_1", "inbar_2", "out_2", "vdd", "gnd"],
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["in_0", "in_1", "inbar_2", "out_3", "vdd", "gnd"],
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["inbar_0", "inbar_1", "in_2", "out_4", "vdd", "gnd"],
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["in_0", "inbar_1", "in_2", "out_5", "vdd", "gnd"],
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["inbar_0", "in_1", "in_2", "out_6", "vdd", "gnd"],
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["in_0", "in_1", "in_2", "out_7", "vdd", "gnd"]]
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self.create_and_array(connections)
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def create_layout(self):
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"""
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The general organization is from left to right:
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1) a set of M2 rails for input signals
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2) a set of inverters to invert input signals
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3) a set of M2 rails for the vdd, gnd, inverted inputs, inputs
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4) a set of NAND gates for inversion
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"""
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self.setup_layout_constraints()
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self.route_rails()
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self.place_input_inverters()
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self.place_and_array()
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self.route()
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self.add_boundary()
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self.DRC_LVS()
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def get_and_input_line_combination(self):
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""" These are the decoder connections of the NAND gates to the A,B,C pins """
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combination = [["Abar_0", "Abar_1", "Abar_2"],
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["A_0", "Abar_1", "Abar_2"],
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["Abar_0", "A_1", "Abar_2"],
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["A_0", "A_1", "Abar_2"],
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["Abar_0", "Abar_1", "A_2"],
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["A_0", "Abar_1", "A_2"],
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["Abar_0", "A_1", "A_2"],
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["A_0", "A_1", "A_2"]]
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return combination
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