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9ac894e2effe79eb1da431dc673e833049468071
OpenRAM/compiler/modules
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Jesse Cirimelli-Low 9ac894e2ef update bitcell array trimming
2023-08-15 11:30:16 -07:00
..
__init__.py
Change rom_base_bank name and top pin names
2023-03-30 11:30:50 -07:00
and2_dec.py
Update copyright year
2023-01-28 22:56:27 -08:00
and3_dec.py
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2023-01-28 22:56:27 -08:00
and4_dec.py
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2023-01-28 22:56:27 -08:00
bank.py
Merge branch 'dev' into delay_ctrl
2023-06-05 16:24:48 -07:00
bitcell_1port.py
Update copyright year
2023-01-28 22:56:27 -08:00
bitcell_2port.py
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2023-01-28 22:56:27 -08:00
bitcell_array.py
update bitcell array trimming
2023-08-15 11:30:16 -07:00
bitcell_base_array.py
lvs failures
2023-07-26 02:51:31 -07:00
bitcell_base.py
Update copyright year
2023-01-28 22:56:27 -08:00
capped_replica_bitcell_array.py
change array modules to allow rbl=[0, 0]
2023-03-09 10:23:28 -08:00
col_cap_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
col_cap_bitcell_1port.py
Over-ride build_graph in row/col caps to remove incorrect graph error.
2023-03-01 09:25:56 -08:00
col_cap_bitcell_2port.py
Over-ride build_graph in row/col caps to remove incorrect graph error.
2023-03-01 09:25:56 -08:00
column_decoder.py
Revert pin/net spice object work
2023-08-14 18:44:51 -07:00
column_mux_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
column_mux.py
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2023-01-28 22:56:27 -08:00
control_logic_base.py
remove cs_bar signal bus from all control logics
2023-06-07 15:53:15 -07:00
control_logic_delay.py
add optional guard band to delay chain sizing
2023-07-05 16:34:42 -07:00
control_logic.py
remove cs_bar signal bus from all control logics
2023-06-07 15:53:15 -07:00
delay_chain.py
Update copyright year
2023-01-28 22:56:27 -08:00
dff_array.py
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2023-01-28 22:56:27 -08:00
dff_buf_array.py
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2023-01-28 22:56:27 -08:00
dff_buf.py
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2023-01-28 22:56:27 -08:00
dff_inv_array.py
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2023-01-28 22:56:27 -08:00
dff_inv.py
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2023-01-28 22:56:27 -08:00
dff.py
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2023-01-28 22:56:27 -08:00
dummy_array.py
add dummy mirroring for sky130 dp
2023-08-14 14:25:57 -07:00
dummy_bitcell_1port.py
Update copyright year
2023-01-28 22:56:27 -08:00
dummy_bitcell_2port.py
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2023-01-28 22:56:27 -08:00
dummy_pbitcell.py
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2023-01-28 22:56:27 -08:00
global_bitcell_array.py
add no rbl support to global array
2023-04-05 14:47:15 -07:00
hierarchical_decoder.py
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2023-01-28 22:56:27 -08:00
hierarchical_predecode2x4.py
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2023-01-28 22:56:27 -08:00
hierarchical_predecode3x8.py
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2023-01-28 22:56:27 -08:00
hierarchical_predecode4x16.py
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2023-01-28 22:56:27 -08:00
hierarchical_predecode.py
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2023-01-28 22:56:27 -08:00
internal_base.py
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2023-01-28 22:56:27 -08:00
inv_dec.py
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2023-01-28 22:56:27 -08:00
local_bitcell_array.py
support no rbls in local array
2023-03-09 14:44:05 -08:00
multi_delay_chain.py
add pinout message output
2023-06-25 10:46:58 -07:00
multibank.py
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2023-01-28 22:56:27 -08:00
nand2_dec.py
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2023-01-28 22:56:27 -08:00
nand3_dec.py
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2023-01-28 22:56:27 -08:00
nand4_dec.py
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2023-01-28 22:56:27 -08:00
orig_bitcell_array.py
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2023-01-28 22:56:27 -08:00
pand2.py
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2023-01-28 22:56:27 -08:00
pand3.py
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2023-01-28 22:56:27 -08:00
pand4.py
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2023-01-28 22:56:27 -08:00
pattern.py
add isntance naming templates
2023-08-03 16:24:24 -07:00
pbitcell.py
Revert pin/net spice object work
2023-08-14 18:44:51 -07:00
pbuf_dec.py
column control and address precharge
2023-03-30 11:30:50 -07:00
pbuf.py
Update copyright year
2023-01-28 22:56:27 -08:00
pdriver.py
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2023-01-28 22:56:27 -08:00
pgate.py
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2023-01-28 22:56:27 -08:00
pinv_dec.py
Changes for test generation and simulation
2023-03-30 11:30:50 -07:00
pinv.py
Update copyright year
2023-01-28 22:56:27 -08:00
pinvbuf.py
revert changes to pinvbuf
2023-03-30 11:30:50 -07:00
pnand2.py
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2023-01-28 22:56:27 -08:00
pnand3.py
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2023-01-28 22:56:27 -08:00
pnand4.py
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2023-01-28 22:56:27 -08:00
pnor2.py
Update copyright year
2023-01-28 22:56:27 -08:00
port_address.py
place wl_en pin on wl drivers in absence of rbl_wl driver
2023-06-05 15:26:11 -07:00
port_data.py
fix column mux without rbl start_bit to 0
2023-07-05 13:17:46 -07:00
precharge_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
precharge.py
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2023-01-28 22:56:27 -08:00
ptristate_inv.py
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2023-01-28 22:56:27 -08:00
ptx.py
reoriented cell and added tap cell
2023-03-30 11:30:50 -07:00
pwrite_driver.py
Update copyright year
2023-01-28 22:56:27 -08:00
replica_bitcell_1port.py
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2023-01-28 22:56:27 -08:00
replica_bitcell_2port.py
Update copyright year
2023-01-28 22:56:27 -08:00
replica_bitcell_array.py
reword comments in replica bitcell array module
2023-06-06 14:43:18 -07:00
replica_column.py
trim bitcells and fix replica column excluding
2023-08-10 00:34:16 -07:00
replica_pbitcell.py
Update copyright year
2023-01-28 22:56:27 -08:00
rom_address_control_array.py
more top level routing cleanup
2023-03-30 11:30:50 -07:00
rom_address_control_buf.py
more code cleaning
2023-03-30 11:30:50 -07:00
rom_bank.py
Change OPTS.route_supplies option since there's only one router now
2023-08-02 21:48:29 -07:00
rom_base_array.py
1kb rom DRC clean
2023-03-30 11:30:50 -07:00
rom_base_cell.py
precharge array test passing sky130
2023-03-30 11:30:50 -07:00
rom_column_mux_array.py
rom base passing tests with top level routing
2023-03-30 11:30:50 -07:00
rom_column_mux.py
rom base passing tests with top level routing
2023-03-30 11:30:50 -07:00
rom_control_logic.py
rom base passing tests with top level routing
2023-03-30 11:30:50 -07:00
rom_decoder.py
more code cleaning
2023-03-30 11:30:50 -07:00
rom_poly_tap.py
rom base passing tests with top level routing
2023-03-30 11:30:50 -07:00
rom_precharge_array.py
rom base passing tests with top level routing
2023-03-30 11:30:50 -07:00
rom_precharge_cell.py
precharge array test passing sky130
2023-03-30 11:30:50 -07:00
rom_wordline_driver_array.py
rom base passing tests with top level routing
2023-03-30 11:30:50 -07:00
row_cap_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
row_cap_bitcell_1port.py
Over-ride build_graph in row/col caps to remove incorrect graph error.
2023-03-01 09:25:56 -08:00
row_cap_bitcell_2port.py
Over-ride build_graph in row/col caps to remove incorrect graph error.
2023-03-01 09:25:56 -08:00
sense_amp_array.py
Update copyright year
2023-01-28 22:56:27 -08:00
sense_amp.py
Update copyright year
2023-01-28 22:56:27 -08:00
sram_1bank.py
Change OPTS.route_supplies option since there's only one router now
2023-08-02 21:48:29 -07:00
sram_multibank_template.v
Shrunk address register in multibank verilog
2022-07-28 15:03:41 -07:00
sram_multibank.py
Update copyright year
2023-01-28 22:56:27 -08:00
template.py
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2023-01-28 22:56:27 -08:00
tri_gate_array.py
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2023-01-28 22:56:27 -08:00
tri_gate.py
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2023-01-28 22:56:27 -08:00
wordline_buffer_array.py
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2023-01-28 22:56:27 -08:00
wordline_driver_array.py
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2023-01-28 22:56:27 -08:00
wordline_driver.py
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2023-01-28 22:56:27 -08:00
write_driver_array.py
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2023-01-28 22:56:27 -08:00
write_driver.py
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2023-01-28 22:56:27 -08:00
write_mask_and_array.py
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2023-01-28 22:56:27 -08:00