luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,646 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

3799 Commits

Author SHA1 Message Date
Bugra Onal 93182d525d Added sky130 golden spice file 2023-07-20 15:20:15 -07:00
Bugra Onal 5b1544ad45 Sky130 tests will use 1 spare row and col 2023-07-20 15:18:32 -07:00
Bugra Onal 78e5b60380 Fix fake_sram bit sizes 2023-07-20 10:43:09 -07:00
mrg f800b50813 Fix wrong bit size in fake_sram. 2023-07-20 10:11:49 -07:00
Bugra Onal 6751442d35 account for spare cols in char 2023-07-19 16:09:28 -07:00
Sam Crow 2051f54f70 Merge branch 'STA-refactor' into dev 2023-07-19 15:14:20 -07:00
Bugra Onal 0b2196a3e4 cleaned logs 2023-07-19 14:50:49 -07:00
Sam Crow 6e3e964c12 cleanup net_spice docstrings 2023-07-19 12:45:41 -07:00
Sam Crow f41537b508 Merge branch 'char' into STA-refactor 2023-07-19 12:35:22 -07:00
Sam Crow 2ced895b32 add BIAS pin type back to valid types 2023-07-19 12:15:47 -07:00
Sam Crow c67fdd8bd8 fix insts typo 2023-07-19 12:15:21 -07:00
Bugra Onal d53353b5be Merge branch 'dev' into char 2023-07-19 12:06:34 -07:00
Bugra Onal 9fa25690ce Added pins for spare_cols 2023-07-19 11:35:09 -07:00
Sam Crow 2b9e70d318 remove line ending whitespace from comment 2023-07-19 10:51:19 -07:00
Sam Crow bfabe64f33 fix pin/net dictionary deepcopy-ing 2023-07-18 16:14:38 -07:00
Sam Crow 09aa395174 cast pins dict to list 2023-07-18 16:13:29 -07:00
Sam Crow 5907cbb3e2 remove pins overwrite from contact class 2023-07-18 16:12:42 -07:00
Sam Crow aa71785bd5 fix circular import with pin and net 2023-07-18 11:28:30 -07:00
Sam Crow 478c76c1ca get connections from spice objects in instances 2023-07-18 10:50:50 -07:00
Sam Crow 8a441bc68b Merge branch 'dev' into STA-refactor 2023-07-17 16:35:31 -07:00
Sam Crow 45b88889e4 use pin and net objects in connect_inst 2023-07-17 16:04:56 -07:00
Sam Crow d0339a90e6 change spice_nets and spice_pins to dicts 2023-07-17 15:36:57 -07:00
Sam Crow e15feb2361 change nets list to dictionary 2023-07-17 15:36:22 -07:00
Sam Crow 7581df2255 change pins to OrderedDict 2023-07-17 15:22:35 -07:00
Sam Crow c8c43f75d9 add spice nets and a way to connect them to pins 2023-07-14 16:18:10 -07:00
Sam Crow 146efc5070 implement pin_spice object 2023-07-13 16:45:05 -07:00
Bugra Onal 833d4c12a6 skip 30_tests for sky130 2023-07-11 10:15:26 -07:00
Sam Crow 89d8441108 Merge branch 'dev' into delay_ctrl 2023-07-10 14:31:26 -07:00
Samuel Crow 042a3ed14f
skip non-scmos delay control tests for now 2023-07-10 14:28:19 -07:00
Bugra Onal ed0c93ba55 Only add drc errors from compiler 2023-07-10 14:05:44 -07:00
Bugra Onal eddc9af45b Merge branch 'dev' into char 2023-07-10 13:55:50 -07:00
Sam Crow 4e649aad6b fix typo bug in spice comments code 2023-07-10 13:21:24 -07:00
Bugra Onal 0ad619f04c Added bl, sen and cell format options 2023-07-10 12:32:58 -07:00
Bugra Onal 7220e0a483 sim_exe will be found everytime with func and char 2023-07-07 12:39:19 -07:00
Sam Crow b91c628acf Merge branch 'dev' into delay_ctrl 2023-07-06 08:45:03 -07:00
Sam Crow 468c972acb add optional guard band to delay chain sizing 2023-07-05 16:34:42 -07:00
Sam Crow d65ccfcc95 fix column mux without rbl start_bit to 0 2023-07-05 13:17:46 -07:00
Sam Crow b4a9784835 model vth delay swing delay 2023-07-05 12:17:48 -07:00
Sam Crow 5235cf9667 model p_en and wl_en delays in delay chain sizing 2023-07-03 17:02:11 -07:00
Sam Crow e1865083d7 incomplete work on improved delay modeling 2023-06-29 14:44:42 -07:00
Sam Crow 91694fdae3 add fixme note for unit conversion 2023-06-28 14:05:42 -07:00
Sam Crow 28ea93bd0a convert 1-indexing to 0-indexing 2023-06-25 11:03:10 -07:00
Sam Crow 006eacd6d0 add pinout message output 2023-06-25 10:46:58 -07:00
Sam Crow 8992c0fb68 first approximation of delay values 2023-06-20 16:22:03 -07:00
Sam Crow dbc9de6c9a implement relationship between delay pinouts 2023-06-14 17:10:07 -07:00
Gary Mejia 9a36cce7ae Fixed formatting on all files 2023-06-14 12:28:36 -07:00
Gary Mejia b9e61f346a Merge branch 'dev' into openROM-verilogoutput 
To test recent changes with ROM verilog output
 2023-06-14 12:26:07 -07:00
Gary Mejia a3284e8b47 Fixed module from writing syntax issues 2023-06-13 17:30:38 -07:00
Sam Crow bf516a927d add skeleton for delay chain sizing 2023-06-13 13:44:32 -07:00
Sam Crow fee90283b9 add spacing and a comment 2023-06-12 16:56:44 -07:00