Fix wrong bit size in fake_sram.

2026-09-03 16:31:08 +02:00 · 2023-07-20 10:11:49 -07:00
parent f246e5a521
commit f800b50813
1 changed files with 1 additions and 1 deletions
@@ -89,7 +89,7 @@ class fake_sram(sram_config):
            self.pins.extend(['dout{0}[{1}]'.format(port, bit)
                              for bit in range(self.word_size + self.num_spare_cols)])
            self.pins.extend(['addr{0}[{1}]'.format(port, bit)
-                              for bit in range(self.word_size)])
+                              for bit in range(self.addr_size)])

            self.pins.extend(['csb{}'.format(port)])