mirror of https://github.com/VLSIDA/OpenRAM.git
use pin and net objects in connect_inst
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d0339a90e6
commit
45b88889e4
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@ -285,9 +285,17 @@ class instance(geometry):
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return new_pins
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def connect_spice_pins(self, nets_list):
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for i in range(len(self.pins)):
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self.pins[i].set_inst_net(nets_list[i])
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nets_list[i].connect_pin(self.pins[i])
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"""
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add the connection between instance pins and module nets
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to both of their respective objects
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nets_list must be the same length as self.spice_pins
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"""
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debug.check(len(self.spice_pins) == len(nets_list),
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"must provide list of nets the same length as pin list\
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when connecting an instance")
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for i in range(len(self.spice_pins)):
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self.spice_pins[i].set_inst_net(nets_list[i])
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nets_list[i].connect_pin(self.spice_pins[i])
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def calculate_transform(self, node):
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#set up the rotation matrix
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@ -192,7 +192,7 @@ class spice():
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# Order the arguments if the hard cell has a custom port order
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ordered_args = self.get_ordered_inputs(args)
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if (check and num_pins != num_args):
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if (num_pins != num_args):
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if num_pins < num_args:
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mod_pins = spice_pins + [""] * (num_args - num_pins)
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arg_pins = ordered_args
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@ -13,7 +13,7 @@ class pin_spice:
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"""
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A class to represent a spice netlist pin.
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mod is the parent module that created this pin.
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mod_net is the net object of this pin's parent module.
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mod_net is the net object of this pin's parent module. It must have the same name as the pin.
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inst is the instance this pin is a part of, if any.
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inst_net is the net object from mod's nets which connects to this pin.
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"""
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@ -45,6 +45,9 @@ class pin_spice:
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self.inst = inst
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def set_inst_net(self, net):
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debug.check(self.inst_net is None,
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"pin {} is already connected to net {} so it cannot also be connected to net {}\
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".format(self.name, self.inst_net.name, net.name))
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debug.check(isinstance(net, net_spice), "net must be a net_spice object")
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self.inst_net = net
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