 Bin Wu
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e4070ddad8
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into pex_fix_v2
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2019-07-10 03:09:12 -07:00 |
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 jsowash
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5258016c9f
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Changed location of port for din_reg.
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2019-07-06 12:27:24 -07:00 |
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jsowash
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6fe78fe04a
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Removed begin end for Verilog without wmask.
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2019-07-06 11:29:34 -07:00 |
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jsowash
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24bfaa3b76
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Added write_size to test 16 and added a newline to Verilog with no wmask for test 25.
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2019-07-05 15:55:03 -07:00 |
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jsowash
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ad9193ad5a
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Verified 1rw mask writing and changed verilog.py accordingly.
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2019-07-05 15:08:59 -07:00 |
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jsowash
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f29631695c
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Finished merge
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2019-07-05 11:43:31 -07:00 |
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jsowash
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150259e2ba
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Added write_size to control_logic_r parameters.
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2019-07-05 11:40:02 -07:00 |
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 mrg
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bfe4213fce
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Port address added to entire SRAM.
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2019-07-05 09:44:42 -07:00 |
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mrg
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4c6556f1bc
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Add port address module
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2019-07-05 09:04:48 -07:00 |
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mrg
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c0f9cdbc12
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Create port address module
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2019-07-05 09:03:52 -07:00 |
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mrg
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dd62269e0b
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Some cleanup
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2019-07-05 08:18:58 -07:00 |
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jsowash
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02a0cd71ac
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fixed merge conflict
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2019-07-04 11:14:32 -07:00 |
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jsowash
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125112b562
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Added wmask flip flop. Need work on placement still.
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2019-07-04 10:34:14 -07:00 |
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mrg
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3176ae9d50
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Fix pnand2 height in bank select. Unsure how it passed before.
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2019-07-03 15:12:22 -07:00 |
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Matt Guthaus
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f914ab0ece
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Re-enable replica tests
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2019-07-03 14:57:47 -07:00 |
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mrg
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9204f85bb0
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Merge branch 'rbl_revamp' of github.com:VLSIDA/PrivateRAM into rbl_revamp
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2019-07-03 14:54:10 -07:00 |
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mrg
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ae9dbe203d
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Add freepdk45 dummy cells
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2019-07-03 14:53:44 -07:00 |
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Matt Guthaus
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0cb86b8ba2
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Exclude new precharge in graph build
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2019-07-03 14:46:20 -07:00 |
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mrg
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0fbfa924f7
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Add other SCMOS dummy cells
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2019-07-03 14:28:12 -07:00 |
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mrg
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8b0b2e2817
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Merge branch 'dev' into rbl_revamp
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2019-07-03 14:05:28 -07:00 |
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mrg
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70c83f20b6
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Fixes to pass unit tests.
Skip replica tests until freepdk45 cells are made.
Revert to previous control and row addr dff placement.
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2019-07-03 13:37:56 -07:00 |
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mrg
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bc4a3ee2b7
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New port_data module works in SCMOS
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2019-07-03 13:17:12 -07:00 |
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jsowash
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474ac67af5
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Added optional write_size and wmask.
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2019-07-03 10:14:15 -07:00 |
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mrg
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244604fb0d
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Data port module working by itself.
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2019-07-02 15:35:53 -07:00 |
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mrg
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2abe859df1
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Fix shared bank offset.
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2019-07-01 16:29:59 -07:00 |
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jsowash
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67c6cdf3bb
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Fixed error where word_size was compared to num_words and added write_size to control_logic.py
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2019-07-01 15:51:40 -07:00 |
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Bin Wu
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9ce968b446
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megre with dev changes
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2019-06-30 00:50:18 -07:00 |
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Bin Wu
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1fcb20f846
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clean pex test based on feedback
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2019-06-30 00:16:04 -07:00 |
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jsowash
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242771f710
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Merge branch 'dev' into add_wmask
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2019-06-28 15:44:27 -07:00 |
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jsowash
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1f76afd294
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Begin wmask functionality. Added wmask to verilog file and config parameters.
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2019-06-28 15:43:09 -07:00 |
|
 Hunter Nichols
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3f5b60856a
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Fixed key error with analytical delay of write ports.
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2019-06-28 13:49:04 -07:00 |
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Hunter Nichols
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ce7e320505
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Undid change to add bitcell as input to array mod.
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2019-06-25 18:26:13 -07:00 |
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Hunter Nichols
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4e08e2da87
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Merged and fixed conflicts with dev
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2019-06-25 16:55:50 -07:00 |
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Hunter Nichols
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4f3340e973
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Cleaned up graph additions to characterizer.
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2019-06-25 16:37:35 -07:00 |
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Hunter Nichols
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33c17ac41c
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Moved manual delay chain declarations from tech files to options.
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2019-06-25 15:45:02 -07:00 |
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Bin Wu
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8e5fa7c7ae
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fix the run_pex function for calibre
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2019-06-25 15:06:07 -07:00 |
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Hunter Nichols
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04ce3d5f45
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Split control logic into different tests to avoid factory errors.
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2019-06-25 14:55:28 -07:00 |
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Bin Wu
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9ef2616d41
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into pex_fix_v2
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2019-06-25 11:28:04 -07:00 |
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Bin Wu
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3f3ee9b885
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add pex function for magic and openram test
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2019-06-25 11:24:25 -07:00 |
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jsowash
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3bd69d2759
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Added functionality to express polygons in LEF files.
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2019-06-25 09:20:00 -07:00 |
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Bin Wu
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91febec3a2
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add hspice and ngspice pex tests
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2019-06-25 09:19:37 -07:00 |
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Matt
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d22d7de195
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Reapply jsowash update without spice model file
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2019-06-24 08:59:58 -07:00 |
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mrg
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4523a7b9f6
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Replica bitcell array working
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2019-06-19 16:03:21 -07:00 |
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Hunter Nichols
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2b07db33c8
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Added bitcell as input to array, but there are DRC errors now.
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2019-06-17 15:31:16 -07:00 |
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mrg
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5c4df2410e
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Fix dummy row LVS issue
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2019-06-14 15:06:04 -07:00 |
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mrg
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d35f180609
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Add dummy row
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2019-06-14 15:05:14 -07:00 |
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mrg
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3c3456596a
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Add replica row with dummy cells.
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2019-06-14 14:38:55 -07:00 |
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mrg
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b67f06a65a
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Add replica column for inclusion in replica bitcell array
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2019-06-14 12:15:16 -07:00 |
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mrg
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d8baa5384d
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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Matt Guthaus
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6e044b776f
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Merge branch 'pep8_cleanup' into dev
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2019-06-14 08:47:10 -07:00 |
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