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OpenRAM
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115 Commits

Author SHA1 Message Date
Joey Kunzler 7a602b75a4 keep dev routing changes to hierarchy_layout 2020-06-03 12:54:15 -07:00
Joey Kunzler 84021c9ccb merge conflict 2 - port data 2020-06-02 16:32:08 -07:00
Joey Kunzler 001bf1b827 merge conflict - port data 2020-06-02 14:15:39 -07:00
mrg 620604603c Fixed offset jogs 2020-06-02 10:08:37 -07:00
Joey Kunzler b39579c109 temp drc fix for regression tests 2020-06-01 20:55:15 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00
Joey Kunzler 9a6b38b67e merge conflict 2020-05-26 16:03:36 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg dd73afc983 Changes to allow decoder height to be a 2x multiple of bitcell height. 
Convert to use li layer in pgates.
Fix multifinger devices with li layers.
Simplify wordline driver input routing.
Fix power pin direction option update.
PEP8 cleanup
Changes to simplify metal preferred directions and pitches.
Split of control logic tests.
 2020-05-10 06:56:22 -07:00
Joey Kunzler e642b8521b increase col_mux bitline spacing to fix cyclic vcg 2020-05-06 13:02:33 -07:00
Joey Kunzler 91dbbed9ba added horizontal trunk route edit to vertical trunk route 2020-05-05 12:18:26 -07:00
Joey Kunzler 1b6634bb97 port data routing fix 2020-04-29 15:48:15 -07:00
Joey Kunzler 0bae652be9 fix merge conflicts 2020-04-23 11:51:46 -07:00
mrg dfbf6fe45c Default is to use preferred layer directions 2020-04-20 15:33:53 -07:00
mrg 7f65176908 Configured bitline directions into prot_data 2020-04-20 14:23:40 -07:00
Joey Kunzler 7920b0cef9 m3 min area rounding fix 2020-04-17 12:36:48 -07:00
mrg 94eb2afa36 Change to callable DRC rule. Use bottom coordinate for bus offsets. 2020-04-15 15:29:55 -07:00
mrg 9907daaffa Min area only for multiple layers 2020-03-26 13:05:02 -07:00
mrg d2c97d75a7 Add well contact and min area to power pin of precharge 2020-03-26 11:49:32 -07:00
mrg ad98137cd4 Merge branch 'dev' into tech_migration 2020-03-05 14:18:06 -08:00
mrg 287a31f598 Precharge updates. 
Enable different layers for bitlines.
Jog bitlines to fit precharge transistors for close proximity bitlines.
PEP8 cleanup.
 2020-03-04 17:39:11 -08:00
Joey Kunzler d7529ce526 Vdd/gnd via stacks now use perferred directions, added cell property to override 2020-03-04 17:05:19 -08:00
mrg 7ba9e09e12 Incomplete precharge layer decoupling 2020-03-04 22:23:05 +00:00
mrg 35110a4453 Improve debug of non-manhattan error 2020-02-25 00:34:28 +00:00
Bastian Koppelmann 9749c522d1 tech: Make power_grid configurable 
this is the first step to allow engineers, porting technologies, more room
for routing their handmade cells.

For now, we don't allow the specification of power_grids where the lower layer
prefers to be routed vertically. This is due to the router not
connecting some pins properly in that case.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 12:06:34 +01:00
Bastian Koppelmann 988df8ebb9 hierarchy_layout: Add methods to create via stacks 
this allows us to simplify add_power_pin() and gives a clean
API to create vias through multiple layers.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 11:47:32 +01:00
mrg 877ea53b7f Fix conflicting boundary name 2020-01-24 21:24:44 +00:00
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
mrg 262782cba0 Remove print, fix compare 2020-01-16 19:27:39 +00:00
Matthew Guthaus bec12f5b94 Cleanup. 2019-12-23 21:16:08 +00:00
Matt Guthaus 9e8b03d6c2 Merge branch 'dev' into tech_migration 2019-12-19 16:23:22 -08:00
Matt Guthaus b7d78ec2ec Fix ptx active contact orientation to non-default M1 direction. 2019-12-19 12:54:10 -08:00
Bastian Koppelmann de6b207798 hierachy_layout: Move number of via arg to add_power_pins() 
this allows custom modules to state how many vias they need
for power rails.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-18 17:33:43 +01:00
Matt Guthaus c025ce6356 Add li to preferred direction 2019-12-17 14:06:23 -08:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Matthew Guthaus 5af22b79e2 Only add boundary for if there's a DRC stdc layer 2019-12-06 02:17:58 +00:00
Matthew Guthaus 3deeaf7164 Decrease verbosity of boundary layer 2019-12-05 23:33:23 +00:00
Matthew Guthaus 7397f110c5 Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00
Matt Guthaus 69bb245f28 Updates to gdsMill/tech layers 
Create active and poly contact types.
Define standard cell boundary option.
DataType and PurposeLayer are the same. Text must have type 0.
Remove vector from vlsiLayout. More debug in reader.
 2019-12-04 16:12:53 -08:00
Matthew Guthaus c4cf8134fe Undo changes for config expansion. Change unit tests to use OPENRAM_HOME. 2019-11-15 18:47:59 +00:00
Matt Guthaus 38213d998f Add separate layer and purpose pairs to tech layers. 2019-10-25 10:03:25 -07:00
Matt Guthaus 7fe9e5704d Convert vcg and nets to ordered dict 2019-08-29 16:06:34 -07:00
Matt Guthaus bdf29c3a26 Fix non-preferred route width again. This time it is likely right. 2019-08-22 13:57:14 -07:00
Matt Guthaus afaa946f9c Fix width of non-preferred trunk wire 2019-08-22 12:03:38 -07:00
Matt Guthaus 2ffdfb18a4 Fix trunks less than a pitch in channel route 2019-08-21 17:11:02 -07:00
Matt Guthaus 9ada9a7dfa Fix pitch in channel router to support M3/M4. 2019-08-21 15:32:49 -07:00
mrg c0f9cdbc12 Create port address module 2019-07-05 09:03:52 -07:00
mrg 4523a7b9f6 Replica bitcell array working 2019-06-19 16:03:21 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00