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OpenRAM
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166 Commits

Author SHA1 Message Date
jsowash 858fbb062d Placed wmask dff and added connections for wmask pins. 2019-08-14 11:45:22 -07:00
Matt Guthaus 8d6a4c74e7 Merge branch 'dev' into control_fix 2019-08-10 13:07:30 -07:00
Matt Guthaus 34d28a19e6 Connect wl_en in all ports to bank. 2019-08-10 12:30:23 -07:00
Hunter Nichols d273c0eef5 Merge branch 'dev' into analytical_cleanup 2019-08-08 13:20:27 -07:00
Hunter Nichols 3c44ce2df6 Replaced analytical characterization with graph implementation. Removed most analytical delay functions used by old chacterizer. 2019-08-08 02:33:51 -07:00
Matt Guthaus d36f14b408 New control logic, netlist only working 2019-08-07 17:14:33 -07:00
Matt Guthaus ae46a464b9 Undo delay changes. Fix bus order for DRC. 2019-08-06 17:17:59 -07:00
Matt Guthaus a2f81aeae4 Combine rbl_wl and wl_en. Size p_en_bar slower than wl_en. 2019-08-06 16:29:07 -07:00
Matt Guthaus 8771ffbfed Fix bug to add all p_en_bar to banks 2019-08-01 12:28:21 -07:00
Matt Guthaus ff64e7663e Add p_en_bar to write ports as well 2019-08-01 12:21:43 -07:00
Matt Guthaus 0c5cd2ced9 Merge branch 'dev' into rbl_revamp 2019-07-26 18:01:43 -07:00
Matt Guthaus fb60b51c72 Add check bits. Clean up logic. Move read/write bit check to next cycle. 2019-07-24 16:57:04 -07:00
Matt Guthaus 3df8abd38c Clean up. Split class into own file. 2019-07-24 08:15:10 -07:00
Matt Guthaus 07401fc6ea Make control bus routing offset consistent 2019-07-23 09:39:28 -07:00
jsowash 0a5461201a Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used. 2019-07-19 14:58:37 -07:00
jsowash 45cb159d7f Connected wmask in the spice netlist. 2019-07-19 13:17:55 -07:00
mrg b546ecce2c Check 2 ports only for layout. 2019-07-16 14:11:54 -07:00
mrg 12fa36317e Cleanup unit test. Fix s_en control bug for r-only. 2019-07-16 13:51:31 -07:00
mrg 2f55911604 Simplify column decoder placement. 2019-07-16 11:55:25 -07:00
mrg bea07c2319 SRAM with RBL integration in array. 2019-07-16 09:04:58 -07:00
mrg e550d6ff10 Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
mrg a189b325ed Merge remote-tracking branch 'origin/dev' into rbl_revamp 2019-07-12 11:10:07 -07:00
mrg 043018e8ba Functional tests working with new RBL. 2019-07-12 08:42:36 -07:00
mrg 0b13225913 Single banks working with new RBL 2019-07-11 14:47:27 -07:00
mrg b841fd7ce3 Replica bitcell array with arbitrary RBLs working 2019-07-10 15:56:51 -07:00
mrg 9dab0be737 Single bank working with replica array. 2019-07-05 13:44:29 -07:00
mrg b9d993c88b Add dummy bitcell module. 
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
 2019-07-05 12:58:52 -07:00
jsowash f29631695c Finished merge 2019-07-05 11:43:31 -07:00
mrg bfe4213fce Port address added to entire SRAM. 2019-07-05 09:44:42 -07:00
mrg c0f9cdbc12 Create port address module 2019-07-05 09:03:52 -07:00
jsowash 02a0cd71ac fixed merge conflict 2019-07-04 11:14:32 -07:00
Matt Guthaus 0cb86b8ba2 Exclude new precharge in graph build 2019-07-03 14:46:20 -07:00
mrg 8b0b2e2817 Merge branch 'dev' into rbl_revamp 2019-07-03 14:05:28 -07:00
mrg bc4a3ee2b7 New port_data module works in SCMOS 2019-07-03 13:17:12 -07:00
mrg 244604fb0d Data port module working by itself. 2019-07-02 15:35:53 -07:00
mrg 2abe859df1 Fix shared bank offset. 2019-07-01 16:29:59 -07:00
jsowash 242771f710 Merge branch 'dev' into add_wmask 2019-06-28 15:44:27 -07:00
jsowash 1f76afd294 Begin wmask functionality. Added wmask to verilog file and config parameters. 2019-06-28 15:43:09 -07:00
Hunter Nichols ce7e320505 Undid change to add bitcell as input to array mod. 2019-06-25 18:26:13 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
mrg 4523a7b9f6 Replica bitcell array working 2019-06-19 16:03:21 -07:00
Hunter Nichols 2b07db33c8 Added bitcell as input to array, but there are DRC errors now. 2019-06-17 15:31:16 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
mrg fc12ea24e9 Add boundary to every module and pgate for visual debug. 2019-06-03 15:27:37 -07:00
mrg 301f032619 Remove +1 to induce error. 2019-05-31 10:55:17 -07:00
mrg d789f93743 Add debug runner during individual tests. 2019-05-31 10:51:42 -07:00
Hunter Nichols 099bc4e258 Added bitcell check to storage nodes. 2019-05-20 18:35:52 -07:00
Hunter Nichols d8617acff2 Merged with dev 2019-05-15 18:48:00 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00