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OpenRAM
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4,932 Commits 5 Branches 63 Tags 79 MiB
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30 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low cb7f117daa squash commits 2026-04-22 01:33:47 -07:00
Jesse Cirimelli-Low 515591a422 dual port rba lvs clean again with cell library changes 2026-04-14 14:48:26 -07:00
Jesse Cirimelli-Low ffcbd51019 technology switching working 2026-03-17 11:44:20 -07:00
Jesse Cirimelli-Low 53d53ec271 checkpoint from tt submission 2026-01-14 12:08:26 -08:00
Jesse Cirimelli-Low 5a74605117 single port fixes 2025-09-12 11:25:03 -07:00
Jesse Cirimelli-Low 4ce6e0538b fix col_cap array for dummu compatability ...bitcells next 2025-03-06 02:05:43 -08:00
Jesse Cirimelli-Low f3c1c5fbb2 Merge branch 'singleport_refactor' into array_gen 2025-02-24 23:26:28 -08:00
mrg 3f1f58065d Add nand4 leakage to sky130 tech 2024-07-01 10:14:43 -07:00
mole99 85e242fa27 Add gf180mcu ROM example 2024-02-03 11:31:58 +01:00
Jesse Cirimelli-Low 788d7e5474 fix VPB/VNB pins not being found 2023-10-31 18:07:35 -07:00
Jesse Cirimelli-Low 0cba6a6050 single port sky130 crba passing lvs 2023-08-30 20:59:02 -07:00
Jesse Cirimelli-Low ba51149dce placement working for sp capped rba, need fix rowcap patterns 2023-08-26 18:54:07 -07:00
Sam Crow f1d91efebd fix single port by using existing custom modules 2023-03-03 14:17:57 -08:00
mrg 1db9881ce7 Add sky130 corners to tech file. 2023-03-01 09:26:16 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Jesse Cirimelli-Low 3b02a8846d sky130 rba passing :) 2022-09-12 16:07:00 -07:00
Jesse Cirimelli-Low 11fa0777e8 add flatglob to tech file; sky130 replica col lvs working 2022-08-22 15:30:11 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
Jesse Cirimelli-Low 98fe4c74a4 colend fixes in progress 2022-06-15 22:34:21 -07:00
mrg 25fa0a8de3 Fix missing cell syntax error. 2022-05-19 14:53:17 -07:00
mrg bdd334bce9 Add layer and directions to pbitcell 2022-05-16 16:11:13 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
Jesse Cirimelli-Low 8d9166a01b only rba lvs errors is colend body extraction 2021-12-29 12:43:02 -08:00
Jesse Cirimelli-Low 9e85d17fbe merge rbc lvs fixes 2021-12-23 21:21:10 -08:00
mrg 02364c6cdf Add klayout option in config. No tool specific LVS libs 2021-12-17 10:29:17 -08:00
mrg d555e67fb1 Add initial sky130 LVS/DRC rules. 2021-12-17 10:27:13 -08:00
Jesse Cirimelli-Low 8879820af4 replica col lvs fix 2021-12-15 14:19:52 -08:00
mrg fa2232fc11 Initial commit of sky130 config files 2021-10-04 15:16:28 -07:00