727 Commits

Include renames

Author	SHA1	Message	Date
mrg	4e7e0c5954	Skip test in sky130	2020-06-29 15:28:16 -07:00
mrg	af4ed3dd6e	Skip riscv func test for time sake	2020-06-26 06:50:45 -07:00
mrg	76e5389c33	Change riscv func test name	2020-06-25 17:43:17 -07:00
mrg	9eb1b500ea	Skip phys riscv test	2020-06-25 17:31:23 -07:00
mrg	7220b23402	Add riscv unit tests	2020-06-25 15:34:18 -07:00
mrg	b3d1161957	Add u+x permissions to new tests	2020-06-24 08:19:25 -07:00
Joey Kunzler	22ed725a35	made 1rw_1r tests for write driver and wmask, fixed typo in portdata_wmask_1rw_1r_test	2020-06-23 18:16:14 -07:00
mrg	22c821f5d8	Change port_address test to 256 for riscv	2020-06-23 15:40:00 -07:00
mrg	1a528f9739	Skip and4_dec test	2020-06-23 10:08:28 -07:00
mrg	92fc30005c	Use factory in and_dec tests	2020-06-22 16:55:49 -07:00
mrg	5872f553e1	Rename tests for consistency	2020-06-19 08:53:35 -07:00
mrg	239b3ea007	Make wmask test a 1rw/1r	2020-06-19 08:49:48 -07:00
mrg	a862cf3cb2	Test more single level col mux configs	2020-06-15 10:17:54 -07:00
mrg	6c04166876	Update port data wmask tests	2020-06-15 06:05:05 -07:00
mrg	9930b5f3f6	Do not run tapless unit tests	2020-06-14 14:18:25 -07:00
mrg	33a32101c9	DRC and LVS fixes for pinv_dec	2020-06-12 15:23:51 -07:00
mrg	dff28a9997	Merge branch 'tech_migration' into dev	2020-06-10 17:09:05 -07:00
mrg	fdf92d0da1	Rename test 14	2020-06-10 16:41:26 -07:00
mrg	469cd260b9	Change bitcell array name to match	2020-06-10 14:54:20 -07:00
mrg	f2c45a230e	Add new replica column test. Add more skip tests.	2020-06-10 11:00:00 -07:00
mrg	10be2d08b5	Full path to skip tests file	2020-06-10 10:23:05 -07:00
mrg	c119e60e79	Add more s8 skip tests	2020-06-10 10:14:52 -07:00
mrg	d4fc88124a	Rename dff_buf test	2020-06-09 17:18:19 -07:00
mrg	14782914b3	Remove vertical pand gates	2020-06-09 16:40:59 -07:00
mrg	c6b875146d	Use local skip file	2020-06-09 16:33:59 -07:00
mrg	fd49d3ed6a	Add tech specific skip tests for making new techs.	2020-06-09 16:09:15 -07:00
mrg	580b0601b5	Unskip 20_psram_1bank_4mux_1rw_1r_test	2020-06-09 16:04:39 -07:00
mrg	a28e747a02	Fix precharge offset. Move well rules to design class.	2020-06-09 15:28:50 -07:00
Aditi Sinha	c39c0efd39	Updated spare col tests	2020-06-08 16:38:18 +00:00
Aditi Sinha	d5041afebc	Merge branch 'dev' into bisr	2020-06-07 16:27:25 +00:00
mrg	5514996708	Auto-generate port dependent cell names.	2020-06-05 15:09:22 -07:00
mrg	4fef632dce	Fix syntax error	2020-06-05 12:13:41 -07:00
mrg	a62b85a6b1	Update mirroring in port_data for bitcell mirrored arrays	2020-06-05 11:29:31 -07:00
mrg	2e7f9395f2	Rename 05 test to 14	2020-06-05 09:57:16 -07:00
mrg	68ffb94d2e	Rename 05 test to 14	2020-06-05 09:55:57 -07:00
mrg	fb3acae908	PEP8 format testutils.	2020-06-05 09:44:30 -07:00
mrg	2fcecb7227	Variable zjog. 512 port address test. s8 port address working.	2020-06-04 16:01:32 -07:00
mrg	77c95b28da	Rename precharge test	2020-06-03 16:39:46 -07:00
mrg	4183638f03	Align precharge bitlines with col mux	2020-06-03 16:05:57 -07:00
mrg	4bc1e9a026	Fix the bitline spacing in the column mux to a constant.	2020-06-03 15:47:03 -07:00
mrg	e93f3f1d2e	Add 1rw_1r tests	2020-06-03 14:30:15 -07:00
mrg	b78166c044	Merge branch 'dev' into tech_migration	2020-06-03 14:08:22 -07:00
Joey Kunzler	6430aad857	Merge branch 'dev' into s8_update	2020-06-03 11:53:33 -07:00
mrg	38f5e8b865	Add col mux tests for multiport	2020-06-03 10:01:02 -07:00
Aditi Sinha	eb0c595dbe	SRAM layout and functional tests with spare cols	2020-06-03 12:31:30 +00:00
mrg	34209dac3d	A port option for correct mirroring in port_data.	2020-06-02 16:50:07 -07:00
Joey Kunzler	84021c9ccb	merge conflict 2 - port data	2020-06-02 16:32:08 -07:00
Joey Kunzler	001bf1b827	merge conflict - port data	2020-06-02 14:15:39 -07:00
mrg	fce8e878b9	Add port to col mux and simplify route with computation to fix mirror bug.	2020-06-02 13:57:41 -07:00
mrg	b3b03d4d39	Hard cells can accept height parameter too.	2020-06-01 16:46:00 -07:00