 mrg
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bec948dcc3
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Fix error in when to add vias for array power
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2020-06-29 15:28:55 -07:00 |
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mrg
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4e7e0c5954
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Skip test in sky130
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2020-06-29 15:28:16 -07:00 |
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Matt Guthaus
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e97644c424
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Only do reverse lookup on valid interconnect layers since layer numbers can be shared.
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2020-06-29 14:42:24 -07:00 |
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mrg
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07d0f3af8e
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Only copy end-cap pins to the bank level
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2020-06-29 11:46:59 -07:00 |
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mrg
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1bc0775810
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Only add pins to periphery
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2020-06-29 10:03:24 -07:00 |
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mrg
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5f3a45b91b
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Compute bus size separately for ports
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2020-06-29 05:54:30 -07:00 |
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mrg
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47f541df0e
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Fix bugs in channel route.
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2020-06-28 16:58:28 -07:00 |
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mrg
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5285468380
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All bitcells need a vdd/gnd pin
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2020-06-28 15:09:47 -07:00 |
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mrg
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751eab202b
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Move row addr flops away from predecode. Route spare wen separately on lower layer.
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2020-06-28 15:06:29 -07:00 |
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mrg
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20324ab3c4
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Revert write driver pin spacing
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2020-06-28 14:55:58 -07:00 |
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mrg
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051c8d8697
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Only add bitcells to dummy and replica rows and columns (the perimeter)
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2020-06-28 14:47:54 -07:00 |
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mrg
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709535f90f
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Fix right perimeter pin coordinate bug
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2020-06-28 14:47:17 -07:00 |
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mrg
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225fc69420
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Use preferred routing direction
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2020-06-28 14:29:12 -07:00 |
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mrg
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4df02dad67
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Move spare wen_dff to the right by spare columns
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2020-06-28 14:28:43 -07:00 |
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mrg
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bc3de9db05
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Pick correct side of pin in channel route.
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2020-06-28 14:28:18 -07:00 |
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mrg
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e774314add
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Separate write driver pins by M3 pitch
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2020-06-28 14:14:48 -07:00 |
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mrg
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0c9f52e22f
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Realign col decoder and control by 1/4 so metal can pass over
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2020-06-28 07:15:06 -07:00 |
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mrg
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66ea559209
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Use channel for dffs all at once
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2020-06-27 08:23:12 -07:00 |
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mrg
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c10a6a29c0
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Simplify precharge pin layer
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2020-06-27 08:22:16 -07:00 |
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mrg
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609aa98c8b
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Move write mask pin to left of cell to avoid sense amp
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2020-06-27 08:21:53 -07:00 |
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mrg
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2bd498c39c
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Change precharge layer to m3
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2020-06-27 08:21:30 -07:00 |
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mrg
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a7ee17eb2d
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Move output of sense amp to side like other techs
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2020-06-26 15:29:27 -07:00 |
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mrg
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c07e20cbe4
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Move mux select from li to m2 in sky130
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2020-06-26 14:27:16 -07:00 |
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mrg
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94d7000717
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Reduce output clutter from gds write
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2020-06-26 12:16:54 -07:00 |
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mrg
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f57eeb88eb
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PEP8 cleanup, multiple vdd/gnd support
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2020-06-26 11:47:55 -07:00 |
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mrg
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e23d41c1d4
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PEP8 cleanup
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2020-06-26 11:47:35 -07:00 |
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mrg
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567675ab31
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PEP8 cleanup
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2020-06-26 11:47:12 -07:00 |
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mrg
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af4ed3dd6e
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Skip riscv func test for time sake
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2020-06-26 06:50:45 -07:00 |
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mrg
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d53abba479
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Always route the channel route since it is it's own design.
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2020-06-25 17:43:44 -07:00 |
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mrg
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76e5389c33
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Change riscv func test name
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2020-06-25 17:43:17 -07:00 |
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mrg
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9eb1b500ea
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Skip phys riscv test
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2020-06-25 17:31:23 -07:00 |
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mrg
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f11afaa63d
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Refactor channel route to be a design.
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2020-06-25 17:30:03 -07:00 |
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mrg
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7220b23402
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Add riscv unit tests
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2020-06-25 15:34:18 -07:00 |
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mrg
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66df659ad4
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Col decoders are anything not bitcell pitch.
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2020-06-25 14:25:48 -07:00 |
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mrg
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f84ee04fa9
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Single bank passing.
Parameterized gate column mux of dff height.
End-cap only supply option instead of no vdd in bitcell.
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2020-06-25 14:03:59 -07:00 |
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mrg
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ee0a003298
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-06-25 08:57:37 -07:00 |
|
 jcirimel
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5941e01b51
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add missing parens
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2020-06-25 08:02:08 -07:00 |
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jcirimel
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59562f2b92
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move accuracy_requirement from techfile to config
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2020-06-25 06:44:07 -07:00 |
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jcirimel
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812cf11e95
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev
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2020-06-25 06:32:29 -07:00 |
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jcirimel
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57b6d49edb
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fix pinv size bining
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2020-06-25 06:32:07 -07:00 |
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mrg
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da900b89ba
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Only expand implants in sky130
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2020-06-24 13:48:30 -07:00 |
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mrg
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ba92467fec
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Add no well enclosure for techs without wells
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2020-06-24 12:07:47 -07:00 |
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mrg
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6c523a7556
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use add_enclosure for npc contacts
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2020-06-24 11:55:44 -07:00 |
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mrg
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e694622f28
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use add_enclosure to extend implants
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2020-06-24 11:54:59 -07:00 |
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mrg
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4bc3df8931
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Add get_tx_insts and expand add_enclosure
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2020-06-24 11:54:36 -07:00 |
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mrg
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93d65e84e1
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Fix power pin layer problems in delay line
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2020-06-24 10:26:49 -07:00 |
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mrg
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98ec9442c6
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Add npc enclosure for pnand2, pnand3, pnor2
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2020-06-24 10:00:00 -07:00 |
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mrg
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1340908330
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Remove fudge factor for pin spacing
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2020-06-24 09:24:26 -07:00 |
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mrg
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cddb16dabc
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Separate active and poly contact to gate rule
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2020-06-24 09:17:39 -07:00 |
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mrg
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a32b5b13e8
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Rename nwell yoffset for consistency
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2020-06-24 08:26:15 -07:00 |
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