luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
1,788 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

1788 Commits

Author SHA1 Message Date
Bin Wu 9ef2616d41 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into pex_fix_v2 2019-06-25 11:28:04 -07:00
Bin Wu 3f3ee9b885 add pex function for magic and openram test 2019-06-25 11:24:25 -07:00
jsowash 3bd69d2759 Added functionality to express polygons in LEF files. 2019-06-25 09:20:00 -07:00
Bin Wu 91febec3a2 add hspice and ngspice pex tests 2019-06-25 09:19:37 -07:00
Matt d22d7de195 Reapply jsowash update without spice model file 2019-06-24 08:59:58 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
mrg 8418aea95a Revert height to width 2019-06-03 15:36:14 -07:00
mrg 58f51b72f1 Merge fixes 2019-06-03 15:31:49 -07:00
mrg 7b8c2cac30 Starting single layer power router. 2019-06-03 15:28:55 -07:00
mrg bd4d965e37 Begin single layer supply router 2019-06-03 15:27:37 -07:00
mrg 4612c9c182 Move power pins before no route option 2019-06-03 15:27:37 -07:00
mrg fc12ea24e9 Add boundary to every module and pgate for visual debug. 2019-06-03 15:27:37 -07:00
mrg 1268a7927b Pbitcell updates. 
Fix module offset error.
Add boundary for debugging.
Line wrap code.
 2019-06-03 15:27:37 -07:00
mrg 17d42d43b4 Add boundary layer 2019-06-03 15:27:37 -07:00
Matt Guthaus 7cca6b4f69 Add back scn3me_subm support 
Add back scn3me_subm tech files
Update cells to be DRC clean with rule 5.5.b
Allow magic for FreePDK45 but not debugged.
Revert to older Magic tech file for SCN3ME_SUBM
 2019-06-03 15:27:37 -07:00
mrg 301f032619 Remove +1 to induce error. 2019-05-31 10:55:17 -07:00
mrg d789f93743 Add debug runner during individual tests. 2019-05-31 10:51:42 -07:00
mrg bf86969972 Create sram subdirectory. 2019-05-31 08:56:24 -07:00
mrg 72f4a223c3 Move power pins before no route option 2019-05-27 16:38:47 -07:00
mrg c2cc901300 Add boundary to every module and pgate for visual debug. 2019-05-27 16:32:38 -07:00
mrg e738353b5c Pbitcell updates. 
Fix module offset error.
Add boundary for debugging.
Line wrap code.
 2019-05-27 16:19:29 -07:00
mrg 42c16ed739 Add boundary layer 2019-05-26 22:30:54 -07:00
mrg 26146b6838 Fix SCN3ME_SUBM stuff. 
Update cells to be DRC clean with rule 5.5.b
Allow magic for FreePDK45 but not debugged.
Revert to older Magic tech file for SCN3ME_SUBM
 2019-05-26 22:28:16 -07:00
mrg 9bb5041d93 Fix pc to p DRC in scn3me_subm 2019-05-26 17:05:00 -07:00
mrg 195fc9804f Add 1w 1r magic just copied 2019-05-21 13:59:44 -07:00
mrg eb40e2fdae Added remaining gds/sp files for multiport in scn3m. 2019-05-21 09:23:25 -07:00
mrg 3fa8c5543a Merge branch 'dev' into scn3me_subm 2019-05-08 17:52:38 -07:00
mrg a5ed9b56cd Optional m4 in design class 2019-05-08 17:51:38 -07:00
mrg 94e736881f Multiport scn3me_subm has drc errors 2019-05-08 16:19:48 -07:00
mrg aca46beb74 Add multiport bitcell spice 2019-05-08 16:17:19 -07:00
Matt Guthaus c24879162a Add back scn3me_subm tech files 2019-05-08 16:06:21 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus e071e53090 Add comments on gds units in tech files. 2019-04-30 10:13:13 -07:00
Matt Guthaus 8b1cd57867 Change contact display wqfrom black X to green solid. 2019-04-29 14:08:10 -07:00
Matt Guthaus 3d98f09019 Add coverage excludes 2019-04-29 10:26:39 -07:00
Matt Guthaus 534c6b36df Use correct back end config file. 2019-04-29 10:20:27 -07:00
Matt Guthaus 8d8565bd9c Add inline_drclvs option for improved coverage 2019-04-29 09:15:46 -07:00
Matt Guthaus 978ba9d2f2 Refactor run scripts. 
Run DRC, LVS, and PEX share a run_*.sh script.
 2019-04-26 15:43:46 -07:00
Matt Guthaus 946a0aca86 Simplify DRC and LVS run scripts. 
Modified run scripts to work on local only files in the temp
directory. This assumes the files and subckts are named the
same as the clel name. Script now copies library files
to the temp directory as well.
 2019-04-26 15:17:39 -07:00
Matt Guthaus 51a97979b9 Add front and back-end test 30. 2019-04-26 15:17:19 -07:00
Matt Guthaus d23aa9a1bd Use local setup.tcl and flatten bitcell arrays. 2019-04-26 14:12:51 -07:00
Matt Guthaus 9cead23f22 Add hierarchy to netgen LVS command. 2019-04-26 13:46:34 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 0439b129bb Some pgates are designs since not a fixed height 2019-04-26 12:33:53 -07:00
Matt Guthaus 05ad4285af Cleanup pgate code. 
Moved create_netlist and create_layout to the pgate class
from which everything is derived. Modified all pgates
to have consistent debug output and order of init function.
 2019-04-26 12:30:42 -07:00
Jesse Cirimelli-Low e507fbd5e9 Merge branch 'datasheet_gen' into dev 2019-04-26 12:29:37 -07:00
Matt Guthaus 222b07ad7a Well contact cleanup for SCMOS TSMC 0.35 2019-04-26 10:19:11 -07:00
Matt Guthaus 50a9515e0c Merge branch 'magic_lvs_ports' of github.com:VLSIDA/PrivateRAM into magic_lvs_ports 2019-04-26 09:19:41 -07:00
Matt Guthaus 3ffcad0db8 Add port makeall for removing symmetry problems in netgen 2019-04-26 09:17:52 -07:00