 mrg
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8021430122
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Fix pbitcell erros
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2020-11-13 15:55:55 -08:00 |
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mrg
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c472a94f1e
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Rework bitcells.
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
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2020-11-13 10:07:40 -08:00 |
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mrg
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3567a3e913
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Remove 1rw_1r
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2020-11-13 08:10:16 -08:00 |
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mrg
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cf63499e76
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Convert bitcells to 1port and 2port
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2020-11-13 08:09:21 -08:00 |
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mrg
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198c0faf85
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Remove special s8 6t names
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2020-11-13 07:45:31 -08:00 |
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mrg
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662d4ea724
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Merge remote-tracking branch 'private/drclvs' into dev
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2020-11-12 16:01:07 -08:00 |
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mrg
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e6a7ecae84
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Fix missing default path in pex
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2020-11-12 14:43:57 -08:00 |
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mrg
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9eeab14639
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Add comment before pininfo
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2020-11-12 14:33:42 -08:00 |
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mrg
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bdda7c4f5f
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Add bl/br pins to dummy array
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2020-11-12 12:38:09 -08:00 |
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mrg
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190234df58
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Add PININFO to outputs too
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2020-11-12 12:12:53 -08:00 |
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mrg
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63941a10e1
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Add None as sp_file parameter to local_drc_check
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2020-11-12 10:01:38 -08:00 |
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mrg
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a2f29e5edd
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Fix missing nand4_leakage #97
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2020-11-12 09:48:08 -08:00 |
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mrg
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d4c4658c77
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Clean up invalid routing layer error message
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2020-11-12 09:43:08 -08:00 |
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mrg
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d3cb22c8c1
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Fix pin vs module names issue #26
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2020-11-12 09:33:48 -08:00 |
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mrg
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537e862d48
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Add -full to LVS script
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2020-11-10 20:38:41 -08:00 |
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mrg
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03dad01e4c
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Use readspice to define ports from sp netlist in Magic extract.
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2020-11-10 17:06:24 -08:00 |
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mrg
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31ae56ff39
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Simplify to a single DRC/LVS library test.
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2020-11-10 16:45:00 -08:00 |
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mrg
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56c2222c2b
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Temp comment Magic GDS filter code.
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2020-11-10 13:37:18 -08:00 |
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mrg
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57e708a6e1
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Add 200 cycles. Can be commented out or run for shorter.
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2020-11-09 15:20:36 -08:00 |
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mrg
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2c203530ad
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Merge branch 'drclvs' into dev
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2020-11-09 14:36:36 -08:00 |
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mrg
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0ba2feee53
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Fix errors in new run_sim calls and corners
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2020-11-09 13:59:46 -08:00 |
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mrg
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e31cbeaa6f
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Don't check for file to determine if it is included.
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2020-11-09 12:11:47 -08:00 |
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mrg
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532492d5ae
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Output functional stimulus to output directory.
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2020-11-09 12:00:25 -08:00 |
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mrg
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31d21e169f
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Skip LEF test as correct output keeps changing.
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2020-11-09 11:14:55 -08:00 |
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mrg
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10542d6cc3
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Output DRC and LVS run files to output directory.
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2020-11-09 11:12:31 -08:00 |
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mrg
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66633a843b
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Add PDK layer names to tech file
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2020-11-09 09:10:43 -08:00 |
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mrg
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2da9c307db
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Disable 4x16 decoder test for now
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2020-11-06 13:50:04 -08:00 |
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mrg
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147649e142
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Why was single port decoder test a dual port?
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2020-11-06 12:21:30 -08:00 |
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mrg
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493c9125f1
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Read different modules overrides for different num ports
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2020-11-06 11:09:50 -08:00 |
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mrg
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8be1436d51
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Use OPTS.bitcell everywhere
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2020-11-05 16:55:08 -08:00 |
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mrg
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18d2987805
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Cleanup
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2020-11-05 16:30:15 -08:00 |
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mrg
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a40716dd48
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Cleanup imports
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2020-11-05 14:32:08 -08:00 |
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mrg
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0118b73eec
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Cleanup imports
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2020-11-05 14:31:53 -08:00 |
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mrg
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681b3a91aa
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Drop to debug in debug module when -d
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2020-11-05 13:20:54 -08:00 |
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mrg
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2c76a2680f
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Adjust openram options.
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
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2020-11-05 13:12:26 -08:00 |
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mrg
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a52aac5f31
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Add gds flatten option for Magic
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2020-11-05 13:12:08 -08:00 |
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mrg
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ce7be7466f
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Model as subckt for Magic too
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2020-11-05 13:11:36 -08:00 |
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mrg
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b160c4a35d
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-11-04 14:31:42 -08:00 |
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mrg
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9a38f7a5f4
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Enable gds readonly in Magic DRC/LVS
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2020-11-04 10:50:53 -08:00 |
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mrg
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fb0b285652
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-11-04 10:40:20 -08:00 |
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mrg
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6e12d4d46c
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Skip tri gate array test
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2020-11-04 06:57:51 -08:00 |
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Matt Guthaus
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844b850b74
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Fix typo in 1w_1r bitcell
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2020-11-03 17:14:45 -08:00 |
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mrg
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3315fe32ba
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Improve nominal corner message
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2020-11-03 16:49:49 -08:00 |
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mrg
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423e2c165f
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Remove test cell in scn4m_subm tech.py
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2020-11-03 16:38:55 -08:00 |
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mrg
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45cdecdea9
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Improve error message about missing DRC/LVS tools.
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2020-11-03 15:47:04 -08:00 |
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mrg
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6335bc3784
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Do not drop to pdb shell when verbose
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2020-11-03 15:46:46 -08:00 |
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mrg
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29f4ee492b
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Fix missing imports in replica bitcells.
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2020-11-03 15:24:44 -08:00 |
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mrg
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2f12c77668
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Create single port memory config examples.
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2020-11-03 14:42:56 -08:00 |
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mrg
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fb9956fe96
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Fix missing include
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2020-11-03 13:50:45 -08:00 |
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mrg
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d209e8d9a3
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Disable perimeter pins for now
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2020-11-03 13:35:34 -08:00 |
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