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OpenRAM
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131 Commits

Author SHA1 Message Date
samuelkcrow 3a8e29ce77 Merge remote-tracking branch 'origin/dev' into no_rbl 2023-02-20 22:11:02 -08:00
samuelkcrow 52dcd81a08 use left_rbl instead of rbl to calculate replica column mirroring (column offset) 2023-02-20 17:28:24 -08:00
samuelkcrow 2565305158 fix positional getters 2023-02-13 18:45:21 -08:00
samuelkcrow 8d6d8f2f8c revert variable names to those inherited from bitcell base array 2023-02-13 18:45:21 -08:00
samuelkcrow 3dac89d041 fixing named variables passed between array modules 2023-02-04 21:06:41 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
samuelkcrow 2f795f8068 fix height calculation bug for replica array 2023-01-26 17:38:24 -08:00
samuelkcrow ebe163c57e fix placement bug for cap cells including wrong height from replica array 2023-01-24 11:07:52 -08:00
samuelkcrow d460eacfcc standardize rbl arguments interface 2023-01-18 22:43:37 -08:00
samuelkcrow 6a8a76dd23 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl 2022-12-14 08:13:08 -08:00
samuelkcrow 119bcb9197 route unused wordlines (still failing lvs) 2022-12-14 08:12:55 -08:00
samuelkcrow d224c06b25 placement positions problem fixed, incorrect w,h calculations were the problem 2022-12-10 19:03:55 -08:00
samuelkcrow 68fb4e3c63 introduced some other bugs but scmos tiling is correct 2022-12-02 09:42:33 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
samuelkcrow ac8a15acc0 fix get_replica_top and get_replica_left return values 2022-11-21 17:42:50 -08:00
samuelkcrow 5a82c45a33 Change how lists of BLs and WLs are named and organized for proper connection between these modules 2022-10-24 20:08:13 -07:00
samuelkcrow 55d89fbae8 copy supply pins to top level in replica array, now passing tests 2022-10-19 17:13:54 -07:00
samuelkcrow f9419e8ff7 fix self.rbls and fix handling of rbl WLs (kinda) 2022-10-17 20:51:42 -07:00
samuelkcrow a1ca7c312d remove grounded WLs from replica array 2022-10-11 11:43:26 -07:00
samuelkcrow cfd52a6065 fix offsets so array ends up at 0,0 2022-09-26 14:24:16 -07:00
samuelkcrow f1f18b3b54 replica code working but failing lvs 2022-09-07 19:32:25 -07:00
samuelkcrow 3ef52789be first pass splitting replica array into capped and replica array modules 2022-09-07 12:39:35 -07:00
mrg 6707a93c3c Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45. 2022-07-20 10:27:30 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg bdd334bce9 Add layer and directions to pbitcell 2022-05-16 16:11:13 -07:00
mrg 4345136d1a Fix offsets for local bitcell arrays. 2022-05-13 10:46:00 -07:00
mrg b6c3580e24 Fix width of replica routes. Don't enclose pins if they overlap sufficiently. 2022-05-09 11:44:46 -07:00
mrg 50045e54e8 Fix a couple supply routing issues. 2022-05-03 11:45:51 -07:00
mrg b1bb9151c4 Reimplement off grid pins. 
Long pins aren't accessed on end pins anymore.
Fix problem with multiple non-enclosed space causing blockages.
Add partial pin offgrid enclosure algorithm.
 2022-05-02 15:43:14 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
mrg 5e546ee974 New power strapping mostly working. 
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
 2022-04-05 13:51:55 -07:00
mrg 7e7670581c Add some vertical/horizontal pins for sky130 only 2022-03-16 07:58:29 -07:00
mrg d69e55c2e3 Power routing changes. 
Make the power rails an "experimental_power" option and conditional.
Rename route_vdd_gnd to route_supplies everywhere for consistency.
 2022-03-06 09:56:00 -08:00
mrg 8b3c10ae79 Improvements to power routing. 
Improved the route horizontal and vertical pin functions to
create a single pin at the end.
Swapped A and B on wordline driver input for cleaner routing
in most technologies.
Fixed vertical supply routing in port_address.
 2022-03-04 15:44:07 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
mrg 3abebe4068 Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
Jesse Cirimelli-Low 4ea0fcd068 support multi cell wide precharge cells 2021-04-23 22:49:29 -07:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 01d312d65c Refactor add power pins 2021-01-13 10:57:12 -08:00
mrg 47cc4cbfca Remove extra debug statement 2020-12-08 11:55:53 -08:00
mrg 0100ae57a3 Fix mirror with odd number of rows 2020-12-08 10:31:22 -08:00
mrg 3829213afe Use and2_dec instead of buf_dec for better wldriver layout 2020-12-01 11:19:12 -08:00
mrg aa03eec943 Fix syntax error. 2020-11-21 07:16:45 -08:00
mrg 4c75bc003e Fix bounding box of replica array to include wordline grounds. 2020-11-21 07:03:59 -08:00
mrg f729e9fca7 Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions. 2020-11-20 16:56:07 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg 8be1436d51 Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00