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OpenRAM
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147 Commits

Author SHA1 Message Date
Eren Dogan ca03da8d95 Use conda to install the tools needed 2023-01-20 15:34:45 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Eren Dogan 845f32805f Change compiler name for unit tests 2022-11-06 14:05:08 -08:00
mrg 8c85230033 Remove experimental power option. 2022-05-23 10:08:35 -07:00
mrg f1f4453d14 Add column decoder module with power supply straps. 2022-05-17 13:32:19 -07:00
mrg 5e546ee974 New power strapping mostly working. 
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
 2022-04-05 13:51:55 -07:00
mrg 229a3b5b3d By default uniquify instances based on macro name. 2022-03-11 18:01:45 -08:00
mrg d69e55c2e3 Power routing changes. 
Make the power rails an "experimental_power" option and conditional.
Rename route_vdd_gnd to route_supplies everywhere for consistency.
 2022-03-06 09:56:00 -08:00
mrg c69eb47a7a Finalize uniquify option for SRAMs 2021-06-22 16:13:33 -07:00
mrg cf61096936 Merge branch 'laptop_checkpoint' into dev 2021-06-04 15:22:37 -07:00
mrg 537fd6eff9 Use None instead of empty string for tool names. 2021-06-01 16:41:14 -07:00
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
mrg 77f221d859 Separate supply pin type from route supplies option 2021-05-28 11:55:50 -07:00
Hunter Nichols 2f4f8ca912 Fixed conflicts in delay and elmore modules on merge with dev. 2021-05-25 15:25:43 -07:00
mrg 3abebe4068 Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
mrg 507ad9f33d Change sim threads to 3. 2021-05-14 11:45:10 -07:00
Jesse Cirimelli-Low 6ea4bdc5e5 Merge branch 'dev' into laptop_checkpoint 2021-04-23 22:50:23 -07:00
Jesse Cirimelli-Low 4ea0fcd068 support multi cell wide precharge cells 2021-04-23 22:49:29 -07:00
mrg f45efe3db6 Abstracted LEF added. Params for array wordline layers. 2021-04-21 11:04:01 -07:00
Hunter Nichols 5dad0f2c0e Merged with dev, fixed import conflict in lib 2021-04-18 23:59:35 -07:00
mrg b510925bdb Enable pruning by default (except on unit tests) 2021-04-07 16:08:29 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
mrg b6f3fbdd1f Use OPTS.precharge instead of hard coded precharge. 2021-03-15 09:44:14 -07:00
Hunter Nichols b5516865f1 Added option to allow specific load/slew combinations in config file. 2021-02-24 16:43:34 -08:00
mrg 7610f23fc7 Sub temp directory. Add github archive. 2021-02-10 15:39:12 -08:00
mrg 19e99d1c7b Enable parallel regression testing. 2021-02-03 14:19:11 -08:00
Hunter Nichols df8d59f32e Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
Hunter Nichols 7bed5bdd1c Added option for model to specify regression model data path. 2021-01-25 14:24:54 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
Hunter Nichols e26e17c53f Added option to specify exact corners for characterization in config file 2021-01-22 00:50:28 -08:00
Hunter Nichols d8437249f7 Condensed some datasheet code in lib.py 2021-01-06 15:53:22 -08:00
Hunter Nichols bb841fc84d Added option to output the datasheet.info file. 2021-01-06 12:45:34 -08:00
Hunter Nichols cd84cf1973 Merged and addressed conflict in delay.py 2021-01-06 01:37:16 -08:00
mrg e59333a232 Change options to use route perimeter pins and supply as tree by default. 2020-12-23 07:25:07 -08:00
Hunter Nichols 732404b330 Added an option that prevents lib.py from generating corners and only uses corners in config file. 2020-12-17 15:32:15 -08:00
Hunter Nichols 942675051a Added test for linear regression model. 2020-12-14 14:37:53 -08:00
Hunter Nichols fc55cd194d Added model selection option. 2020-12-09 12:54:11 -08:00
mrg 0ccb3487b6 Set default port map 2020-11-24 13:27:11 -08:00
mrg 5ee3f4cc66 Many edits. 
Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.
 2020-11-22 08:24:47 -08:00
Hunter Nichols 53e64fb696 Merge branch 'dev' into characterizer_bug_fixes 2020-11-20 11:16:41 -08:00
Hunter Nichols 9fd473ce70 Fixed issue with selection of column address when checking bitline names. 2020-11-20 01:11:08 -08:00
mrg 033111a5f3 Default to no hierarchical word lines. 2020-11-19 10:48:35 -08:00
Hunter Nichols 35e1a523cc Changed named on delay chain sizing variable. Automatic sizing default is False. 2020-11-17 14:29:01 -08:00
Hunter Nichols df4c2bad1f Disabled debug measures that are WIP. 2020-11-17 13:30:18 -08:00
Hunter Nichols ac425643a0 Merge branch 'dev' into characterizer_bug_fixes 2020-11-17 13:22:56 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
Hunter Nichols 84ba5c55d1 Merged with dev 2020-11-10 15:47:56 -08:00
mrg 2c76a2680f Adjust openram options. 
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
 2020-11-05 13:12:26 -08:00