 mrg
|
7bb21fb73f
|
Updates to local and global arrays to make bitline and wordlines consistent.
|
2020-09-09 11:54:46 -07:00 |
|
|
mrg
|
8e91ec1770
|
Add check_pins function
|
2020-09-08 13:31:50 -07:00 |
|
|
mrg
|
1269bf6e16
|
Global bitcell working
|
2020-09-04 13:06:58 -07:00 |
|
|
mrg
|
1534295326
|
Ground dummy lines in replica bitcell array
|
2020-09-03 14:04:20 -07:00 |
|
|
mrg
|
f6f6242d68
|
Ground dummy lines in replica bitcell array
|
2020-09-03 10:45:28 -07:00 |
|
|
mrg
|
4ec47d8ee1
|
Refactor global and local to be a bitcell_base_array
|
2020-09-01 11:59:01 -07:00 |
|
|
mrg
|
c1c631abe1
|
Global bitcell array passes LVS/DRC
|
2020-09-01 10:57:49 -07:00 |
|
|
mrg
|
7bdce3ca9a
|
Don't make dummy bitlines pins for simplicity
|
2020-09-01 09:55:23 -07:00 |
|
|
mrg
|
11a82b7283
|
Fixed local bitcell array for single and dual port
|
2020-08-27 14:03:05 -07:00 |
|
|
mrg
|
c321d85595
|
Fix syntax error for dual port
|
2020-08-26 09:54:41 -07:00 |
|
|
mrg
|
e92337ddaf
|
Separate get_ and get_all for bitlines and wordlines
|
2020-08-25 17:08:48 -07:00 |
|
|
mrg
|
bdb18b4cab
|
Fix disconnected replica pins
|
2020-08-25 14:51:49 -07:00 |
|
|
mrg
|
bd8bf9afd8
|
Remove RBL label at top level of SRAM
|
2020-08-25 14:42:21 -07:00 |
|
|
mrg
|
856cce1e62
|
Add -json for detailed LVS output
|
2020-08-25 13:58:28 -07:00 |
|
|
mrg
|
28bd93bf51
|
Still working on array refactor
|
2020-08-25 11:50:44 -07:00 |
|
|
mrg
|
8dee5520e0
|
Standardize array names independent of bitcell
|
2020-08-21 13:44:35 -07:00 |
|
|
mrg
|
b762580ee2
|
Skip global test for now
|
2020-08-19 11:36:21 -07:00 |
|
|
mrg
|
593a98e29a
|
Update local bitcell array for dual port
|
2020-08-19 11:35:55 -07:00 |
|
|
mrg
|
e215c0e016
|
Drafting global bitcell array
|
2020-08-18 16:30:55 -07:00 |
|
|
mrg
|
5776788574
|
Order of wordlines and bitlines in bank
|
2020-08-18 16:30:38 -07:00 |
|
|
mrg
|
224e359208
|
Fix pin order for replica array
|
2020-08-18 15:59:05 -07:00 |
|
|
mrg
|
f58fc6579f
|
Rename local/global tests
|
2020-08-18 15:58:44 -07:00 |
|
|
mrg
|
e3e4bac922
|
Fix replica bitcell array for right only RBL
|
2020-08-18 15:47:52 -07:00 |
|
|
mrg
|
59d65c46c3
|
Fix bug in not adding RBLs in local bitcell array
|
2020-08-18 15:11:10 -07:00 |
|
|
mrg
|
2643a96f97
|
Order inputs wordline, bitline, supply
|
2020-08-18 14:29:36 -07:00 |
|
|
mrg
|
b288bba43e
|
Add global bitcell array test
|
2020-08-18 14:29:23 -07:00 |
|
|
mrg
|
e37a9234cc
|
Update replica column call to new refactor
|
2020-08-18 09:14:50 -07:00 |
|
|
mrg
|
bc974ff78e
|
Update replica column unit tests for new refactor
|
2020-08-18 08:56:24 -07:00 |
|
|
mrg
|
99e252d6d4
|
Update interface of RBL array
|
2020-08-17 17:19:07 -07:00 |
|
|
mrg
|
b1e55f9072
|
Add local bitcell array
|
2020-08-17 15:14:42 -07:00 |
|
|
mrg
|
3a692e2846
|
Comment updates
|
2020-08-17 14:35:39 -07:00 |
|
|
mrg
|
60224b105f
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2020-08-17 14:20:34 -07:00 |
|
|
mrg
|
94bfad4113
|
Horizontal gnd vias for unused array inputs
|
2020-08-17 13:24:34 -07:00 |
|
|
mrg
|
bddb251a84
|
More room for power contacts
|
2020-08-17 12:32:44 -07:00 |
|
|
mrg
|
2c43d315db
|
Revert gds readonly true
|
2020-08-17 12:19:23 -07:00 |
|
|
mrg
|
35a1b00aa0
|
Extra space for unused wl contacts
|
2020-08-14 14:23:40 -07:00 |
|
|
mrg
|
170e3feb7d
|
Fix order of replica wordlines and bitlines
|
2020-08-14 14:14:49 -07:00 |
|
|
mrg
|
604e433e22
|
Add readonly true for Magic scripts
|
2020-08-14 10:40:31 -07:00 |
|
|
mrg
|
dfb593e9b4
|
Add draft lyt file -- connectivity not working
|
2020-08-14 10:38:22 -07:00 |
|
|
mrg
|
2ac04efe2e
|
Must connect for replica cells other than top/bottom
|
2020-08-13 16:26:19 -07:00 |
|
|
mrg
|
797c41c750
|
Skip local bitcell array test
|
2020-08-13 14:36:39 -07:00 |
|
|
mrg
|
50525e70f4
|
Fix up to SRAM level with new replica bitcell array ports.
|
2020-08-13 14:29:10 -07:00 |
|
|
mrg
|
8dbaa66aa5
|
Merge branch 'super' into dev
|
2020-08-12 14:25:13 -07:00 |
|
|
mrg
|
7ac4574e4f
|
Use micron units for all simulation in sky130
|
2020-08-12 13:54:55 -07:00 |
|
|
mrg
|
5fc6438553
|
Fix pinv_dec super call
|
2020-08-12 13:22:28 -07:00 |
|
|
mrg
|
15c8c200f3
|
Undo super() in measurement abstract class
|
2020-08-12 12:10:12 -07:00 |
|
|
mrg
|
55814a8f74
|
Fix syntax errors in pgates for super edits
|
2020-08-12 11:15:32 -07:00 |
|
|
mrg
|
0bec6f0439
|
Fix SRAM to use simulation spice instead of LVS spice
|
2020-08-12 10:41:21 -07:00 |
|
|
mrg
|
a55909930f
|
Replace replcia_bitcell_array with new one in bank
|
2020-08-12 09:49:14 -07:00 |
|
|
mrg
|
8e890c2014
|
Replica bitcell with all the fixings
|
2020-08-11 15:00:29 -07:00 |
|