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luke/OpenRAM
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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 18:02:23 +02:00
Code Issues Packages Projects Releases Wiki Activity
3,919 Commits 5 Branches 63 Tags
7b2f73d8b99c0f2ce3d7d3a0686592eef230258f
Commit Graph
14 Commits
Author SHA1 Message Date
mrg bbfccd1e00 Remove netlist bl/br swaps on flipped cells 2022-05-23 17:16:36 -07:00
Jesse Cirimelli-Low 172d070880 fix bl routing in rba 2022-05-19 21:45:48 -07:00
Jesse Cirimelli-Low 0667a93d53 single port rba passing lvs 2022-03-07 13:45:50 -08:00
Jesse Cirimelli-Low 038acd1568 single port rba lvs progress 2022-03-07 01:20:59 -08:00
Jesse Cirimelli-Low 8d9166a01b only rba lvs errors is colend body extraction 2021-12-29 12:43:02 -08:00
Jesse Cirimelli-Low cf8c486cea merge sky130_dummy_array 2021-12-22 16:00:59 -08:00
Jesse Cirimelli-Low de60a1c38a merge in opc fixes 2021-12-22 15:53:36 -08:00
Jesse Cirimelli-Low 468de963f6 remove add_mod in sky130 2021-12-22 15:51:49 -08:00
Jesse Cirimelli-Low 8a0450afac adjust replica col wls 2021-12-22 15:46:03 -08:00
Jesse Cirimelli-Low 8879820af4 replica col lvs fix 2021-12-15 14:19:52 -08:00
Jesse Cirimelli-Low 4e5744df50 remove add_mod() 2021-12-15 01:36:56 -08:00
Jesse Cirimelli-Low ddb76c4aff fix dummy array opc 2021-12-15 01:28:30 -08:00
Jesse Cirimelli-Low 8eb6caa248 fix bitcell array opc errors 2021-12-14 22:15:27 -08:00
mrg fa2232fc11 Initial commit of sky130 config files 2021-10-04 15:16:28 -07:00
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