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OpenRAM
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4,338 Commits 4 Branches 63 Tags 78 MiB
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606 Commits

Author SHA1 Message Date
Jacob Walker fef9902c45 rom base passing tests with top level routing 2023-03-30 11:30:50 -07:00
Jacob Walker af0209ec96 passing code style 2023-03-30 11:30:50 -07:00
Jacob Walker bbf2cd2913 Changes for test generation and simulation 2023-03-30 11:30:50 -07:00
Jacob Walker f7aed247fd column control and address precharge 2023-03-30 11:30:50 -07:00
samuelkcrow 3a8e29ce77 Merge remote-tracking branch 'origin/dev' into no_rbl 2023-02-20 22:11:02 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
samuelkcrow 29c79abaf8 move layout pins when copying them 2023-01-15 20:33:38 -08:00
mrg 7ddb1a39dc Line wrap output spice subckt and instance lines at 80 characters. 2022-12-12 13:58:30 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan 2e7206343e Remove unnecessary imports 2022-11-27 13:11:10 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Bugra Onal 25cc08db80 Further fixes for new verilog naming convention 2022-08-18 11:03:13 -07:00
Bugra Onal aefe46394c Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
Bugra Onal a361d9f7bb Fixed write_size checks for None 2022-07-28 16:45:58 -07:00
Bugra Onal c1e891b2fb Multibank file generation (messy) 2022-07-28 15:03:41 -07:00
Bugra Onal 846dfc79dc modified template engine & sram multibank class 2022-07-28 15:03:41 -07:00
Bugra Onal bde4a389aa Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal 9158e92a71 TEmplate rework 2022-07-28 15:03:41 -07:00
Bugra Onal a5728cdecc Base-verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 769633a459 Base template additions 2022-07-28 15:03:41 -07:00
Bugra Onal cda3822526 Verilog Template additions 2022-07-28 15:03:41 -07:00
Bugra Onal 28c5406075 Base verilog template init 2022-07-28 15:03:41 -07:00
Bugra Onal 30f5638b9f Replaced instances of addr_size with bank_addr 2022-07-28 15:03:41 -07:00
Bugra Onal 24bb6f8c11 Multibank file generation (messy) 2022-07-28 15:03:37 -07:00
mrg 5db470155e Fix print errors in code format unit test. 2022-07-26 12:20:15 -07:00
Eren Dogan e3fe8c3229 Remove line ending whitespace 2022-07-22 19:52:38 +03:00
Bugra Onal 6d6063ef4e modified template engine & sram multibank class 2022-07-21 15:56:29 -07:00
Bugra Onal b75e1fc499 Template section clone method 2022-07-21 15:45:50 -07:00
Bugra Onal f2cd611cb8 TEmplate rework 2022-07-21 15:45:50 -07:00
Bugra Onal 988399ba73 Base-verilog 2022-07-21 15:45:50 -07:00
Bugra Onal 06c56c256e Base template additions 2022-07-21 15:45:50 -07:00
Bugra Onal 3d3a8202fe Verilog Template additions 2022-07-21 15:45:50 -07:00
Bugra Onal be9fadf1bb Base verilog template init 2022-07-21 15:45:50 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg 8217a84165 Uniquify overlap points during segment overlap computation. 2022-05-17 13:31:23 -07:00
mrg 9b592ab432 Fix missing hash recompute in vector class. 2022-05-17 13:30:41 -07:00
mrg 4be075e586 Overlap length can include a rectangle overlap. 2022-05-16 14:57:32 -07:00
mrg 74c2c5ae0e Don't double prefix a name 2022-05-13 14:32:52 -07:00
mrg fbb2ea5fb6 Intersection now returns a pin_layout fixed during LEF computation. 2022-05-13 13:56:16 -07:00
mrg 8f2d787d53 Add min area metal in preferred direction 2022-05-11 10:50:32 -07:00
mrg b6c3580e24 Fix width of replica routes. Don't enclose pins if they overlap sufficiently. 2022-05-09 11:44:46 -07:00
mrg 50045e54e8 Fix a couple supply routing issues. 2022-05-03 11:45:51 -07:00
mrg b1bb9151c4 Reimplement off grid pins. 
Long pins aren't accessed on end pins anymore.
Fix problem with multiple non-enclosed space causing blockages.
Add partial pin offgrid enclosure algorithm.
 2022-05-02 15:43:14 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
mrg 5e546ee974 New power strapping mostly working. 
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
 2022-04-05 13:51:55 -07:00
mrg 01a73b31e1 Fix power ring routing boundary bug. 2022-03-18 10:32:25 -07:00
mrg 7e7670581c Add some vertical/horizontal pins for sky130 only 2022-03-16 07:58:29 -07:00
mrg 229a3b5b3d By default uniquify instances based on macro name. 2022-03-11 18:01:45 -08:00
mrg b841e18abd Remove breakpoint 2022-03-07 16:59:55 -08:00
mrg 2796800898 Fix bug with incorrect pitch while adding channel route trunks. 2022-03-07 16:12:20 -08:00