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OpenRAM
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606 Commits

Author SHA1 Message Date
mrg d69e55c2e3 Power routing changes. 
Make the power rails an "experimental_power" option and conditional.
Rename route_vdd_gnd to route_supplies everywhere for consistency.
 2022-03-06 09:56:00 -08:00
mrg 8b3c10ae79 Improvements to power routing. 
Improved the route horizontal and vertical pin functions to
create a single pin at the end.
Swapped A and B on wordline driver input for cleaner routing
in most technologies.
Fixed vertical supply routing in port_address.
 2022-03-04 15:44:07 -08:00
mrg febf7031b1 Fix wrong power layer for min area constraint 2022-03-02 17:04:54 -08:00
mrg 7654cd7295 Allow supply pins on m4 too 2022-03-02 16:47:17 -08:00
mrg 51ba88d896 Port address with vertical power stripes 2022-03-02 16:29:43 -08:00
mrg 0908aa9e25 Add route vertical pins 2022-03-01 14:37:09 -08:00
mrg 54bd022efc Rework precharge route supply horizontally 2022-02-28 11:36:10 -08:00
mrg 7b77378927 Add layer to horizontal pin help and use in precharge 2022-02-25 10:45:25 -08:00
mrg d4c14d7d19 Add horizontal pin helper function 2022-02-23 14:06:19 -08:00
mrg abac5a11ab Move power supply stack to design 2022-02-18 15:02:45 -08:00
mrg e460eff014 Add per tool lvs directories 2021-12-17 10:21:34 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
mrg e6a009312e Move mem reg before usage for compatibility 2021-10-13 09:46:02 -07:00
Hunter Nichols 39ae1270d7 Merge branch 'dev' into cacti_model 2021-09-20 17:01:50 -07:00
mrg 8d9a4cc27b PEP8 cleanup 2021-09-07 16:49:44 -07:00
Hunter Nichols 1236a0773a Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage. 2021-09-07 15:56:27 -07:00
Hunter Nichols 6b8d143073 Changed cacti RC delay function to better match cacti code in bitcell. Sense amp also has similar changed but is missing transconductance parameter. 2021-09-01 14:27:13 -07:00
erendo e9b370bf21 Fix write masks in Verilog 2021-08-29 00:31:32 +03:00
Hunter Nichols 680d7b5d93 Added special RC delay functions for the bitline and sense amp to match CACTI. Contains temporary parameters which need to be defined. 2021-08-25 16:12:05 -07:00
Hunter Nichols 12c03ddd9f Fixed issues with load capcitance units. Changed freepdk45 r and c wire values to be more in line with cacti. 2021-08-16 22:58:26 -07:00
Hunter Nichols b3500982ca Fixed issue with wire resistance in total resistance equations for cacti. Fixed issue with sense amp resistance values. 2021-08-04 16:10:27 -07:00
Hunter Nichols b44f840814 Changed delay calculation to include wire resistance and wire capacitance. Added bitline r and c values. 2021-08-01 19:25:54 -07:00
Hunter Nichols 1b89533d7b Added unit r and c values with m2 minwidth incorporated to match CACTI params 2021-08-01 00:23:59 -07:00
biarmic 85955ce298 Fix addr flop in Verilog 2021-07-30 12:22:55 +03:00
Hunter Nichols 54cbef1aff Replaced cacti tech params with already existing params. Added an existence check in design_rules. 2021-07-27 14:31:22 -07:00
Hunter Nichols 1e08005639 Merge branch 'dev' into cacti_model 2021-07-26 14:35:47 -07:00
Hunter Nichols 3e0a49e58d Added options for the model type in timing graph (cacti or elmore) 2021-07-25 22:28:23 -07:00
Hunter Nichols 5ad86538d4 Renamed graph_util to timing_graph to match the module name 2021-07-25 20:21:54 -07:00
Hunter Nichols 7dd9023ce4 Uncommented horowitz delay function. 2021-07-21 15:02:39 -07:00
Hunter Nichols 10085d85ab Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files. 2021-07-21 14:59:02 -07:00
Hunter Nichols 1acc10e9d5 Added name changes to on resistance params. Added input capacitance functions to relevant modules for CACTI input load functions. 2021-07-21 12:24:08 -07:00
Hunter Nichols f6924b7cc2 Removed unusued inputs in drain_c function 2021-07-20 11:33:18 -07:00
Hunter Nichols ebc91814e5 Fixed various issues with imported code from CACTI, added CACTI as an option for analytical sim, added placeholder names in tech files for CACTI 2021-07-12 15:48:47 -07:00
Hunter Nichols 2c9f755a73 Added on resistance functions for pgates, custom cells, and bitcell. 2021-07-12 14:25:37 -07:00
Hunter Nichols e9bea4f0b6 Changed names of some functions in base CACTI delay function. Removed unused analytical delay functions. 2021-07-12 13:02:22 -07:00
Jesse Cirimelli-Low 1a7adcfdad fix vnb and vpb routing in rba 2021-07-08 18:31:55 -07:00
Hunter Nichols c1efa2de59 Added delay function for cacti, moved cacti related delay functions to hierarchy_spice, and trimmed the functions to remove irrelevant options for OpenRAM. 2021-07-07 13:22:30 -07:00
Jesse Cirimelli-Low b5daa51a6c don't use hard coded purpose numbers 2021-07-01 17:31:01 -07:00
Jesse Cirimelli-Low c9b3f4772e fix bias correspondence points 2021-06-30 05:21:39 -07:00
Jesse Cirimelli-Low c36f471333 add vnb/vpb lvs correspondence points 2021-06-29 02:31:56 -07:00
Jesse Cirimelli-Low c599d8f62c use special purposes with _get_gds_reader 2021-06-23 13:21:19 -07:00
mrg 8d71a98ce9 Make purposes argument to gdsMill. Create prefixGDS.py script. 2021-06-22 14:40:43 -07:00
mrg af31027504 Fix error in 1 spare column Verilog 2021-06-21 13:13:53 -07:00
mrg 67877175b2 Fix error in no spare column verilog 2021-06-18 08:41:26 -07:00
mrg 81d20ec2aa Add spare cols to behavioral Verilog model 2021-06-18 07:23:41 -07:00
Jesse Cirimelli-Low 1ce6b4d41a fix freepdk45 2021-06-17 03:21:01 -07:00
Hunter Nichols 16e658726e When determining bitline names, added a technology check for sky130. 2021-06-16 17:04:02 -07:00
mrg cf61096936 Merge branch 'laptop_checkpoint' into dev 2021-06-04 15:22:37 -07:00
mrg 1ded978256 Change nwell from gnd to vdd. dnwell space added. 2021-06-01 15:10:55 -07:00
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
mrg 77f221d859 Separate supply pin type from route supplies option 2021-05-28 11:55:50 -07:00
mrg f6587badad Improve supply routing for ring and side pins 2021-05-28 10:58:30 -07:00
mrg 8bf37ca708 Connect dnwell taps to gnd 2021-05-26 17:38:09 -07:00
mrg 6493d1a7f4 Add dnwell 2021-05-26 16:14:16 -07:00
mrg e16f44cc81 Update lib file with external supply names 2021-05-26 15:34:32 -07:00
mrg d579a60382 Fix external supply names in verilog 2021-05-26 15:26:20 -07:00
Jesse Cirimelli-Low f9eae3fb80 route bias pisn 2021-05-24 02:42:04 -07:00
mrg 3abebe4068 Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
Jesse Cirimelli-Low 0ba229afe5 Merge branch 'dev' into laptop_checkpoint 2021-05-07 19:06:17 -07:00
mrg e995e61ea4 Fix Verilog module typo. Adjust RBL route. 2021-05-06 14:32:47 -07:00
mrg 2243761500 Must transitively cut blockages until no more. 2021-05-05 13:44:06 -07:00
Jesse Cirimelli-Low d3199ea70e Merge branch 'dev' into laptop_checkpoint 2021-05-03 12:53:31 -07:00
mrg 98fb34c44c Add conditional power pins to Verilog model. 2021-04-30 14:15:32 -07:00
Jesse Cirimelli-Low 6ea4bdc5e5 Merge branch 'dev' into laptop_checkpoint 2021-04-23 22:50:23 -07:00
Jesse Cirimelli-Low 4ea0fcd068 support multi cell wide precharge cells 2021-04-23 22:49:29 -07:00
mrg a111ecb74c Fix extra indent that made openlane fail. 2021-04-22 13:05:51 -07:00
mrg f45efe3db6 Abstracted LEF added. Params for array wordline layers. 2021-04-21 11:04:01 -07:00
mrg 584349c911 Add custom parameter for wordline layer 2021-04-21 11:04:01 -07:00
mrg aa5e1fd168 Merge remote-tracking branch 'olofk/verilog_model_features' into dev 2021-04-15 14:41:56 -07:00
Olof Kindgren 688a1f1e60 Add HOLD_DELAY parameter for dout in verilog model 
Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
 2021-04-15 22:39:49 +02:00
Olof Kindgren 1d657abebc Add VERBOSE parameter to generated verilog model 
This allows disabling the $display commands that are generated for every
read and write access to the model. The verilog output has been tested
with the following example script

from compiler.base.verilog import verilog

v = verilog()

v.num_words = 256
v.word_size = 32
v.write_size = 8
v.name = "sky130_sram_1kbyte_1rw1r_32x256_8"
v.all_ports = [0,1]
v.readwrite_ports = [0]
v.read_ports = [0,1]
v.write_ports = [0]
v.addr_size=8

v.verilog_write("mymodule.v")

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
 2021-04-15 22:33:57 +02:00
Jesse Cirimelli-Low e976c4043b Merge branch 'dev' into laptop_checkpoint 2021-04-14 15:58:06 -07:00
mrg 41226087ba Use separate mXp pin layer if it exists 2021-04-14 13:55:21 -07:00
mrg 3eed6bb8ff Check for None before checking DRC tool 2021-04-14 11:07:38 -07:00
mrg a730fd0f10 Use magic for LEF abstract. Fix supply perimter pin. 2021-04-14 10:01:43 -07:00
mrg 0e48e020c1 Use pins in computing bbox offsets 2021-04-13 16:24:28 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg db118beeba Zoom parameter should be optional in tech files. 2021-03-02 13:38:09 -08:00
mrg 9e7c04a43a Merge lekez2005 changes WITHOUT control logic change. 2021-03-01 15:19:30 -08:00
mrg 4ab694033d Merge remote-tracking branch 'bvhoof/dev' into dev 2021-03-01 12:16:26 -08:00
ota2 48bc47c686 Set pin label size to use zoom factor from tech specifications 2021-02-27 18:30:57 -05:00
jcirimel b18e2eae8d remove debug lines and merge 2021-02-09 20:53:23 -08:00
jcirimel dbe8a7f1af fix pwell pin shape bug 2021-02-09 20:51:50 -08:00
Bob Vanhoof d14a68847e added cell label checker and cell labels to the freepdk technology 2021-02-09 13:09:26 +01:00
mrg bc8fd4a882 Merge branch 'supply_router' into dev 2021-01-25 11:01:48 -08:00
Matt Guthaus eebc2a93b6 Remove redundant pins when adding each pin 2021-01-25 09:36:27 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg db142bcd5a Rename pins to original names 2021-01-21 15:22:54 -08:00
mrg 88f2198524 Always use min area power/IO pins 2021-01-13 13:56:46 -08:00
mrg 4991693f1a Clean up min area 2021-01-13 12:32:17 -08:00
mrg 01d312d65c Refactor add power pins 2021-01-13 10:57:12 -08:00
mrg 7eb1e2f2d1 Keep previous pin shapes which were used in router pin connections. 2021-01-06 11:31:16 -08:00
mrg d61fcb3be3 Fix lpp erase bug in removing router annotations 2021-01-06 09:39:01 -08:00
mrg 94b1e729ab Don't add vias when placing dff array 2020-12-22 17:08:53 -08:00
mrg 286ac635d6 Escape router changes. 
Rename exit router to escape router.
Perform supply and signal escape routing after channel and other routing.
 2020-12-22 16:35:05 -08:00
mrg 52119fe3b3 Cleanup exit route. Pins are on perimeter mostly. 2020-12-22 15:56:51 -08:00
mrg ae1c889235 Updates to IO signal router. 
Route signals to perimeter using maze router.
Move IO pins without perimeter pins to M3 using add_io_pin (like add_power_pin).
 2020-12-22 09:39:58 -08:00
mrg 6101195b51 Function to remove layout pins. 2020-12-21 12:44:04 -08:00
mrg 878a9cee8a Add channel routes as flat instances to appease Magic extraction. 2020-12-15 16:01:39 -08:00
mrg fd118c62e5 Default zom is None not negative. 2020-12-15 13:27:36 -08:00