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OpenRAM
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55 Commits

Author SHA1 Message Date
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
mrg fc6e6e1ec7 Add via when write driver supply is different layer 2021-04-28 15:16:26 -07:00
mrg 03e0c14ab2 Move write driver supply to m1 rather than pin layer 2021-04-28 10:13:33 -07:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 01d312d65c Refactor add power pins 2021-01-13 10:57:12 -08:00
mrg 946ad66e7a Make width based on bitcell offsets, not number of columns 2020-12-18 09:22:10 -08:00
mrg 29880a0b5a Write mask and array supply pins on the ends 2020-12-17 15:25:19 -08:00
mrg e6ff73dbc1 Move supply pins for wmask and array to edge to avoid channel route congestion 2020-12-17 11:48:08 -08:00
mrg 8be1436d51 Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
mrg 8909ad7165 Update modules to use variable bit offsets. 
Bitcell arrays can return the bit offsets.
Port data and submodules can use offsets for spacing.
Default spacing for port data if no offsets given.
 2020-09-11 15:36:22 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
mrg bed2e36550 Simplify write mask supply via logic 2020-07-01 14:44:48 -07:00
mrg 66ea559209 Use channel for dffs all at once 2020-06-27 08:23:12 -07:00
Joey Kunzler 4e83e8c648 added contact to locali for wmask 2020-06-23 18:13:17 -07:00
mrg 02352c35d7 Fix hard coded layer in wmask 2020-06-14 17:10:32 -07:00
mrg 4fef632dce Fix syntax error 2020-06-05 12:13:41 -07:00
mrg a62b85a6b1 Update mirroring in port_data for bitcell mirrored arrays 2020-06-05 11:29:31 -07:00
mrg 4b526f0d5f Check min size inverter. 2020-05-13 16:54:26 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
Matt Guthaus 9ad06a7770 Move write mask vias to center to avoid data pins. 2019-12-20 11:48:27 -08:00
Matt Guthaus 82496a66fe Simplify supply code. 2019-12-20 10:35:57 -08:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
jsowash 452cc5e443 Added wmask to lib.py. 2019-09-04 09:29:45 -07:00
jsowash 1a72070f04 Removed LVS error where w_en went over whole AND array in 2 port. 2019-09-03 17:14:31 -07:00
jsowash dd67490823 Changed routing to allow for 2 write port with write mask. 2019-09-03 14:43:03 -07:00
jsowash c1906ade3f Removed A pin's via connection since it's created in the SRAM level and rearranged the SRAM flip flop creation. 2019-08-29 14:48:13 -07:00
jsowash f13c8eae8d Moved column mux ff's to be horizontal with wmask flip flops and adjusted wmask AND array en pin location starting point. 2019-08-29 11:07:42 -07:00
jsowash 5099ff6f6c Changed A/Z pins to copy_layout_pin and made en (B) pin a single pin. 2019-08-29 09:01:35 -07:00
jsowash 737e873923 Changed via direction for via1 in flip flops. 2019-08-21 14:49:54 -07:00
jsowash 980760b724 Add preferred direction to via1, routed between supply lines in wmask AND array, and only uses m3 for channel route with a write mask. 2019-08-21 14:02:57 -07:00
jsowash 4f01eeb3c1 Combined changes to the pin locations and vias. 2019-08-21 12:36:53 -07:00
jsowash c2015335b0 Fixed merge issues. 2019-08-21 11:54:22 -07:00
jsowash 4813c01d56 Moved dff's up and moved wmask_AND/wdriver pins left/down, respectively. 2019-08-21 11:50:28 -07:00
Matt Guthaus b0821a5a0e Re-add simplified power pins on edges 2019-08-21 11:42:56 -07:00
Matt Guthaus f281510828 Merge branch 'add_wmask' of github.com:VLSIDA/PrivateRAM into add_wmask 2019-08-21 11:20:42 -07:00
Matt Guthaus 2b7025335c Use pand2 of correct size. Simplify width checking of AND array. 2019-08-21 11:20:35 -07:00
jsowash 43d45fba98 Moved pwr/gnd pins to the right of the rail. 2019-08-21 10:44:04 -07:00
jsowash 71af70a636 Moved pwr/gnd vias and corrected width boundary. 2019-08-20 09:14:23 -07:00
jsowash 316132a33c Sized inverter for number of driven write drivers. 2019-08-19 13:31:49 -07:00
jsowash aaa1e3a614 Added change to route wmask en between driver and AND gates. Need to apply it to all cases. 2019-08-16 10:23:51 -07:00
jsowash 92e0671e15 Removed DRC error with AND array in freepdk45 and moved pin on en_{} pin in port data. 2019-08-15 12:36:17 -07:00
jsowash 0d7170eb95 Created wmask AND array en pin to go through to top layer. 2019-08-14 09:59:40 -07:00
jsowash aa4803f3c4 Increased enable pin's width for larger # of column mux ways. 2019-08-11 15:25:05 -07:00
jsowash d259efbcda Connected wdriver_sel between write_mask_and_array and write_driver_array. 2019-08-11 14:33:08 -07:00
jsowash d5e331d4f3 Connected en together in write_mask_and_array. 2019-08-09 14:27:53 -07:00