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OpenRAM
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3545 Commits

Author SHA1 Message Date
Matt Guthaus 93c66ec45d Update precharge section. 2018-02-12 15:38:53 -08:00
Matt Guthaus f457091bba Fix typo in precharge. 2018-02-12 15:34:01 -08:00
Matt Guthaus e32b0b8f7a Change precharge input from clk to en 2018-02-12 15:32:47 -08:00
Matt Guthaus 21967fccde Update bitcell and array section. 2018-02-12 15:30:38 -08:00
Matt Guthaus d2ed35526a Updates to intro and overview. Some edits to tech and DRC/LVS section. 2018-02-12 15:07:16 -08:00
mguthaus 18702f5f5e Add recursive Makefile clean 2018-02-12 13:37:14 -08:00
mguthaus 0e53cdd4e1 Add top-level Makefile for all technologies. 2018-02-12 13:23:22 -08:00
mguthaus 2245ecffa0 Add SCMOS library file generation. 2018-02-12 13:18:14 -08:00
mguthaus 8ea0f6be2d Fix FreePDK45 Makefile to properly organize output files to subdirs and clean. 2018-02-12 13:10:14 -08:00
mguthaus e210d3d49a Make some common lib memory sizes. Update Makefile to auto build and char them all. 2018-02-12 12:00:59 -08:00
mguthaus 636099c5e1 Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library. 2018-02-12 11:22:47 -08:00
mguthaus 6bf4190dde Fix missing tech name in path to spice models. Rename models to p,n. 2018-02-12 10:24:15 -08:00
Matt Guthaus a12ebeed9f Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken. 2018-02-12 09:33:23 -08:00
mguthaus 1795dc5677 Fix three unit tests to work with new lib corner files. 2018-02-11 20:43:41 -08:00
Michael Timothy Grimes 72fc92ad95 Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-02-11 16:47:53 -08:00
mguthaus f690532563 Add new corner-based lib files to unit tests. 2018-02-11 16:35:10 -08:00
Matt Guthaus 4dd075c7b7 Add V and C to names of lib files. 2018-02-11 16:34:32 -08:00
Matt Guthaus ce164fb7a8 Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-02-10 10:03:26 -08:00
Matt Guthaus b75eef3684 Fix syntax error. 2018-02-10 08:02:59 -08:00
Matt Guthaus 4d35972553 Get default corner options from tech file 2018-02-09 15:49:55 -08:00
Matt Guthaus f86985821a Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-09 15:33:03 -08:00
Matt Guthaus b7be042c7f Update .gitignore 2018-02-09 10:44:15 -08:00
Matt Guthaus d19867e64c Move utils to base. 2018-02-09 10:42:23 -08:00
Matt Guthaus 84c798d9e4 Move last few modules to base dir 2018-02-09 10:29:37 -08:00
Matt Guthaus 7c83ef3f04 Fix missing subdir name. Comment about organization. 2018-02-09 10:27:43 -08:00
Matt Guthaus 15747b4759 Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-02-09 10:25:28 -08:00
Matt Guthaus 7100d6f904 Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
Matt Guthaus 489faaba99 Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-02-09 10:20:56 -08:00
Matt Guthaus 13fd87d99e Accidentally committed to master. Merge branch 'master' into dev 2018-02-09 10:19:22 -08:00
Matt Guthaus d62da44329 Fix bug where path does not obey specified width. 2018-02-09 10:03:09 -08:00
mguthaus 5aa92a6549 Reorganize top-level functions a bit more. Add help info to banner. 2018-02-09 09:53:28 -08:00
mguthaus 8719a19377 Move parameter setting to config reading rather than status function. 2018-02-09 09:26:13 -08:00
Matt Guthaus f4a99be9d8 Add poly_to_field_poly rule in SCMOS 2018-02-08 16:08:20 -08:00
Matt Guthaus 3c86f94549 Change argument name for lib in tests as well. 2018-02-08 15:28:49 -08:00
Matt Guthaus d684189241 Don't output text in SRAM during unit test. 2018-02-08 14:58:55 -08:00
Michael Timothy Grimes ce83b67350 Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-02-08 14:27:53 -08:00
Michael Timothy Grimes b90f5c9a59 pbitcell is now a multiport cell with a read transistor that connects to RBL and RROW and a read access transistor that connects to Q and gnd 
current commit works without drc errors on freepdk45 but has drc rules not included in scn3me_subm. Does have lvs errors
adding several unit tests: the basic one that tests the full functionality of the pbitcell, one with no write ports, and one with no read ports
 2018-02-08 14:21:15 -08:00
Matt Guthaus 17716191c1 Clean up time statements in openram output 2018-02-08 13:11:18 -08:00
Matt Guthaus 6c89f7965d Refactor openram.py. 2018-02-08 12:47:19 -08:00
Matt Guthaus 299cffd393 Merge with 'dev'. Fix critical timing bug when column mux is present. 2018-02-08 05:15:33 -08:00
Matt Guthaus 54c21f6282 Added method=gear back to ngspice simulation to fix convergence bug. 2018-02-07 21:07:11 -08:00
mguthaus e8f658d356 Add updated non-pruned unit test results. 2018-02-07 19:35:21 -08:00
mguthaus 63ce754c72 Update unit test results 2018-02-07 18:48:22 -08:00
Matt Guthaus 1b4be741df Fix broken print statements 2018-02-07 17:39:42 -08:00
Matt Guthaus 9cc46453a2 Fix PWL bug to output last value. Fix bug in setup/hold use of improved PWL function. 2018-02-07 15:43:09 -08:00
Matt Guthaus 2413304f4e Update replica bitline test for new parameters. Add small test and a larger test. 2018-02-07 15:15:19 -08:00
Matt Guthaus 1a491f3cd0 Make temp directory unique for test 30. Update LEF files after delay chain size change. 2018-02-07 15:05:21 -08:00
Matt Guthaus e93517529c Make delay chain length and bitcell load parameters to enable tuning. Rename the parameters to be more descriptive. 2018-02-07 14:54:59 -08:00
Matt Guthaus 8e91552701 Remvoe newline. 2018-02-07 14:33:29 -08:00
Matt Guthaus 5dacafc698 Disable gear integration in ngspice. Not sure it is necessary anymore and it is quite slow. 2018-02-07 14:20:15 -08:00