Fix FreePDK45 Makefile to properly organize output files to subdirs and clean.

This commit is contained in:
mguthaus 2018-02-12 13:10:14 -08:00
parent e210d3d49a
commit 8ea0f6be2d
1 changed files with 14 additions and 12 deletions

View File

@ -4,25 +4,27 @@ TEST_DIR = ${CUR_DIR}/tests
MAKEFLAGS += -j 2
CONFIG_DIR = configs
OUT_DIRS = sp lib lef gds
OUT_DIRS = sp lib lef gds verilog
$(shell mkdir -p $(OUT_DIRS))
SRCS=$(wildcard $(CONFIG_DIR)/*.py)
SPICES=$(SRCS:.py=.sp)
all : $(SPICES)
# Characterize and perform DRC/LVS
OPTS = -c
# Do not characterize or perform DRC/LVS
#OPTS = -n
%.sp : %.py
openram.py -c $<
mv ($basename $<).lef lef
mv ($basename $<).sp sp
mv ($basename $<).gds gds
mv ($basename $<)\*.lib lib
$(eval bname=$(basename $(notdir $<)))
openram.py $(OPTS) $< 2>&1 > $(bname).log
mv $(bname).lef lef
mv $(bname).v verilog
mv $(bname).sp sp
mv $(bname).gds gds
mv $(bname)*.lib lib
clean:
find . -name \*.pyc -exec rm {} \;
find . -name \*~ -exec rm {} \;
find . -name \*.lef -exec rm {} \;
find . -name \*.lib -exec rm {} \;
find . -name \*.sp -exec rm {} \;
find . -name \*.gds -exec rm {} \;
rm -f *.log *.pyc *~ *.gds *.lib *.sp *.v *.lef
rm -f gds/* lef/* lib/* sp/* verilog/*