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OpenRAM
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111 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
mrg 77f221d859 Separate supply pin type from route supplies option 2021-05-28 11:55:50 -07:00
mrg f6587badad Improve supply routing for ring and side pins 2021-05-28 10:58:30 -07:00
mrg 8bf37ca708 Connect dnwell taps to gnd 2021-05-26 17:38:09 -07:00
mrg 7736d3b927 Fix updated side pin option 2021-05-26 16:14:46 -07:00
mrg cc91cdf008 Add power ring pin 2021-05-26 16:14:14 -07:00
mrg 7fa6c7ce0f Typo in wmask supply variable 2021-05-26 15:24:31 -07:00
mrg 4a8e0cdabb Add top-level pin functionality 2021-05-26 15:04:52 -07:00
Jesse Cirimelli-Low 0ba229afe5 Merge branch 'dev' into laptop_checkpoint 2021-05-07 19:06:17 -07:00
Jesse Cirimelli-Low e5662180e8 single port 20 series tests running 2021-05-07 18:44:45 -07:00
mrg b3948121df Default supply routing is tree. 2021-05-05 14:04:24 -07:00
mrg f48b0b8f41 Add left stripe power routes to tree router as option. 2021-05-05 13:45:12 -07:00
mrg a0e263b14a Add vdd/gnd pins to the side. 2021-05-03 15:14:15 -07:00
mrg f45efe3db6 Abstracted LEF added. Params for array wordline layers. 2021-04-21 11:04:01 -07:00
mrg a730fd0f10 Use magic for LEF abstract. Fix supply perimter pin. 2021-04-14 10:01:43 -07:00
mrg e706f776eb Offset macro to 0,0 which was accidentally comented by a PR 2021-04-13 16:24:13 -07:00
mrg 229b0059c4 Add perimeter margin to expand pins outside perimeter for OpenRoad router. 2021-04-07 16:08:29 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg 9e7c04a43a Merge lekez2005 changes WITHOUT control logic change. 2021-03-01 15:19:30 -08:00
mrg 4ab694033d Merge remote-tracking branch 'bvhoof/dev' into dev 2021-03-01 12:16:26 -08:00
Bob Vanhoof f5a9ab3b2c cleanup clutter 2021-03-01 15:23:57 +01:00
Bob Vanhoof fde8794282 calibre pex modifications to run hierarchical pex 2021-03-01 09:56:25 +01:00
ota2 9d025604ff Simulate calibre extracted netlists without requiring extra layout ports 2021-02-27 19:29:18 -05:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 69fe050bad Refactor and cleanup router grids. 2021-01-15 13:25:57 -08:00
mrg 94b1e729ab Don't add vias when placing dff array 2020-12-22 17:08:53 -08:00
mrg 52119fe3b3 Cleanup exit route. Pins are on perimeter mostly. 2020-12-22 15:56:51 -08:00
mrg 98250cf115 Copy pins as rects before removing them. 2020-12-21 13:47:05 -08:00
mrg 3c08dfcca5 Enable single pin for vdd/gnd after supply router 2020-12-18 11:09:10 -08:00
mrg d5ed45dadf Make default router tree router 2020-12-16 16:42:19 -08:00
mrg 6714e9fac0 Only run DRC and LVS at SRAM level if not a unit test to reduce run time. 2020-12-15 10:46:55 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 1e24b780bb Initial pex sram test. 2020-10-02 13:32:52 -07:00
mrg b32c123dab PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable. 2020-10-01 11:10:18 -07:00
Matt Guthaus 112d57d90a Enable riscv tests 2020-09-30 12:39:40 -07:00
mrg b147e8485c PEP8 formatting 2020-09-29 16:52:27 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
mrg 652f160aca Merge branch 'wlbuffer' into dev 2020-08-25 15:50:08 -07:00
mrg 28bd93bf51 Still working on array refactor 2020-08-25 11:50:44 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
mrg 50525e70f4 Fix up to SRAM level with new replica bitcell array ports. 2020-08-13 14:29:10 -07:00
jcirimel 02e65a00ef update pex to work with dev changes 2020-08-03 17:14:34 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg bb8157b3b7 Exit on DRC not run, check for LVSDRC before running in sram_base. 2020-07-14 08:38:49 -07:00
mrg 2011974e01 Make drc and lvs errors a member variable. Run only once. 2020-07-13 12:49:24 -07:00
mrg 8e8a97cc4b Add correct boundary to SRAM 2020-06-14 14:17:35 -07:00
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
Aditi Sinha 8bd1052fc2 Spare columns in full sram layout 2020-05-14 10:30:29 +00:00