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50 Commits

Author SHA1 Message Date
mrg 596302d9a9 Update pgate well and well contacts. 
Extend well left and right past a cell boundary.
Use asymmetric well contacts.
 2020-02-05 18:22:45 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
Matt Guthaus 89396698ef Non-preferred via in pnand active 2019-12-20 10:36:14 -08:00
Matt Guthaus 0da8164ea6 Remove some unnecessary via directions. 2019-12-19 13:54:50 -08:00
Matt Guthaus aceaa9fb21 Standardize contact names. 2019-12-17 15:55:20 -08:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Matt Guthaus 84c7146792 Fix some pep8 errors/warnings in pgate and examples. 2019-10-06 17:30:16 +00:00
Matt Guthaus 585ce63dff Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
Hunter Nichols fc1cba099c Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
Hunter Nichols 6860d3258e Added graph functions to compute analytical delay based on graph path. 2019-08-07 01:50:48 -07:00
Hunter Nichols 2ce7323838 Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
Matt Guthaus ad35f8745e Add direction to pins of all modules 2019-08-06 14:14:09 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Hunter Nichols d8617acff2 Merged with dev 2019-05-15 18:48:00 -07:00
Hunter Nichols d54074d68e Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 05ad4285af Cleanup pgate code. 
Moved create_netlist and create_layout to the pgate class
from which everything is derived. Modified all pgates
to have consistent debug output and order of init function.
 2019-04-26 12:30:42 -07:00
Hunter Nichols e292767166 Added graph creation and functions in base class and lower level modules. 2019-04-24 14:23:22 -07:00
Matt Guthaus be20408fb2 Rewrite add_contact to use layer directions. 2019-04-15 18:00:36 -07:00
Hunter Nichols 80a325fe32 Added corner information for analytical power estimation. 2019-03-04 19:27:53 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Hunter Nichols d1218778b1 Fixed merge conflicts 2019-01-28 22:33:08 -08:00
Matt Guthaus 091b4e4c62 Add size commments to spize. Change pdriver stage effort. 2019-01-23 17:27:15 -08:00
Matt Guthaus b58fd03083 Change pbuf/pinv to pdriver in control logic. 2019-01-23 12:03:52 -08:00
Matt Guthaus 5192a01f2d Convert pgates to use ptx through the factory 2019-01-16 16:30:31 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Hunter Nichols 8eb4812e16 Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model. 2018-12-17 23:32:02 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus b440031855 Add netlist only mode to new pgates 2018-11-26 15:29:42 -08:00
Matt Guthaus 5209619987 Move pnand2 output to allow input pin access on M2 2018-11-26 13:59:53 -08:00
Hunter Nichols 6e47de3f9b Separated relative delay into rise/fall. 2018-11-14 23:34:53 -08:00
Hunter Nichols b8061d3a4e Added initial code for determining the logical effort delay of the wordline. 2018-11-08 23:54:18 -08:00
Matt Guthaus ce8c2d983d Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
Hunter Nichols 5dfa8bc2c6 Fixed known typos of the word transition. 2018-09-10 14:27:26 -07:00
Matt Guthaus 6963a1092f Make bitcell width/height not static. Update modules to use it for pbitcell. 2018-09-04 11:55:22 -07:00
Matt Guthaus 6401cbf2a6 Move place function to instance class rather than hierarchy. 2018-08-27 17:25:39 -07:00
Matt Guthaus 8664f7a0b8 Converted all modules to not run create_layout when netlist_only 
mode is enabled.
 2018-08-27 16:42:48 -07:00
Matt Guthaus 19d46f5954 Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
Matt Guthaus 97c08bce95 Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. 
Shift s_en buffers even with other cells.
 2018-03-23 08:14:09 -07:00
Hunter Nichols d0dcd9f34b Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
Hunter Nichols 93ad99b9e1 Changed variable names in analytical power function to be more clear. 2018-02-28 12:32:54 -08:00
Hunter Nichols d0e6dc9ce7 First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
Hunter Nichols beb7dad9bc Added corner paramters to power functions. This commit does not compile (sorry) 2018-02-22 00:15:55 -08:00
Hunter Nichols 8ea384a761 Fixed merging issues with power branch 2018-02-14 15:21:42 -08:00
Matt Guthaus 7100d6f904 Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00