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OpenRAM
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3,836 Commits 4 Branches 63 Tags 78 MiB
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185 Commits

Author SHA1 Message Date
mrg 51ba88d896 Port address with vertical power stripes 2022-03-02 16:29:43 -08:00
mrg 0908aa9e25 Add route vertical pins 2022-03-01 14:37:09 -08:00
mrg 54bd022efc Rework precharge route supply horizontally 2022-02-28 11:36:10 -08:00
mrg 7b77378927 Add layer to horizontal pin help and use in precharge 2022-02-25 10:45:25 -08:00
mrg d4c14d7d19 Add horizontal pin helper function 2022-02-23 14:06:19 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
mrg 8d71a98ce9 Make purposes argument to gdsMill. Create prefixGDS.py script. 2021-06-22 14:40:43 -07:00
mrg cf61096936 Merge branch 'laptop_checkpoint' into dev 2021-06-04 15:22:37 -07:00
mrg 1ded978256 Change nwell from gnd to vdd. dnwell space added. 2021-06-01 15:10:55 -07:00
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
mrg 77f221d859 Separate supply pin type from route supplies option 2021-05-28 11:55:50 -07:00
mrg f6587badad Improve supply routing for ring and side pins 2021-05-28 10:58:30 -07:00
mrg 8bf37ca708 Connect dnwell taps to gnd 2021-05-26 17:38:09 -07:00
mrg 6493d1a7f4 Add dnwell 2021-05-26 16:14:16 -07:00
Jesse Cirimelli-Low f9eae3fb80 route bias pisn 2021-05-24 02:42:04 -07:00
mrg f45efe3db6 Abstracted LEF added. Params for array wordline layers. 2021-04-21 11:04:01 -07:00
mrg a730fd0f10 Use magic for LEF abstract. Fix supply perimter pin. 2021-04-14 10:01:43 -07:00
mrg 0e48e020c1 Use pins in computing bbox offsets 2021-04-13 16:24:28 -07:00
mrg bc8fd4a882 Merge branch 'supply_router' into dev 2021-01-25 11:01:48 -08:00
Matt Guthaus eebc2a93b6 Remove redundant pins when adding each pin 2021-01-25 09:36:27 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 88f2198524 Always use min area power/IO pins 2021-01-13 13:56:46 -08:00
mrg 4991693f1a Clean up min area 2021-01-13 12:32:17 -08:00
mrg 01d312d65c Refactor add power pins 2021-01-13 10:57:12 -08:00
mrg 7eb1e2f2d1 Keep previous pin shapes which were used in router pin connections. 2021-01-06 11:31:16 -08:00
mrg 94b1e729ab Don't add vias when placing dff array 2020-12-22 17:08:53 -08:00
mrg 286ac635d6 Escape router changes. 
Rename exit router to escape router.
Perform supply and signal escape routing after channel and other routing.
 2020-12-22 16:35:05 -08:00
mrg 52119fe3b3 Cleanup exit route. Pins are on perimeter mostly. 2020-12-22 15:56:51 -08:00
mrg ae1c889235 Updates to IO signal router. 
Route signals to perimeter using maze router.
Move IO pins without perimeter pins to M3 using add_io_pin (like add_power_pin).
 2020-12-22 09:39:58 -08:00
mrg 6101195b51 Function to remove layout pins. 2020-12-21 12:44:04 -08:00
mrg 878a9cee8a Add channel routes as flat instances to appease Magic extraction. 2020-12-15 16:01:39 -08:00
mrg fd118c62e5 Default zom is None not negative. 2020-12-15 13:27:36 -08:00
mrg a2ebaf9f81 Fix typo 2020-12-08 10:31:39 -08:00
mrg 35c162acbd Use internal pin names in path names for signal traces. 2020-11-19 08:45:09 -08:00
mrg fbed738b4a Merge multiple cell_name fix. 2020-11-18 16:27:28 -08:00
mrg baae28194b Add custom cell custom port order code. Update setup/hold to use it. 2020-11-17 11:12:59 -08:00
mrg 86799ae3ff Small bug fixes related to new name mapping. 2020-11-16 13:42:42 -08:00
mrg 1d729e8f02 Move pin name mapping to layout class. 2020-11-16 11:04:03 -08:00
mrg 93e94e26ec Get vdd/gnd from properties if it is defined. 2020-11-16 10:14:37 -08:00
mrg 1890385be1 Use custom cells when needed. 2020-11-03 11:58:25 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
mrg 07ef43eaf8 Convert design class data to static 2020-10-27 09:23:11 -07:00
mrg 27d921d2db Fix run-time bug for duplicate instance check 2020-10-06 16:26:35 -07:00
mrg b81cdab0d6 Use unique instance names for channel routes. 2020-10-01 07:43:06 -07:00
mrg bd125e2ed3 Check for duplicate instance names. 2020-10-01 07:17:16 -07:00
mrg c7d32089f3 Create RBL wordline buffer with correct polarity. 2020-09-17 14:45:49 -07:00
jcirimel 714b57d48e Merge branch 'dev' into pex 2020-08-17 17:48:21 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg f87b427f76 Add parent to channel route for dumpign debug gds. 2020-07-20 12:03:25 -07:00