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OpenRAM
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4,037 Commits 4 Branches 63 Tags 78 MiB
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3409 Commits

Author SHA1 Message Date
Bugra Onal 2ed107f9ff Fix the total addr_size 2022-08-04 16:36:26 -07:00
Bugra Onal 0ca14a3662 Fix typo on w_en 2022-08-04 16:35:09 -07:00
Bugra Onal 7fe0f647ef fix 2022-07-28 17:00:16 -07:00
Bugra Onal 8f955207d3 Fixed write_size checks for characterizer 2022-07-28 16:47:29 -07:00
Bugra Onal a361d9f7bb Fixed write_size checks for None 2022-07-28 16:45:58 -07:00
Bugra Onal 6efe974d7b Delete sram_base form rebase 2022-07-28 16:02:39 -07:00
Bugra Onal 9771bb7056 Don't generate wmask and if word per line is 1 2022-07-28 15:59:28 -07:00
Bugra Onal 02d8eca640 Fix indentation 2022-07-28 15:07:19 -07:00
Bugra Onal 36e23dc80f Moved template module to new modules folder 2022-07-28 15:05:34 -07:00
Bugra Onal bac40fa630 Removed SRAM directory 2022-07-28 15:04:53 -07:00
Bugra Onal caac39c88b Added 1bank module check to the multibank test 2022-07-28 15:03:41 -07:00
Bugra Onal 3f1a5a2051 Shrunk address register in multibank verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 6b5fe8a096 Changed test name for multibank verilog test 2022-07-28 15:03:41 -07:00
Bugra Onal 8f00e396cd Added unit test for multibank 2022-07-28 15:03:41 -07:00
Bugra Onal d36f74a514 Not mathcing whitespace bug fixed 2022-07-28 15:03:41 -07:00
Bugra Onal 5f45f7db15 Fixed the bad commas with post-process regex 2022-07-28 15:03:41 -07:00
Bugra Onal 9bd3f1b45a None check syntax fix 2022-07-28 15:03:41 -07:00
Bugra Onal a75951b5b1 write_size init in sram_config 2022-07-28 15:03:41 -07:00
Bugra Onal e130ba736c Fixed indent error on write_size init 2022-07-28 15:03:41 -07:00
Bugra Onal 898a1f07f5 Fixed verilog filename double extension 2022-07-28 15:03:41 -07:00
Bugra Onal a87b40e1cb Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal c1e891b2fb Multibank file generation (messy) 2022-07-28 15:03:41 -07:00
Bugra Onal 846dfc79dc modified template engine & sram multibank class 2022-07-28 15:03:41 -07:00
Bugra Onal bbcbddd934 Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal bde4a389aa Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal 9158e92a71 TEmplate rework 2022-07-28 15:03:41 -07:00
Bugra Onal a5728cdecc Base-verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 769633a459 Base template additions 2022-07-28 15:03:41 -07:00
Bugra Onal cda3822526 Verilog Template additions 2022-07-28 15:03:41 -07:00
Bugra Onal 28c5406075 Base verilog template init 2022-07-28 15:03:41 -07:00
Bugra Onal 2b1d0bd9f7 Template module done 2022-07-28 15:03:41 -07:00
Bugra Onal 0970095415 Bank select 2022-07-28 15:03:41 -07:00
Bugra Onal 859548f19f Templatable verilog file 2022-07-28 15:03:41 -07:00
Bugra Onal f08da6acc5 Fixed globals conflict 2022-07-28 15:03:41 -07:00
Bugra Onal 30f5638b9f Replaced instances of addr_size with bank_addr 2022-07-28 15:03:41 -07:00
Bugra Onal a0c6a0ad03 Set write_size default to word_size 2022-07-28 15:03:41 -07:00
Bugra Onal 29079bd6ac Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal 24bb6f8c11 Multibank file generation (messy) 2022-07-28 15:03:37 -07:00
Bugra Onal 6d6063ef4e modified template engine & sram multibank class 2022-07-21 15:56:29 -07:00
Bugra Onal a497943be3 Template section clone method 2022-07-21 15:45:50 -07:00
Bugra Onal b75e1fc499 Template section clone method 2022-07-21 15:45:50 -07:00
Bugra Onal f2cd611cb8 TEmplate rework 2022-07-21 15:45:50 -07:00
Bugra Onal 988399ba73 Base-verilog 2022-07-21 15:45:50 -07:00
Bugra Onal 06c56c256e Base template additions 2022-07-21 15:45:50 -07:00
Bugra Onal 3d3a8202fe Verilog Template additions 2022-07-21 15:45:50 -07:00
Bugra Onal be9fadf1bb Base verilog template init 2022-07-21 15:45:50 -07:00
Bugra Onal 874d965edb Template module done 2022-07-21 15:45:50 -07:00
Bugra Onal 99b517d55a Bank select 2022-07-21 15:45:50 -07:00
Bugra Onal 54a012b574 Templatable verilog file 2022-07-21 15:45:50 -07:00
mrg 6707a93c3c Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45. 2022-07-20 10:27:30 -07:00