 mrg
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2e67d44cd7
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First pass of multiple bitcells per decoder row
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2020-04-10 13:29:41 -07:00 |
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mrg
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7888e54fc4
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Remove dynamic bitcell multiple detection.
Check for decoder bitcell multiple in tech file or assume 1.
PEP8 fixes.
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2020-04-09 11:38:18 -07:00 |
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mrg
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8a55c223df
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Use single height for netlist_only mode
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2020-04-09 09:48:54 -07:00 |
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mrg
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58fbc5351a
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Change rows to outputs in hierarchical decoder
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2020-04-08 17:05:16 -07:00 |
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|
mrg
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745450fadc
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Syntax error
|
2020-04-08 17:04:50 -07:00 |
|
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mrg
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cddfaa0dc8
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Tech dependent fudge factor
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2020-04-08 17:04:14 -07:00 |
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mrg
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ade3b78711
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Add exception errors file
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2020-04-08 16:55:45 -07:00 |
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mrg
|
0c27942bb2
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Dynamically try and DRC decoder for height
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2020-04-08 16:45:28 -07:00 |
|
 Hunter Nichols
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4103745de2
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Merged with dev, fixed conflict in ptx
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2020-04-08 02:33:05 -07:00 |
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|
Hunter Nichols
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95363856e4
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Added logical effort and input load for ptx module.
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2020-04-08 02:29:57 -07:00 |
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mrg
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a3797094d0
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Swap lvs and sp dimensions for s8
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2020-04-07 10:37:49 -07:00 |
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mrg
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c8c74e8b69
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Fix lvs_write in sram class
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2020-04-06 15:20:59 -07:00 |
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mrg
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f20246abdc
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-04-06 14:08:45 -07:00 |
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mrg
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cd8dc8e20b
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Output lvs model instead of spice model
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2020-04-06 14:08:38 -07:00 |
|
 Jesse Cirimelli-Low
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b59c789dec
|
remove whitespace
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2020-04-05 03:58:26 -07:00 |
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|
Jesse Cirimelli-Low
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beef9441b7
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fix pin check debug typo
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2020-04-05 02:55:15 -07:00 |
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|
Jesse Cirimelli-Low
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8b33cb519f
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Merge branch 'dev' into custom_mod
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2020-04-03 17:05:56 -07:00 |
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mrg
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ab5dd47182
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Ptx is in microns if lvs_lib exists
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2020-04-03 14:06:56 -07:00 |
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mrg
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f358de78bb
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Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation)
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2020-04-03 13:39:54 -07:00 |
|
|
mrg
|
8603d3edd6
|
PEP8 cleanup
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2020-04-03 11:37:06 -07:00 |
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|
mrg
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2850b9efb5
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Don't force check in lib characterization. PEP8 formatting.
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2020-04-02 12:52:42 -07:00 |
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|
mrg
|
f105c9ab36
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Netlist only in verilog test
|
2020-04-02 12:43:19 -07:00 |
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mrg
|
1d5e5e3607
|
Don't run lvs/drc or route supplies in verilog test
|
2020-04-02 12:42:28 -07:00 |
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|
mrg
|
67de7efd49
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Fix syntax error. No DRC/LVS in netlist only mode.
|
2020-04-02 11:31:28 -07:00 |
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|
mrg
|
9106e22b58
|
Fix typo and syntax error.
|
2020-04-02 10:37:21 -07:00 |
|
|
mrg
|
5349323acd
|
PEP8 cleanup. DRC/LVS returns errors.
|
2020-04-02 09:47:39 -07:00 |
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|
mrg
|
0d6c84036d
|
Adjust fudge factor for pin spacing.
|
2020-04-02 09:47:13 -07:00 |
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|
mrg
|
a3683c5898
|
Separate pbitcell from hierarchical decoder
|
2020-04-01 16:39:47 -07:00 |
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|
mrg
|
a9d3548be1
|
Refactor drc/lvs error output
|
2020-04-01 15:54:06 -07:00 |
|
|
Jesse Cirimelli-Low
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cdf0315a90
|
Merge branch 'dev' into custom_mod
|
2020-04-01 15:35:33 -07:00 |
|
|
mrg
|
3b662026d2
|
pnand3 constant hack for input separation
|
2020-04-01 11:36:04 -07:00 |
|
|
mrg
|
7956b63d9f
|
Add licon option to precharge
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2020-04-01 11:26:45 -07:00 |
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|
mrg
|
3e41664db6
|
Split precharge array to multiport and normal cell
|
2020-04-01 11:26:31 -07:00 |
|
|
mrg
|
3074cf3b86
|
Small format cleanup
|
2020-04-01 11:15:29 -07:00 |
|
|
mrg
|
da334e47aa
|
Separate pbitcell tests for precharge
|
2020-04-01 11:14:50 -07:00 |
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|
mrg
|
bc9cbe70a7
|
Poly overlap doesn't convert to tx device
|
2020-04-01 09:42:07 -07:00 |
|
|
Jesse Cirimelli-Low
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6e2a5d7a1a
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set sram output cap in characterizer to be 4x dff input cap
|
2020-04-01 04:24:43 -07:00 |
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|
mrg
|
d916322b74
|
PEP8 updates
|
2020-03-31 10:15:46 -07:00 |
|
 Joey Kunzler
|
b0d2946c80
|
update to sense amp and write driver modules
|
2020-03-30 20:00:32 -07:00 |
|
|
mrg
|
9907daaffa
|
Min area only for multiple layers
|
2020-03-26 13:05:02 -07:00 |
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|
mrg
|
d2c97d75a7
|
Add well contact and min area to power pin of precharge
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2020-03-26 11:49:32 -07:00 |
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|
mrg
|
1e3734cb26
|
Hack to fix pnand3 in freepdk45
|
2020-03-26 11:08:53 -07:00 |
|
|
Jesse Cirimelli-Low
|
341bde7a48
|
Merge branch 'dev' into custom_mod
|
2020-03-26 02:40:37 -07:00 |
|
|
mrg
|
2f353187ba
|
Skywater extraction mode for si unit scales
|
2020-03-24 12:41:15 -07:00 |
|
|
mrg
|
1e2163c3a6
|
Hack for pnand3 pin spacing
|
2020-03-24 12:40:41 -07:00 |
|
|
mrg
|
e9d0db44fd
|
Add li_stack contact to ptx and pgate if it exists.
|
2020-03-23 16:55:38 -07:00 |
|
|
mrg
|
f491876a5a
|
Move up B input in pnor2
|
2020-03-23 13:49:08 -07:00 |
|
|
mrg
|
c15b4167b6
|
Merge branch 'dev' into tech_migration
|
2020-03-23 11:57:03 -07:00 |
|
|
mrg
|
f598a359d5
|
Remove unused contact in pnor2
|
2020-03-23 11:55:17 -07:00 |
|
|
mrg
|
717cbb0fe5
|
Remove unused contact in pnand3
|
2020-03-23 11:52:19 -07:00 |
|